JP2000293437A - Cache memory device and cache memory control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To implement substitute algorithm by a programmer by selecting a cache set or its group when a specific value is stored in the specific bit area of an entry of a high-speed converting buffer mechanism. SOLUTION: The high-speed converting buffer mechanism (TLB) 41 of a memory management (MMU) 4 has multiple entries, which is each stored with a virtual page address VPN, a physical page address PFN, an effective bit V, and extension C bits so that they correspond to one another. The extension C bits are information obtained by adding information specifying a cache set to information of the C bits indicating a conventional cache coherency property. Then a selector 5 selects one of 0th and 1st cache sets 31 and 32 according to the value of the extension C bits included in data outputted from the MMU 4. Further, a controller 6 makes one of the 0th and 1st cache sets 31 and 32 active when the extension C bits are '11'.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory device, and more particularly, to providing a TLB entry with a bit area designating a cache set in which a replacing process is to be performed, thereby realizing means for implementing a replacement algorithm by a programmer. The present invention relates to a processor having a cache memory device.

[0002]

2. Description of the Related Art In many information processing apparatuses, a large virtual address space is used to logically expand a memory space in order to supplement a small physical memory. As means for accessing this extended address space at high speed, TLB is used.
(Table Look-up Buffer; high-speed conversion buffering mechanism) and a method of using a cache memory are generally used. The TLB is a high-speed address converter for converting an address (virtual address) in a virtual address space into a physical address at a high speed.

A cache memory is a high-speed memory that stores a copy of the contents stored in the main memory in order to increase the apparent speed of accessing the main memory that operates at a relatively low speed.

[0004] The TLB stores a look-up table having conversion information into a virtual address and a physical address. A memory or a register which is faster than a cache memory, and refers to this table by a virtual address to obtain a corresponding data. Whether or not is stored in the cache memory,
If stored, the physical address is read. When converting the virtual address to the final physical address, other address conversion means covering the TLB may be used.

In order to effectively use a cache memory having a limited capacity as in the configuration of the conventional cache memory device shown in FIG.
A coherency designation bit for designating coherency attribute information may be added.

In the case of the conventional example shown in FIG. 6, if the coherency designation bit is 1, control based on the ordinary cache attribute, that is, control of the cache including replacement logic (replacement algorithm) is performed.

If the coherency designation bit is 0, control based on the uncache attribute, that is, control not using a cache, is performed.

In the above, the replacement logic (replacement algorithm) is an algorithm for determining which block should be evicted when there is no free space in the cache. This decision may include statistical information about past accesses, empirical rules such as locality of reference data, or
The specification of the block priority is referred to. These decisions are related to increasing the cache hit rate.

For example, permutation logic (replacement algorithm) in a processor generally includes:
There is a distinction between replacement logic for cache memories and replacement logic for TLB entries (the invention relates to replacement logic for cache memories).

The most frequently used cache replacing algorithm is the so-called LRU (LRU).
east recently used) algorithm. That is, a control is generally performed so that the most recently referenced block is not replaced.

However, in recent years, not only the replacing algorithm but also the need to cope with the case where the optimal control method relating to the replacement is known a priori, an instruction set (usually a load instruction) in a program has been required. In addition, there is a policy to provide means for realizing the optimal control method.

As a prior application based on such a policy, Japanese Patent Application Laid-Open No. 4-338848 discloses a TLB entry.
A technique of providing a replacement prohibition flag for designating prohibition of replacement (prohibition of eviction) of the TLB entry is disclosed.

Japanese Patent Application Laid-Open No. 6-348595 discloses means for providing a replacement prohibition flag for prohibiting replacement of a plurality of cache sets, and a replacement prohibition flag for each of the plurality of cache sets. Have been disclosed that have a means for selecting one eviction entry by integrating the eviction entries.

Furthermore, Japanese Patent Application Laid-Open No. 7-28706 discloses a technique for setting an area for designating the priority of a cache line in a cache line in the cache.

[0015]

In the LRU algorithm under the cache attribute in the conventional cache device, the block to be replaced is determined based on the frequency of cache access as the sole determinant. Therefore, a cache set (a set of caches) storing the block is automatically determined. Therefore, when undesired unmatches occur in the consistency between the cache state and the execution program, it is better not to replace, but instead, it is replaced. May be good but not replaced. As a result, a phenomenon called thrashing occurs, and a number of replacements that are originally unnecessary may occur frequently, and the processing performance may decrease.

A compiler with an optimization phase, O
Even when the code optimized using S is used, the optimization may not be effective depending on the cache state as described above.

That is, in the prior art, when the need for replacement in the cache arises, the cache set to be replaced is forcibly specified according to a system-specific replacement algorithm (usually LRU logic). You. The cache set to be replaced cannot be dynamically specified from an execution program generated by a compiler or the like having an optimization phase. For this reason, the above-mentioned replacement often occurs, and the processing performance may be reduced.

Therefore, in the present invention, as a mode different from the mode to which the conventional replacing algorithm is applied, means for designating a cache set to be replaced from an instruction set (usually a load instruction) on an execution program is provided. Giving was considered.

The technique disclosed in Japanese Patent Application Laid-Open No. 4-338848 is not a technique for selecting any one of a plurality of cache sets corresponding to a block for which eviction prohibition is specified.

The technique disclosed in Japanese Patent Application Laid-Open No. 6-348595 does not use a TLB and, like the above-mentioned publication, uses any of a plurality of cache sets corresponding to a block for which eviction prohibition is specified. It is not a technology to choose.

Further, the technique disclosed in Japanese Patent Application Laid-Open No. 7-28706 does not use the TLB similarly to the above-mentioned publication, and specifies a priority instead of a prohibition of eviction.

The present invention has been made in view of the above-mentioned problems in the conventional cache memory device, and provides a cache memory device and a method thereof capable of realizing a means for executing a replacement algorithm by a programmer. The purpose is to:

[0023]

In order to solve the above-mentioned problems, a cache memory device according to a first aspect of the present invention includes a set associative cache memory having a plurality of cache sets, and a virtual address storage device. A virtual memory type processor having a high-speed translation buffer mechanism having a correspondence between a part and an entry in the cache memory as address translation information, and a cache memory device including a control circuit for executing replacing control with a predetermined replacement logic. In the above, each entry of the high-speed conversion buffer mechanism has a designated bit area for storing a designated value that designates a cache set or a group of cache sets in the cache memory device for data of a block corresponding to the entry. , The control circuit includes an input of the high-speed conversion buffer mechanism. The designated bit region of, when the designated value is stored, selects a group of the specified cache set or cache set by the specified value, characterized in that.

According to this configuration, it is possible to directly designate a cache set or a group of cache sets in the cache memory by the designation bit. The designation bits can provide the programmer with a means for implementing the optimum control method when the programmer knows the optimum control method for the block corresponding to the entry.

The specified bit area of the entry of the high-speed conversion buffer mechanism includes information for specifying whether the entry uses a cache memory, for example, a bit indicating a cache coherency attribute, a cache set to be used, or a cache set of the cache set. Information for selecting a group may be stored.

In this case, the size of the designated bit area of the entry of the high-speed conversion buffer mechanism means both information for specifying a cache set or a group of cache sets and information for indicating a cache coherency attribute. The number of bits can be set as necessary and sufficient. With such a bit configuration, the required number of bits of each entry of the high-speed conversion buffer mechanism can be reduced as compared with the case where both are designated in different areas.

An address for storing data in units of blocks and for associating a virtual address and a physical address of data of each block with a designated value indicating which cache set or group of cache sets the block uses. A main memory for storing the conversion table may be arranged. The control circuit, when a miss occurs in the cache device, determines a physical address in the main memory of the data to be accessed, a block data located at the determined physical address, a cache set indicated by a specified value or Replace with a group of cache sets.

When loading data into the main memory,
Means for storing, in the address translation table, a virtual address of a data block to be loaded, a physical address in main memory, and a designated value indicating which cache set or group of cache sets the block uses, May be provided. According to this configuration, when data is loaded into the main memory or the like, a cache set or a group of cache sets into which the block is loaded can be specified by the specified value.

By setting the same designated value to a data block having substantially the same capacity as the cache set or the cache set group, the cache set or the cache set group is used as a high-speed memory that does not cause replacement. can do.

When the specified value specifies a group of cache sets, for example, two cache sets, the control circuit converts the cache sets in the specified group according to a predetermined replacement logic, for example, an LRU algorithm. May be selected to perform the replacement process. In this case, it is possible to compromise between the function of performing the replacement process by specifying the cache set and the function of performing the replacement process by applying the conventional replacement logic.

The designated value in the designated bit area of the entry in the main memory may be stored by executing a predetermined instruction set in an execution program.

A cache memory device according to a second aspect of the present invention includes a set associative cache memory having a plurality of cache sets, a main memory for storing data in block units, and a data memory in the main memory. Means for setting, for the data block, designation data for designating a cache set or a group of cache sets of the cache memory used by the data block; and setting the data block on the main memory to A control unit for selecting a cache set or a group of cache sets according to corresponding designated data when storing the data block in the cache memory, and storing the data block in the selected cache set.

According to this configuration, a cache set for storing data on the main memory can be specified.
By appropriately setting the designated data, the hit rate of the cache memory can be improved.

A cache memory device according to a third aspect of the present invention has a main memory for storing data in block units, a cache memory having a plurality of cache sets and storing a copy of data on the main memory. Address conversion means for converting a virtual address into a physical address, and control for replacing data in the cache memory with data in the main memory in units of blocks by a predetermined replacement logic when a cache mishit occurs. Wherein the address translation means includes, for each block of data, designation information for designating a cache set or a group of cache sets in the cache memory device, wherein the control circuit For the data block of If the information is set by selecting a group of the specified cache set or cache set by the designation information, to replace the data of the corresponding block, and wherein the.

The specification information may include information for specifying whether or not the corresponding data block uses the cache memory and information for selecting a cache set or a group of cache sets to be used.

The address conversion means is, for example, arranged on the main memory, and specifies a virtual address and a physical address of data of each block and a designated value indicating which cache set or group of cache sets the block uses. And a high-speed conversion buffer mechanism for storing a copy of the address conversion table.

Means for converting the supplied virtual address into a physical address by the high-speed translation buffer mechanism, and converting the virtual address into a physical address by using an address translation table in the event of a mishit in the high-speed translation buffer mechanism; And an access unit for accessing the cache memory using a physical address converted by a mechanism or an address conversion table, wherein the cache memory accessed by the access unit is configured to perform the control when a cache miss occurs. The circuit may replace the block data on the main memory located at the determined physical address with the cache set or the cache set group indicated by the specified value.

A cache memory control method according to a fourth aspect of the present invention includes a set associative cache memory having a plurality of cache sets;
A cache memory control method for controlling a cache memory device including a high-speed translation buffer mechanism having a correspondence between a part of a virtual address and an entry in the cache memory as address translation information, wherein each entry of the high-speed translation buffer mechanism is controlled. A designation bit area for storing a designation value for designating a cache set or a group of cache sets in the cache memory for data of a block corresponding to the entry; When the specified value is stored in the bit area, a cache set or a group of cache sets specified by the specified value is selected.

Each data block on the main memory may have a designated bit added thereto in advance by a compiler, an OS, a load program, or the like, before the data block is replaced.

When the designated bit designates a cache set group, the cache set in the group may be selected by a predetermined replacement logic to perform a replacement process. In this case, it is possible to partially compromise the function of performing the replacement processing by designating the cache set and the function of performing the replacement processing by applying the conventional replacement logic such as LRU.

[0041]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a diagram showing a configuration of a computer device according to a first embodiment of the present invention. As shown in the figure, this computer device includes a CPU (Central Processing Unit) 1, a main memory 2, a cache memory 3
, An MMU (memory management unit) 4, a selector 5, a controller 6, and a plurality of peripheral devices 7.

The CPU 1 is a processing device which is a core of the computer device. The main memory 2 is a volatile memory for storing various programs, data, and the like.
An address conversion table 21 for converting a virtual address (logical address) into a physical address (a storage position on the main memory 2) is provided.

The cache memory 3 is a high-speed memory, such as an SRAM, which can be accessed at a higher speed than the main memory 2 and stores a copy of data, programs, and the like on the main memory 2. The cache memory 3 is
Cache set 31 and first cache set 32
And a control circuit (cache control circuit) 39. Each cache line of the 0th cache memory 31 and the first cache memory 32 has a valid bit V
, A tag (physical tag) Tag, and data Data. The cache control circuit 39 determines the 0th cache set 3 according to the data supplied from the MMU 4.
The first or first cache set 32 is accessed, and a replacement process is performed as necessary.

The MMU 4 is for managing access to the main memory 2, the cache memory 3, and the like in response to a request for access by a virtual address from the CPU 1 or the like, and includes the TLB 41.

As shown in FIG. 2, the TLB 41 has a plurality of entries, and each entry has a virtual page address VPN (Virtual Page Number).
And the physical page address PFN (Page Frame)
Number), a valid bit V, and an extended C bit are stored in association with each other.

The virtual page address VPN is the address of a page which is a data block of a predetermined size (contents are an instruction code, data, etc.) in the referenced virtual space.
It consists of the upper bits of the virtual address. The physical page address PFN is the address of the physical area where the corresponding data block is stored, and is composed of the upper bits of the physical address. The valid bit V is a bit indicating whether the content of the entry is valid or invalid.

The extended C bit is information obtained by adding information designating a cache set to C (Coherency) bit information indicating a conventional cache coherency attribute. In the present embodiment, the extension C bit is "
The case of "00" is the same as the case where the C bit of the conventional cache shown in FIG. 6 is "0", indicates the uncache attribute, and the data block (page) corresponding to the entry does not use the cache.

When the extension C bit is "11", it is the same as the case where the C bit of the conventional cache shown in FIG. 6 is "1". 1 cache set 31,
32, the one in the area corresponding to the physical address is selected and used.
One of the zeroth or first cache set 31, 32 is selected and used based on the RU algorithm.

When the above-mentioned extended C bit is “01”, the selector 5 sets the 0th cache set 11 when the extended C bit is “01” and the first cache set when it is “10”.
Each of the cache sets 32 is selected.

The value of the above-mentioned extended C bit can be set by an instruction set in a program, usually, a load instruction for loading the address information of the block to be referenced from the address conversion table 21 into the cache memory 3. is there. When data is loaded into the main memory 2, an extended C bit may be set on the address conversion table 21 in advance. Further, the user may set the extended C bit for the data block in the specific area on the main memory 2 by using a special tool.

The selector 5 selects one of the 0th cache set 31 and the first cache set 32 according to the value of the extended C bit included in the data output from the MMU 4.

The controller 6 controls the operation of the main memory 2 and the peripheral circuit 6 based on the supplied address and the like. When the above-mentioned extended C bit is “11”, the controller 6 activates one of the zeroth cache set 31 and the first cache set 32.

The peripheral device 7 includes a disk device, a display device, and the like.

FIG. 3 shows an example of an address conversion table 21 of a type in which the extension C bit is set in advance. As shown in the figure, the address conversion table 21 includes a plurality of entries, and in each entry, a virtual page address, a physical page address, and an extended C bit are registered in association with each other.

Each extended C bit is set according to the purpose of use of the 0th cache set 31 and the first cache set 32.
It can be set arbitrarily by user's individual setting, execution of assembler, execution of compiler, etc.

For example, when executing a program,
When data of a specific area on the main memory 2 is made to reside in the 0th cache set 31 or the first cache set 32, "01" or "01" is set in the extended C bit of the area.
10 ". When a certain program is executed, all the extended C bits of the area of the same size as the 0th cache set 31 on the main memory 2 are set to" 01 ", and the first cache set 32 By setting all the extension C bits of the same size area to “10”, the 0th cache set 31 and the 1st cache set 32 can be used as a high-speed memory that does not cause replacement.

When the cache memory 3 is used, the probability of a mishit is very high, and if the efficiency is reduced by frequent replacement,
It is also effective to set the extended C bit to “00” so that the cache memory 3 is not used.

Further, when replacing the contents of the cache memory 3 based on the normal LRU algorithm, the extension C bit is set to "11".

Hereinafter, the operation of the cache memory device according to the present embodiment will be described with reference to FIG. CPU1
In order to access the main memory 2, the upper address (virtual upper address) VP of the virtual address output to the MMU 4
N (Virtual Page Number) is TL
B41 which is inputted to B41 and which matches the inputted virtual upper address VPN among the plurality of entries of TLB41.
It is determined whether there is a TLB entry having N. If the corresponding entry exists, it is determined whether or not the valid bit V indicates “1” (valid).

If there is a TLB entry having a VPN that matches the input virtual upper address VPN and the valid bit V of the entry indicates 1 (valid), it is a TLB hit. In this case, MMU4
By linking the physical page address PFN registered in the corresponding entry and the lower address (in-page address) of the virtual address, a physical address is obtained and output together with the C bit.

On the other hand, in the case of a TLB miss, the MMU
Reference numeral 4 refers to the address translation table 21 on the main memory 2 via the controller 6, detects an entry having a VPN that matches the virtual higher-order address VPN output by the CPU 1 to the MMU 4, and fetches the contents. MMU4
Concatenates the physical page address PFN registered in the fetched entry with the lower address, obtains the physical address, and outputs it together with the extended C bit. In addition, TLB
In the case of a mishit, the table in the TLB 41 can be replaced with the contents of the address translation table 21 according to the TLB replacement algorithm.

When the extended C bit output from the MMU 4 is "0"
0 ”, that is, when the uncache attribute is specified, the selector 5 sets the 0th cache set 31
And the first cache set 32 are not enabled (not selected). Therefore, access to the cache memory 3 is not performed. The MMU 4 controls the main memory 2 designated by the physical address via the controller 6.
Access the upper position to read data or write data.

On the other hand, when the extension C bit output from the MMU 4 is “01”, the selector 5 activates only the 0th cache set 31. The cache control circuit 39 determines that the tag of the cache line of the 0th cache set 31 corresponding to the lower address matches the upper address of the physical address supplied from the MMU 4 and that the valid bit V is “1” (valid). It is determined whether or not there is, that is, whether or not the cache hits on the 0th cache set 31.

When determining that there is a cache hit, the cache control circuit 39 accesses (reads and writes data) the cache line based on the physical address.

On the other hand, in the case of data reading, when the cache control circuit 39 determines that there is a cache mishit, the MMU 4
To that effect. In accordance with this notification, MMU 4
Data corresponding to the physical page address is read from the main memory 2 via the controller 6 and supplied to the cache memory 3. The cache control circuit 39 copies (replaces) the data read from the main memory 2 to the 0th cache set 31 selected by the selector 5. The MMU 4 reads data from the replaced cache line of the 0th cache set 31.

In the case of data writing, when the cache control circuit 39 determines that there is a cache mishit, it writes the 0th cache set 31 selected by the selector 5 and notifies the MMU 4 at the same time. I do. According to this notification, the MMU 4 writes data corresponding to the physical page address of the main memory 2 via the controller 6.

On the other hand, when the extension C bit output from the MMU 4 is “10”, the selector 5 activates only the first cache set 32 according to the extension C bit. The cache control circuit 39 has a tag corresponding to the upper address (PFN) of the physical address supplied from the MMU 4, and the cache line whose valid bit V is "1" (valid) is in the active state.
Whether it exists on the cache set 32, that is,
It is determined whether a cache hit occurs on the first cache set 32 or not.

If the cache control circuit 39 determines that there is a cache hit, the cache control circuit 39 accesses (reads and writes data) the cache line.

On the other hand, if the cache control circuit 39 determines that there is a cache miss, it notifies the MMU 4 to perform cache replacement.

The MMU 4 reads the data block indicated by the physical address (PFN) from the main memory 2 via the controller 6 according to the notification, and supplies the data block to the cache memory 3. The cache control circuit 39 copies (replaces) the data block read from the main memory 2 to the first cache set 32 selected by the selector 5. The MMU 4 reads data from the replaced cache line of the first cache set 32 or writes data to the cache line.

On the other hand, when the extended C bit output from MMU 4 is “11”, cache control circuit 39
The cache line having a tag corresponding to the upper address of the physical address supplied from No. 4 and having a valid bit V of “1” (valid) is one of the 0th cache set 31 and the first cache set 32. It is determined whether or not it exists. It has a tag corresponding to the physical address supplied from the MMU 4 and has a valid bit V
If it is determined that a cache line with "1" (valid) exists in either of the cache sets, it is a cache hit. The cache control circuit 39 accesses the cache line.

If the cache line having the tag corresponding to the physical address supplied from the MMU 4 does not exist in either the 0th cache set 31 or the first cache set 32, or if it exists, the valid bit If V is "0" (invalid), it is a cache miss hit. In this case, the cache control circuit 39 notifies the MMU 4 to perform cache replacement.

In accordance with this notification, the MMU 4 reads the corresponding data block from the area indicated by the physical page address of the main memory 2 via the controller 6 and supplies the data block to the cache memory 3. The cache control circuit 39 stores the data block read from the main memory 2 in the 0th cache set 31 according to the LRU replacement logic.
The first cache set 32 is copied (replaced) on the data block that has been used the oldest. M
The MU 4 reads data from the replaced cache line or writes data to the cache line.

As described above, according to this embodiment, the cache is not used for each data block (page) in the main memory 2 by individual processing using a tool, setting of a compiler, processing of a loading program, and the like. ,
One of the use of only the 0th cache set 31, the use of only the first cache set 32, and the selection of a cache set by the LRU can be set. That is, since a cache set to be replaced can be directly specified, or a cache set can be selected by an LRU algorithm and replaced with the cache set, a cache structure such as allocating a specific set of cache to an arbitrary data block can be used. Optimized code can be created independently of the state of the cache.

When specific data (group) is assigned to an arbitrary cache set, replacement due to cache mishit can be eliminated, and high-speed access to the memory becomes possible. Through such optimization, the hit rate of the cache memory can be manipulated, and the performance can be improved.

(Second Embodiment) FIG. 5 is a block diagram showing an overall configuration of a cache memory device according to a second embodiment of the present invention. In the above-described first embodiment, two cache sets are provided, and the extended C bit specifies one of the two cache sets. In the present embodiment, the extension C bit is extended so that a cache set can be specified or a group of cache sets can be specified.

In the configuration shown in FIG. 5, the extended C bit is 3 bits. In general, however, information obtained by adding information specifying a cache set or specifying a cache set group to information indicating a conventional cache coherency attribute is used. And the number of bits necessary and sufficient to indicate This extended C bit is also set in each entry of the address conversion table of the main memory.

Hereinafter, the operation of the cache memory device according to the present embodiment will be described with reference to FIG. The upper address VPN of the virtual address output by the CPU 1 is TLB4
1 is input. In the case of a TLB hit, the physical page address PFN corresponding to the upper address and the lower address are connected to obtain a physical address, which is output together with the C bit.

On the other hand, in the case of a TLB miss, the physical page address PFN corresponding to the virtual upper address VPN is referred to by referring to the address conversion table 21 in the main memory 2.
Is obtained, the obtained physical page address PFN and the lower address are concatenated to obtain a physical address, which is output together with the extended C bit.

When the extension C bit is “000”, un
This is the case where the cache attribute is specified, and the selector 5 does not enable any of the 0th cache set 31 to the third cache set 34. MMU4
Accesses the main memory 2 via the controller 6,
Read data or write data.

When the extension C bit is “001”, the selector 5 sets only the 0th cache set 31 to the active state. The cache control circuit 39 determines whether or not the cache hits on the 0th cache set 31. In the case of a cache hit, the cache control circuit 3
9 accesses the 0th cache set 31.

On the other hand, in the case of a cache miss, the cache control circuit 39 notifies the MMU 4 of the cache miss to perform cache replacement. According to this notification, the MMU 4 reads the corresponding data block from the main memory 2 via the controller 6, and
The data is supplied to the cache memory 3. Cache control circuit 3
9 copies the data block read from the main memory 2 to the 0th cache set 31.

If the extension C bit is "010", the selector 5 activates only the first cache set 32, and if a cache hit occurs, the access is made to the first cache set 32 and a cache miss occurs. If so, the corresponding data block is read from the main memory 2 and replaced in the first cache set 32.

When the extension C bit is "011", the selector 5 activates only the second cache set 33, and if a cache hit occurs, the second cache set 33 is accessed and a cache miss occurs. If so, the corresponding data block is read from the main memory 2 and replaced in the second cache set 33.

When the extension C bit is "100", the selector 5 activates only the third cache set 34, and if a cache hit occurs, the third cache set 34 is accessed. If a cache miss occurs, the corresponding data block is read from the main memory 2 and replaced in the third cache set 34.

Next, when the extension C bit is “101”, the selector 5 activates the 0th cache set 31 and the first cache set 32. The cache control circuit 39 controls the 0th cache set 31 or the 1st cache set.
It is determined whether or not the cache hits on the cache set 32. That is, a cache line having a tag corresponding to the physical upper address supplied from the MMU 4 exists on the 0th cache set 31 or the first cache set 32, and the valid bit V of the cache line is “1” ( Valid).

In the case of a cache hit, the cache control circuit 39 accesses the hit 0th or first cache set 31 or 32.

On the other hand, in the case of a cache miss, the cache control circuit 39 notifies the MMU 4 of the cache miss in order to perform cache replacement. In accordance with this notification, the MMU 4 reads a data block from the area of the main memory 2 indicated by the physical higher address PFN via the controller 6 and supplies the data block to the cache memory 3. The cache control circuit 39 stores the data block read from the main memory 2 in the uppermost one of the 0th cache set 31 and the first cache set 32 according to the LRU replacement rule. Copy to

Next, when the extension C bit is "110", the selector 5 activates the second cache set 33 and the third cache set 34. The cache control circuit 39 controls the second cache set 33 or the third
It is determined whether or not the cache hits on the cache set 34.

If the hit is a cache hit, the cache control circuit 39 accesses the hit second or third cache set 33 or 34.

On the other hand, in the case of a cache miss, the cache control circuit 39 reads a data block from the area specified by the physical upper address PFN of the main memory 2 via the MMU 4 and the controller 6, and according to the LRU replacement rule. Copy to one of the second cache set 33 and the third cache set 33.

Further, when the extension C bit is "111", the selector 5 activates the 0th cache set 31 to the third cache set 34. The cache control circuit 39 determines whether or not a cache hit occurs on the 0th cache set 31 to the third cache set 34.

If the hit is a cache hit, the cache control circuit 39 accesses the hit cache set.

On the other hand, in the case of a cache miss, the cache control circuit 39 notifies the MMU 4 of the cache miss to perform cache replacement. In accordance with this notification, the MMU 4 reads a data block from the area of the main memory 2 indicated by the physical higher address PFN via the controller 6 and supplies the data block to the cache memory 3. The cache control circuit 39 converts the data block read from the main memory 2 into the oldest used data block among the 0th cache set 31 to the third cache set 34 according to the LRU replacement rule. Copy above.

According to the configuration of the second embodiment, it is also possible to specify a cache set used by each data block or a group of cache sets independently of the state of the cache, and to optimize and use the cache. Can be. Further, by grouping the cache sets, it is possible to perform control that is more finely optimized for the cache structure. In addition, a replacement algorithm such as ordinary LRU logic can be applied to blocks in a group of the grouped cache sets.

In each of the above embodiments, the designation bit of the cache set or the group of the cache set is set by extending the C bit indicating the conventional cache coherency attribute.
Both can be set as separate areas in the LB entry or the address translation table entry.

In each of the above embodiments, the method of setting a specified value for specifying a cache set or a group of cache sets in the address translation table on the main memory can be arbitrarily changed. For example, in the address conversion table 21 on the main memory 2, the extension C bit is not arranged, and a copy of the address conversion table is written in TLB.
, The extended C bit may be set.

In the first and second embodiments, when the cache memory 3 is accessed, the selector 5 activates only the cache set corresponding to the extended C bit. With all cache sets active, cache hits and mishits are determined, and only at the time of replacement processing,
The selector 5 may be operated.

[0099]

As described above, according to the cache memory device of the present invention, it is foreseen that, for example, a cache miss (frequent occurrence of unnecessary replacing processing) or a cache miss will occur. In this case, the cache set to be replaced is specified directly from the program, and in some cases, the normal L
A replacement algorithm for RU logic can be implemented.
Therefore, it is possible to generate code optimized for the cache structure, such as forcibly assigning a specific cache set to an arbitrary block by a compiler or the like,
Thus, optimal cache control can be performed without depending on the cache state.

By allocating a specific block, which is predicted to be a block with a high reference frequency, to any one of the cache sets, the replacing process due to a cache miss is eliminated and the cache set is occupied. Therefore, with respect to the subsequent access to the block, the external memory access requires 1
Where eight clocks are required per cycle, zero clocks can be used.

By optimizing such cache control, it is possible to improve the cache hit ratio and contribute to the improvement of the performance of the information processing apparatus. Further, by grouping the cache sets, it is possible to generate a code that is more finely optimized for the cache structure, and to apply a control that does not depend on the cache state. In addition, a normal LRU logic replacement algorithm can also be partially applied to blocks within a group of cached sets.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a cache memory device according to a first embodiment of the present invention.

FIG. 2 illustrates an example of a TLB entry.

FIG. 3 is a diagram showing an example of an address conversion table formed on a main memory.

FIG. 4 is a diagram for explaining an operation of the cache memory device according to the first embodiment of the present invention.

FIG. 5 is a block diagram illustrating an operation of a cache memory device according to a second embodiment of the present invention.

FIG. 6 is a block diagram showing an overall configuration of a conventional cache memory device.

[Explanation of symbols]

 1 CPU 2 Main Memory 3 Cache Memory 4 MMU (Memory Mapping Unit) 5 Selector 6 Controller 7 Peripheral Equipment 31 0th Cache Set 32 1st Cache Set 33 2nd Cache Set 34 3rd Cache Set 39 Cache Control Circuit 41 TLB (High Speed Conversion buffer mechanism)

Claims (13)

[Claims] 1. A set associative cache memory having a plurality of cache sets, a high-speed translation buffer having a correspondence between a part of a virtual address and an entry in the cache memory as address translation information, and a predetermined replacement logic. In a virtual memory type processor having a cache memory device provided with a control circuit for performing replacing control in the cache memory device, each entry of the high-speed conversion buffer mechanism stores data of a block corresponding to the entry in the cache memory device. A specified bit area for storing a specified value that specifies a cache set or a group of cache sets, wherein the control circuit stores the specified value in a specified bit area of an entry of the high-speed conversion buffer mechanism. In case,
A cache set or a group of cache sets specified by the specified value is selected. 2. A designated bit area of an entry of the high-speed conversion buffer mechanism stores information for designating whether the entry uses a cache memory and information for selecting a cache set or a group of cache sets to be used. The cache memory device according to claim 1, wherein: 3. A method of storing data in units of blocks and storing a virtual address and a physical address of data of each block in association with a designated value indicating which cache set or group of cache sets the block uses. A main memory for storing an address conversion table to be accessed, wherein the control circuit, when a mishit occurs in the cache device, sets a block data in the main memory of the data to be accessed in a cache set or a cache indicated by a designated value. The cache memory device according to claim 1, wherein the cache memory device is replaced with a set group. 4. When loading data into the main memory,
Means for storing, in the address translation table, a virtual address of a data block to be loaded, a physical address in main memory, and a designated value indicating which cache set or group of cache sets the block uses, The cache memory device according to claim 3, comprising: 5. A high-speed memory that does not cause replacement of the cache set or the group of cache sets by setting the same designated value to a data block having substantially the same capacity as that of the cache set or the group of cache sets. The cache memory device according to claim 4, wherein the cache memory device is used as: 6. The control circuit according to claim 1, wherein when the specified value specifies a cache set group, a cache set in the specified group is selected by a predetermined replacement logic to perform a replacement process. The cache memory device according to any one of claims 1 to 5, wherein: 7. A set associative cache memory having a plurality of cache sets, a main memory storing data in block units, and when loading a data block into the main memory, the data block Means for setting specified data specifying a cache set or a group of cache sets of the cache memory used by a data block; and storing a data block on the main memory in the cache memory in accordance with the corresponding specified data. Select a set or a group of cache sets,
Control means for storing the data block in a selected cache set. 8. A main memory for storing data in block units, a cache memory having a plurality of cache sets and storing a copy of data on the main memory, and an address conversion means for converting a virtual address to a physical address. A control circuit that replaces data in the cache memory with data in the main memory in units of blocks by a predetermined replacement logic when a cache mishit occurs. Includes designation information for designating a cache set or a group of cache sets in the cache memory device for the data of each block, and the control circuit sets the designation information to the address conversion means for the data block to be replaced. The key specified by the specified information Sshusetto or select a group of cache set, to replace the data of the corresponding block, the cache memory device, characterized in that. 9. The method according to claim 8, wherein the designation information includes information for designating whether the corresponding data block uses the cache memory and information for selecting a cache set or a group of cache sets to be used. The cache memory device according to claim 8. 10. The address translation means is arranged on the main memory, and specifies a virtual address and a physical address of data of each block, and a designated value indicating which cache set or group of cache sets the block uses. 10. The cache memory device according to claim 8, further comprising: an address translation table that stores the address translation table in association with the address translation table; and a high-speed translation buffer mechanism that stores a copy of the address translation table. 11. A means for converting the supplied virtual address into a physical address by the high-speed translation buffer mechanism, and converting the virtual address into a physical address by using an address translation table when a miss occurs in the high-speed translation buffer mechanism. An access unit for accessing the cache memory using a physical address converted by a conversion buffer mechanism or an address conversion table, wherein the cache memory accessed by the access unit has a cache miss. 11. The cache memory device according to claim 10, wherein the control circuit replaces the block data on the main memory located at the determined physical address to a cache set or a group of cache sets indicated by the specified value. 12. When loading data into the main memory, the virtual address of the data block to be loaded, the physical address in the main memory, and which cache set or group of cache sets the block is stored in the address translation table. 11. The apparatus according to claim 10, further comprising means for storing a designated value indicating whether or not to use the information.
Or a cache memory device according to item 11. 13. A cache memory control method for replacing a data block in a cache memory having a plurality of cache sets with other data in the main memory by a predetermined replacement logic, and performing the replacing. Each data block is assigned a designated bit that specifies a cache set or a group of cache sets into which the data block is loaded by replacing, and the cache set or the designated bit is designated by the designated bit of the data block to be replaced. A cache memory control method, comprising selecting a group of cache sets and performing a replacing process.