JPH07210463A - Cache memory system and data processor - Google Patents

Abstract

PURPOSE:To improve system performance by omitting unnecessary block transfer operation from a high-order hierarchy memory to an initiary cache mistake at the time of execution of a storing instruction. CONSTITUTION:Consecutive storing instructions causing the operation of the access of the whole data in the same entry are detected by a block transfer deterrence judging part 14 and the detection result is given to a memory control part 12 so as to prohibit the pertient memory control part from the operation of block-transferring an entry from the second cache memory 2 of a high order hierarchy to a low-order hierarchy memory such as a data cache memory 5 at the time of the initiary cache mistake.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory system and a data processor used therein,
For example, the present invention relates to a technique particularly effective when applied to a data processing system including a data processor having a lower cache memory built therein and an upper cache memory externally attached to the data processor.

[0002]

2. Description of the Related Art As a cache memory system, there is a system in which a second cache memory having a relatively large storage capacity is provided in addition to a data processor having a built-in high speed and small capacity first cache memory. The first cache memory and the second cache memory hold a plurality of entries with a plurality of cache data as a single entry, for example.

The first cache memory is a lower cache memory, and the second cache memory is an upper cache memory. Therefore, the first cache memory must hold a subset of the entries held by the second cache memory.

At this time, as a processing method at the time of a cache hit of the second cache memory against a cache miss of the first cache memory in the write access, a write allocate method of rewriting both cache memories and a non-allocate method of rewriting only the upper cache memory. There is a method.

In the case of the write allocate method, the first cache memory must hold a subset of the entries held by the second cache memory, so that the entry containing the cache-hit cache data in the second cache memory is transferred from the second cache memory to the first cache memory. Block transfer to the cache memory, and then the corresponding data in both cache memories is rewritten. In this write allocate method, since the entry including the cache-missed cache data is transferred to the first cache memory, there is a locality in the data reference within a certain time range (recently used data According to the rule of thumb that data in the vicinity is used immediately after that) is high, the cache hit rate can be expected to improve in subsequent memory accesses. However, the instruction execution is delayed by the time spent for the block transfer of the entry. In particular, the second cache memory is bus-connected to the outside of the data processor,
Since the throughput regulates the performance of the system, the system performance will be deteriorated when frequent accesses that do not follow the above empirical rule occur.

On the other hand, in the non-write allocate method, since no write processing is performed to the first cache memory, block transfer is not required, but even if access is frequently performed according to the empirical rule of the cache memory. We cannot expect an improvement in the hit rate. As described above, the write allocate method and the non-write allocate method have advantages and disadvantages, and the overall superiority or inferiority of the both depends on the application to be executed and the system to be mounted.

As an example of the document describing the cache memory, "Ultra High Speed MOS Device", issued by Baifukan Co., Ltd., November 5, 1987, pages 285 to 283.
There is a page.

[0008]

When the present inventor further examined the above-mentioned write allocate system, it was found by the present inventor that the write allocate system may essentially perform an extra operation. That is,
If a single entry in the cache memory is not stored for all cache data, or if there is a load instruction between store instructions, the cache data in the same entry is accessed from the second time. Becomes a hit, so even if the block transfer is performed first, the extra penalty caused by the block transfer can be reduced by the subsequent cache hit. However, if all cache data in the same entry are continuously stored without a memory reference instruction such as a load instruction, the first block transfer will result in an extra operation. Become. This is because all cache data in the newly block-transferred entry is sequentially rewritten by the subsequent store instruction without being referred to once.

An object of the present invention is to reduce unnecessary block transfer operations as in the above write allocate system and improve the overall system performance.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0011]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

(1) That is, in short, a means such as continuous store detection for all cache data in the entries of the cache memory is provided and the detection result is reflected in the instruction sequence, or the memory control unit is directly connected. Reflect on. The activation of the block transfer is controlled based on the reflected detection result.

More specifically, an upper memory and a lower memory for holding a plurality of single entries each including a plurality of cache data with the data held by the upper memory as cache data. In response to a cache miss in the lower memory in the execution of an instruction that involves writing, an entry including cache data of the cache miss can be transferred from the upper memory to the lower memory and a memory control unit that can perform the above data transfer. A determination unit that determines whether or not it is determined based on the code information of the instruction accompanied with the above-mentioned writing, and for the operation in which all the cache data included in a single entry is continuously rewritten, the memory control unit A determination unit that prohibits the data transfer, and otherwise permits the memory control unit to transfer the data; You configure the cache memory system. The upper memory may be the main memory,
It may also be a higher-side cache memory. When using the upper and lower cache memories, the lower cache memory holds a subset of the entries held by the upper cache memory.

In the case where the above-mentioned judging section is constituted exclusively by hardware, the code information of the prefetched instructions of the number corresponding to the number of cache data forming a single entry is received in parallel, and accordingly, A detection circuit that detects a state in which all cache data contained in a single entry is instructed to continuously rewrite, and a detection circuit that supplies the detection circuit in parallel when the detection result is obtained. The determination unit can be configured by a delay circuit that maintains the detection state during the execution period of all instructions and a storage unit that passes the output of the delay circuit to the memory control unit. When the instruction to be determined by the determination unit is a store instruction, a store detection unit that detects that the code information of each instruction received in parallel includes the operation code of the store instruction, and the plurality of instructions received in parallel Of the address detection unit for detecting that the code information of the address information includes all the cache data included in the same entry without duplication, and the detection state in both the store detection unit and the address detection unit. The determination unit can be configured by a logic gate that detects that the signal is obtained and supplies it to the delay circuit.

In order to simplify the hardware configuration of the determination unit, each instruction of the instruction sequence for instructing the operation of continuously rewriting all the information included in the same entry has a compile stage. Then, the data transfer prohibition instruction information is held. In this case, the determination section may cause the memory control section to prohibit the data transfer based on the data transfer prohibition instruction information.

(2) The data processor applicable to the cache memory system described above is an interface circuit capable of externally connecting the upper cache memory exclusively.
A lower cache memory for holding a plurality of single entries including the plurality of cache data with the data held by the upper cache memory as cache data, and a lower cache memory at the time of executing an instruction involving writing When a cache hit occurs in the upper cache memory in response to the cache miss of the above, a memory control unit capable of transferring the entry of the upper cache memory including the cache data of the cache miss to the lower cache memory and whether or not the above data transfer is performed. Is a determination unit that determines the determination based on code information of an instruction that involves writing, and transfers the data to the memory control unit for an operation in which all cache data included in a single entry is continuously rewritten. Ban, otherwise note A determination unit that permits the data transfer to the control unit, a central processing unit for executing a pipeline manner instructions can be configured into a single chip includes a.

[0017]

According to the above-mentioned means (1), the data transfer of the entry, that is, the block transfer of the cache data is carried out by referring to the information added to the instruction by software or exclusively depending on the hardware structure. The determination unit for selectively prohibiting the operation detects an operation such as continuous store for all cache data in the same entry of the cache memory, and prohibits block transfer for all cache data of the entry at the time of the operation. This reduces wasteful block transfer of entries that would cause cache data to be sequentially rewritten by subsequent store instructions without being referenced even if a new block is transferred, thus improving system performance.

According to the above means (2), the data processor connects the upper cache memory, which has a relatively large storage capacity but has a slower access speed than the built-in lower cache memory having a high speed and a small capacity, to the external bus. In this case, since the upper cache memory is connected to the outside of the data processor by a bus, its throughput regulates the system performance, but there is no waste of data from the upper cache memory to the internal lower cache memory. Block transfers can be reduced, which improves system performance.

[0019]

1 is a block diagram of a cache memory system according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a RISC (architecture having a reduced instruction set) format data processor 1, which is not particularly limited. A second cache memory 2 is coupled to the data processor 1 and an external bus is provided. The system bus 3 is connected. Although not shown, a main memory, an auxiliary storage device, an input / output circuit, etc. are connected to the system bus 3.

The data processor 1 has an interface circuit 8. The interface circuit 8 is externally coupled to the second cache memory 2 and the system bus 3 and the like, and internally coupled to a later-described built-in circuit module via a dedicated or common signal line. As a built-in circuit module, an instruction cache memory 4, a data cache memory 5, an address translation buffer (TL
B) 6, tag cache memory 7, write buffer 9,
Instruction control unit 10, arithmetic unit 11, memory control unit 12, instruction buffer register 13, and block transfer inhibition determination unit 1
Have 4.

The instruction buffer register 13 constitutes an instruction prefetch queue and the like. Instruction buffer register 13
The command output from is decoded by the command control unit to generate various internal control signals. The arithmetic unit 11 includes an arithmetic unit, a register file, and the like, and performs address arithmetic, data arithmetic, and the like to execute an instruction. The memory control unit 12 controls access to an external main memory (not shown) and the second cache memory 2 when executing an instruction. Further, the memory control unit 12 performs transfer of entries, which will be described later, and write / read control of cache data to the internal instruction cache memory 4, the data cache memory 5, and the tag cache memory 7.

The circuit composed of the instruction cache memory 4, the data cache memory 5, the address translation buffer 6 and the tag cache memory 7 constitutes a lower cache memory (also referred to as a first cache memory) for the second cache memory 2. Here, the configuration of the first cache memory will be described with reference to FIG.

The instruction cache memory 4 stores instructions,
The data cache memory 5 stores data, and the data and instructions stored in the cache memory are collectively referred to as cache data. The instruction cache memory 4 and the data cache memory 5 hold a plurality of entries with a plurality of cache data as a single entry. The data cache memory 5 will be representatively described. The tag cache memory 7 holds the physical address information that corresponds to the entry of the data cache memory 5 on a one-to-one basis as the tag information of that entry. Data cache memory 5
The tag cache memory 7 is accessed based on the logical address output from the arithmetic unit 11. The address translation buffer 6 outputs a physical address corresponding to the logical address output from the arithmetic unit 11. For example, when an instruction involving memory access such as a store instruction or a load instruction is executed, when the operation unit 11 performs an address operation for that and outputs a logical address, it outputs the data cache memory 5, the tag cache memory 7, and the address. It is supplied to the conversion buffer 6. As a result, the physical address output from the address conversion buffer 6 and the tag information output from the tag cache memory 7 are compared.
If the instruction being executed at this time is a load instruction, the cache data read from the data cache memory 5 is used for executing the instruction and is a store instruction. In that case, the cache data is rewritten. In addition,
Tag information has a valid bit for indicating the validity of cache data, a share bit for indicating whether or not cache target information is shared in a multiprocessor system, and these are also referred to for cache hit / miss. Is determined.

The second cache memory 2 is not particularly limited, but includes a data cache, an instruction cache,
And each memory of the tag cache. The access of the second cache memory 2 is controlled by the memory control unit 12.

The relationship between the second cache memory 2 and the first cache memories 4 to 7 will be described. The first cache memories 4 to 7 are lower cache memories, and the second cache memory 2 is an upper cache memory. To satisfy this relationship, the first cache memories 4 to 7 must hold a subset of the entries held by the second cache memory 2. Therefore, for example, in a load instruction from a memory to a register, when the first cache memory is a cache miss and the upper second cache memory is a cache hit, the data to be loaded is read from the second cache memory. At this time, the above relationship is satisfied even if the entry including the cache miss cache data is not transferred from the second cache memory 2 to the first cache memories 4 to 7. According to the empirical rule that the data reference within a certain time range has locality, it is a good idea to transfer the data unconditionally in such a case.

On the other hand, for example, in the case of a store instruction from a register to a memory, when the first cache memory is a cache miss and the upper second cache memory is a cache hit, the data to be stored is written in the second cache memory. At this time, depending on whether or not the first cache memories 4 to 7 are also rewritten, the processing can be divided into the write allocate system and the non-allocate system.

The write allocate system is a system in which both cache memories are rewritten in the expectation of a cache hit of the first cache memory in the subsequent data reference. Since the first cache memories 4 to 7 must hold a subset of the entries held by the second cache memory 2, the entries including the cache data cache hit in the second cache memory 2 are transferred from the second cache memory 2 to the first cache memories 4 to 7. Block transfer to the cache memory, and then the corresponding data in both cache memories is rewritten.

FIG. 3 shows a procedure according to the write allocate system. If a cache miss occurs in the first cache cache memories 4 to 7 (hereinafter also referred to as the first cache memory FCM) during the store operation of the data X ′ (), the entry that has been missed from the second cache memory 2 (hereinafter also referred to as the second cache memory SCM). Data is written in the first cache memory FCM by block transfer (). The block-transferred entry contains the previous data X. Then, the cache-missed data X ′ is written to the first cache memory FCM and the write buffer 9 (hereinafter also simply referred to as the write buffer WTB) (). The data X ′ written in the write buffer WTB is transferred to the second cache memory SCM in consideration of the timing when the bus connecting the second cache memory SCM and the data processor 1 is released. During the period of ~, the pipeline by the data processor 1 may be locked for a period of several cycles. For example, in the pipelined instruction execution sequence shown in FIG. 5, if there is a cache miss in the memory access of a store instruction, the memory access stage A continues for a plurality of stages, and the instruction execution is substantially executed during that period. Suspended.

FIG. 4 shows a procedure according to the non-write allocate system. If the first cache memory FCM has a cache miss during the store operation of the data X '(), the block transfer is not started, and the value of the share bit S (representing the shared data in the multiprocessor configuration) of the second cache memory SCM is checked. Then, (), the new data X'that was the cache miss is written only in the write buffer WTB (). The data X ′ written in the write buffer WTB is transferred to the second cache memory SCM in consideration of the timing when the bus connecting the second cache memory SCM and the data processor 1 is released. During the period of ~, the pipeline of the data processor 1 may be locked for several cycles.

The penalty due to the pipeline lock of the non-write allocate system is 1 in the write allocate system.
/ 2 to 2/3 is sufficient. This is because the non-write allocate method does not transfer the block of the cache missed entry. However, instead, even if local data references frequently occur thereafter, the non-write allocate method cannot be expected to improve the cache hit rate in the first cache memory FCM.

The memory controller 12 controls the above block transfer. That is, at the time of a cache hit of the second cache memory 2 against the cache miss of the first cache memory at the time of storing in the memory, the data transfer control of the entry of the second cache memory 2 including the cache data of the cache miss to the first cache memory.

In the present embodiment, in the write allocate system, when the above block transfer is substantially wasted, the block transfer is not performed, and at that time, the write allocate is performed so that the advantage of the non-write allocate system can be obtained. This is a partial modification of the procedure of the method. In other words, the block transfer is not performed when it is clear that the localized data reference does not occur, and otherwise, the cache hit rate is expected to improve by the localized data reference. Block transfer is performed.

FIG. 6 shows an example of the case where it is clear that a localized data reference does not occur and a case where it is not. As shown in the figure, one entry holds four pieces of cache data. The instruction sequence (a) in FIG. 6 shows a case in which one entry is not stored for all the cache data, or a load instruction exists between store instructions. In this case, since the cache data of the same entry is accessed as a cache hit from the second time, an extra penalty due to block transfer (BT) can be reduced. The instruction sequence (b) in FIG. 6 is a case where store instructions are continuously executed for all cache data in the same entry without a memory reference instruction such as a load instruction interposed therebetween. At this time, the first block transfer (B
T) is an extra operation. This is because all the cache data in the entry newly block-transferred from the second cache memory to the first cache memory is never referred to (here, the data of B, C, D) and is stored by the subsequent store instruction. Because it will be rewritten.

Next, a concrete example for prohibiting the block transfer by the memory control unit 12 for the operation by the continuous store instruction in which all the cache data of the same entry is rewritten as described above will be described with reference to FIGS. The description will be made with reference to FIG.

As shown in FIG. 7, the instruction buffer register 13 includes serial four-stage instruction queues 16A to 16D. Instructions are transmitted from the instruction cache memory 4 to the instruction queue 16A in the first stage. The output of the last-stage instruction queue 16D is supplied to the instruction register 23. The block transfer inhibition determination unit 14 determines whether or not to perform the block transfer based on the code information of the instruction, and all cache data included in a single entry is continuously rewritten. In response to the operation, the memory control unit 12 is prohibited from performing the data transfer, and otherwise, the memory control unit 12 is allowed to perform the data transfer.

That is, according to this embodiment, as shown in FIG. 9, one entry of the cache memory includes four cache data. For example, the lower 2 bits of the logical address for accessing the cache data are regarded as a signal indicating which cache data is pointed within one entry, and the upper bits thereof are regarded as a bit string for pointing one entry.

As shown in FIG. 7, the block transfer inhibition determination unit 14 includes the instruction queues 16A to 16D of four serial stages.
Receive the information held by each of them in parallel. The information input in parallel is supplied to the store detection unit 30, the base register match detection unit 31, and the displacement detection unit 32. Although not particularly limited, the format of the store instruction is composed of a 6-bit operation code section, a 5-bit base register section, and an 11-bit displacement section as shown in FIG. The addressing method of the destination address (write memory address) in this instruction format is base register modification, and the value obtained by adding the value of the displacement part to the value of the base register specified by the base register part is the destination address. It is said that

The store detecting section 30 detects that the operation code of the instruction held by the four-stage instruction queues 16A to 16D in series is the code of the store instruction and outputs a high level signal. Base register match detection unit 31
Detects that the values stored in the base register designating section of the instructions held by the four-stage instruction queues 16A to 16D match, and outputs a high level signal. In the displacement detection unit 32, the upper 9 bits of the displacement portion of the instruction held by the four-stage instruction queues 16A to 16D are completely coincident, and the lower 2 bits are sequentially 00, 01, 10, 11.
Is detected and a high level is output. These functions are shown conceptually in FIG. Each detection unit 30
The outputs of .about.32 are supplied to the AND gate 33. Therefore, the output of the AND gate 33 is set to the high level because a series of store instructions such that all cache data of the same entry are instructed to be rewritten is instructed continuously in four stages. Prefetch queue 1
It is obtained according to the state taken into 6A to 16D.

The output of the AND gate 33 is a shift circuit 35 including latch circuits 35A, 35B and 35C in three stages in series.
Be transmitted to. Latch circuits 35A, 35B of three stages in series,
The respective outputs of 35C are supplied to the 4-input type OR gate 34 together with the output of the AND gate 33. The shift operation of the shift circuit 35 is synchronized with the timing at which the output of the instruction queue 16D at the final stage is transmitted to the instruction register 23.
Therefore, if the output of the AND gate 33 is once set to the high level, then the four-stage instruction queues 16A to 16D
The output of the OR gate 34 is maintained at the high level for the period in which the store instruction held in the instruction register 23 is sequentially fetched into the instruction register 23. The output of the OR gate 34 is regarded as a control bit that controls the availability of the block transfer. Hereinafter, this control bit is referred to as block transfer control bit B
It is referred to as TC. This block transfer control bit BTC is supplied to a predetermined flag bit 24 of the instruction register 23,
It is given to the instruction control unit 10 together with the instruction.

The block transfer control bit BTC given to the instruction control unit 10 is given to the block transfer starting circuit 40 of the memory control unit 10 as shown in FIG. 1, for example. The logical block 41 included therein stores the entry of the second cache memory 2 including the cache data of the cache miss at the time of the cache hit of the second cache memory 2 against the cache miss of the first cache memory FCM at the time of storing in the memory. To form a primitive block transfer detection signal 42 for controlling data transfer. The block transfer detection signal 42 is not particularly limited, but sets the primitive detection level of the block transfer state to the high level. The inverted signal of the block transfer control bit BTC is supplied to the other input of the AND gate 43 which receives the detection signal 42 at one input. Therefore, while the block transfer control signal BTC is at the high level, even if the block transfer detection signal 42 is at the high level, the block transfer activation signal 44 output from the AND gate 43 is set to the disable level, and the memory controller The block transfer by 12 is suppressed. When the block transfer control bit BTC is at the low level, the block transfer detection signal 42 is directly output as the block transfer start signal 44, and the block transfer by the memory controller 12 is enabled.

FIG. 10 shows a conventional write allocate system,
A comparative example of the processing steps according to the non-write allocate method and the above-described embodiment method is shown. (A) of the same figure is an example in the case of executing a continuous 4-store instruction that requires a write operation of cache data of the same entry, and (B) of the same figure shows that an operation of cache data of the same entry is required. 2 is an example of executing a 1 store-3 load instruction.

In FIG. 9A, the states obtained in the first cache memory and the second cache memory by the conventional write allocate method and the method of the present embodiment are the same, but in the conventional write allocate method, there is a substantially wasteful start. As a result of omitting the block transfer processing, the number of processing steps (the number of pipeline stages) is reduced in the method of this embodiment. Comparing the method of this embodiment and the non-write allocate method, the number of steps is apparently the same, but in the latter case, the data to be stored in the first cache memory is not held as cache data. Therefore, if a load instruction or the like that refers to the entry is executed thereafter, a cache miss will occur. Therefore, the method of this embodiment is superior to the other two methods in terms of both the number of processing steps and the cache hit rate in subsequent data reference.

In FIG. 6B, the method of this embodiment is substantially the same as the conventional write allocate method, and it can be expected that the cache hit rate can be improved according to the locality of data reference. The non-allocate method cannot expect that at all, and the number of processing steps is significantly increased.

The performance improvement of the entire system when this embodiment is adopted is determined by the occurrence frequency of the above-mentioned continuous 4-store instruction, but even if it is several percent, the system performance can be surely improved. In particular, in the case of the RISC processor, high-performance processing is realized by a combination of relatively simple instructions including a store instruction, so that it is considered that the frequency of occurrence of continuous four store instructions also increases. Also,
In the above embodiment, one entry includes four cache data, but the greater the number of cache data included in one entry, the greater the effect can be expected as compared with the conventional allocate method. Further, even if the bus width of the data bus or the number of bits of the bus increases, it is considered that the execution frequency of the continuous strike instruction also increases, so that a large effect can be expected in that case as well.

In the above embodiment, when an interrupt occurs during execution of four consecutive store instructions and the interrupt processing is started before the end of four store instructions, the first cache memory FCM and the second cache memory SCM are used.
The processing is interrupted while the contents of the common entry of are left inconsistent. Therefore, it is desirable to correct the mismatch at least immediately after returning from the interrupt processing. For example, four instruction queues 16A to 16D
Is provided with a special flag bit (not shown) so that the four flags are set when the output of the AND gate 33 is set to the high level. When interrupted, the four flag bits and block transfer control bit B
Also try to save the TC. After the return, it is sufficient to refer to the flag bit and add processing for maintaining the block transfer control bit BTC at the high level as long as the flag bit is in the set state.

Further, in the above embodiment, the block transfer inhibition determination unit 14 is used to configure the determination unit exclusively by hardware, but to simplify the hardware configuration of the determination unit, the determination unit is included in the same entry. Each instruction of the instruction sequence for instructing the operation of continuously rewriting all the information to be stored has the data transfer prohibition instruction information at the compilation stage. The data transfer prohibition instruction information is decoded together with other instruction code information by the instruction control unit 10 and the result is given to the memory control unit 12, or the data transfer prohibition instruction information is cut out from the instruction and given directly to the memory control unit 12. .
By this, similarly, the block transfer can be selectively prohibited, and the same effect can be obtained.

When the read access and the write access are performed in parallel in the pipeline instruction execution stage, the memory control section 12 detects the cache hit of the second cache memory SCM against the cache miss of the first cache memory FCM in the read access. For the state, the read operation of the second cache memory SCM is permitted in preference to the write access,
In parallel with this, instead of the write operation of the second cache memory SCM, the write operation to the write buffer 9 is performed.

In the above embodiment, the second cache memory 2 for the first cache memory FCM is the upper memory, but the upper memory may be the main memory (not shown) of the system bus 3.
In this case, the memory control unit 12 performs the above block transfer from the main memory to the first cache memory. The logic block 41 may generate the block transfer detection signal 42 from the result of the cache miss determination of the first cache memory during the storage in the memory.

According to the above embodiment, the following operational effects can be obtained. (1) To omit the block transfer operation from the upper cache memory such as the second cache memory 2 and the main memory when the primary cache miss occurs in the first cache memory FCM at the time of executing a store instruction only when all data in the same entry is accessed. You can As a result, if the upper-layer memory is the second cache memory 2 configured in the external SRAM form, several cycles,
In the case of the main memory, the penalty of tens of cycles (the number of pipeline stages or pipeline cycles of pipeline lock) can be reduced. Therefore, system performance can be improved. (2) The data processor 1 is a high-order cache memory SCM having a relatively large storage capacity, although the access speed is slower than that of the built-in cache memory FCM having a high speed and a small capacity.
Can be held externally by bus connection. At this time, since the upper cache memory SCM is connected to the outside of the data processor 1 by bus, its throughput regulates the system performance. It is possible to reduce unnecessary block transfer to the memory FCM. Therefore, by using the data processor 1 described in this embodiment, the performance of the system controlled by the data processor 1 can be improved. (3) Cache memory SCM by the memory control unit 12
When the read access and the write access conflict with each other, the write buffer 9 is used to prioritize the read of the cache data to minimize the delay of the data processing or the instruction execution, and further improve the system performance. You can

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Yes. For example,
The configuration of the lower cache memory such as the first cache memory is not limited to the above embodiment and can be changed as appropriate. For example, the configuration may be such that either one of the instruction cache memory and the data cache memory is provided, or the instruction and data may be mixed and stored.
The transmission of the block transfer control bit BTC to the memory control unit 12 may be a direct transmission of the block transfer control bit BTC, or a signal obtained from the decoding result by the instruction control unit 10 may be transmitted to the memory control unit 12. Good.

[0051]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) 1 when executing an instruction involving writing
The block transfer operation from the upper layer memory for the next cache miss can be omitted only when all data in the same entry is accessed. As a result, it is possible to reduce wasteful block transfer of entries that would cause cache data to be sequentially rewritten by subsequent instructions without being referenced even if a new block is transferred, and improve system performance. . (2) The data processor can externally hold a high-order cache memory having a relatively large storage capacity but a relatively large storage capacity by bus connection as compared with a high-speed and small-capacity built-in low-order cache memory. Since the cache memory is connected to the outside of the data processor by a bus, its throughput regulates the system performance.
It is possible to reduce unnecessary block transfer from the upper cache memory to the built-in lower cache memory, thereby improving the system performance.

[Brief description of drawings]

FIG. 1 is a block diagram of a cache memory system according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an overall configuration of a first cache memory.

FIG. 3 is an explanatory diagram of a processing procedure by a write allocate system.

FIG. 4 is an explanatory diagram of a processing procedure in a non-write allocate system.

FIG. 5 is an explanatory diagram of pipeline lock.

FIG. 6 is an explanatory diagram showing an example of a case in which it is clear that a localized data reference does not occur and a case in which it is not.

FIG. 7 is a block diagram of an example of an instruction buffer register and a block transfer control unit.

FIG. 8 is an explanatory diagram conceptually showing the function of a block transfer inhibition determination unit.

FIG. 9 is an explanatory diagram showing an example of the relationship between one entry and a plurality of cache data included therein.

FIG. 10 is a comparative explanatory diagram in which the number of processing steps of the conventional write allocate method, non-write allocate method, and method according to the present embodiment is divided into four consecutive store instruction executions and one store-3 load instruction execution. is there.

[Explanation of symbols]

 1 data processor 2 second cache memory 3 system bus 4 instruction cache memory 5 data cache memory 6 address conversion buffer 7 tag cache memory 8 interface circuit 9 write buffer 10 instruction control unit 12 memory control unit 13 instruction buffer register 14 block transfer inhibition determination unit 15 comparator FCM first cache memory SCM second cache memory 16A to 16D instruction queue 23 instruction register 24 flag bit BTC block transfer control bit 30 store detection unit 31 base register match detection unit 32 displacement detection unit 33 AND gate 34 OR gate 35 shift circuit 40 Block transfer start circuit 41 Logical block 42 Block transfer start signal 43 AND gate 4 Block transfer start-up signal

Claims (6)

[Claims] 1. An upper side memory, a lower side memory for holding a plurality of single entries including the plurality of cache data with data held by the upper side memory as cache data, and writing In response to a cache miss in the lower side memory during instruction execution, a memory control unit that can transfer an entry including cache data of the cache miss from the upper side memory to the lower side memory, and whether or not to perform the data transfer Is a determination unit for determining based on the code information of the instruction accompanied by the writing,
A determination unit that prohibits the data transfer by the memory control unit for an operation in which all cache data included in a single entry is continuously rewritten, and otherwise permits the data transfer by the memory control unit. And a cache memory system comprising: 2. An upper cache memory for holding a plurality of entries with a plurality of cache data as a single entry, and a lower cache memory for holding a subset of the entries held by the upper cache memory, Memory control that can transfer the entry of the upper cache memory including cache data of the cache miss to the lower cache memory when the cache hit of the upper cache memory against the cache miss of the lower cache memory at the time of executing an instruction accompanying writing And a determination unit that determines whether or not to perform the data transfer, based on code information of the instruction accompanying the writing,
A determination unit that prohibits the data transfer by the memory control unit in response to an operation in which all cache data included in a single entry is continuously rewritten, and otherwise allows the memory control unit to allow the data transfer. And a cache memory system comprising: 3. The determination unit receives in parallel code information of prefetched instructions, the number of which corresponds to the number of cache data forming a single entry, and thereby all caches included in the single entry. A detection circuit that detects a state instructing an operation in which data is continuously rewritten, and the above detection during the execution period of all the instructions supplied in parallel to the detection circuit when the detection state is obtained. 3. The cache memory system according to claim 1, further comprising: a delay circuit for maintaining a state, and a storage unit for passing an output of the delay circuit to the memory control unit. 4. The store detection unit, wherein the detection circuit detects that the code information of each instruction received in parallel includes an operation code of a store instruction, and the code information of the plurality of instructions received in parallel are the same. It is detected that the detection state is obtained in both the store detection unit and the address detection unit that detects that the cache data included in the entry includes the addressing information that indicates the entire cache data without duplication. 4. The cache memory system according to claim 3, further comprising a logic gate which is supplied to the delay circuit. 5. Each instruction of an instruction sequence for instructing an operation of continuously rewriting all information to be included in the same entry has the data transfer prohibition instruction information, and the determination section 3. The cache memory system according to claim 1, wherein the memory control unit prohibits the data transfer based on the data transfer prohibition instruction information. 6. An interface circuit to which an upper cache memory can be exclusively connected externally, and a single entry including a plurality of cache data, wherein the data held by the upper cache memory is used as cache data. When the cache hit of the upper side cache memory against the cache miss of the lower side cache memory at the time of executing an instruction accompanied by a write, the upper side cache memory including the cache data of the cache miss A memory control unit that can transfer the data to the lower cache memory, and a judgment unit that judges whether or not to perform the data transfer based on the code information of the instruction accompanied by the writing. All included cache data is continuous A control unit that prohibits the above data transfer by the memory control unit for an operation that is rewritten, and a determination unit that permits the above data transfer to the memory control unit if not, and a central processing unit that executes instructions in a pipeline manner. A data processor characterized by comprising: and a single chip.