JP2004303232A - Data memory cache device and data memory cache system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data memory cache device and a data memory cache system for improving a memory access speed. <P>SOLUTION: This cache unit 117 perform the reading/writing of data for a main storage device 131 by a line unit of 16 byte width, and performs the reading/writing of data for an MPU 113 by a small area unit of 4 byte width included in each line. When the MPU 113 executes a push instruction, and any cache mistake is generated in the line including the small area for holding data to be read to the MPU 113 (No at S1), the cache unit 117 opens the line (S301). When the small area where the data to be transmitted from the MPU 113 should be written is made adjacent to the line boundary of the large address side, that is, early writing side (Yes at S56), the cache unit 117 does not perform refill, and when the small area is not made adjacent to the line boundary (No at S56), the cache unit 117 performs refill(S21). <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The invention according to the present patent application (hereinafter, also simply referred to as “the present invention”) aims at improving performance by avoiding overhead due to slow access speed of the main storage device when the CPU accesses the main storage device. (Also referred to as a cache memory) device and system.

  The present invention particularly relates to a cache of a data memory for storing data, and furthermore, a so-called stack memory, that is, an address is continuously accessed (reading or writing of data) by a push-pop instruction. This is related to a data memory cache.

Conventional stack cache control methods and stack caches for reducing the time required for a push / pop instruction and preventing unnecessary data after the push / pop from being held in the cache include, for example, a main memory. It supports a stack structure in which the last input data is output first as a data structure on the device, pushes data input to the stack, pops data output from the stack, and distinguishes it from other data writing / reading. In a microcomputer system including a microcomputer that performs data processing, when the microcomputer pushes, a set of a corresponding address and data is held in place of the main storage device, and held data that has not been pushed to the main storage device is stored. The microcomputer accesses outside Pushing to the main storage device at a time when it is not performed, and outputting the relevant data to the microcomputer instead of the main storage device if the microcomputer holds the corresponding data when the microcomputer pops, In order to replace data that is no longer required by the pop with data at the bottom of the stack that may be popped later, the microcomputer pops from the main storage device when the microcomputer is not accessing the outside. There has been a stack cache control method (for example, see Patent Document 1).
JP-A-5-143330

  However, the conventional stack cache system and the conventional stack cache control method make use of the characteristic of the regular access called the stack memory without any difference from the memory access speed-up method assuming random access to the normal data memory. However, there was a problem in increasing the speed.

  This is a serious problem particularly in a memory system having a large stack access specificity, such as a Java (registered trademark) system, which has been increasingly required for ubiquitous computing in recent years. Specific problems will be described below.

(First problem)
For example, assume that a data push on a stack is performed in the direction of increasing memory addresses on the main storage device, and that this stack is cached in a cache memory. It is assumed that a cache miss has occurred due to the push of a certain data A. Under this condition, the contents of the new data memory for one cache unit from the memory address where the cache miss has occurred are read from the main storage device to the cache memory.

  This state is shown in FIG. FIG. 35 shows a state where the stack pointer 913 is located in the memory area at the address 90, and the data A is pushed to the memory area at the address 90. At this time, the stack pointer 913 is moved from the memory area at the address 89 to the memory area at the address 90 by pushing the data A as shown in FIG.

  Further, as shown in FIG. 35, the memory area of addresses 90, 91, 92, and 93 is one cache unit, and the memory area of address 90 of this one cache unit is accessed for the first time. One cache unit including the memory areas 91, 92, and 93 is read from the main storage device to the cache memory.

  However, the contents of the new data memory for one cache unit read into this cache memory are contents which are overwritten by successive data pushes and are data which are never read out, as long as the regularity of stack access is followed. is there. Reading data that is never read out from the main storage device into the cache memory as described above has been a problem in increasing the speed.

(Second problem)
Conversely, it is assumed that a data pop on the stack has been performed in the direction of decreasing memory addresses on the main memory, and that this stack has been cached in the cache memory. Then, it is assumed that a cache miss has occurred due to a pop of a certain data B. Under this condition, the contents of the data memory for one cache unit are written back from the cache memory to the main storage device from the memory address larger than the memory address where the cache miss has occurred.

  This state is shown in FIG. As shown in FIG. 36, the stack pointer 923 moves from the memory area at the address 90 to the memory area at the address 89 due to the pop of the data B. Further, as shown in FIG. 36, the memory area of addresses 90, 91, 92, and 93 is one cache unit, and the stack pointer has moved to the memory area of address 89 other than this one cache unit. One cache unit consisting of the memory areas 90, 91, 92, and 93 is written back from the cache memory to the main storage device, and the cache memory is released.

  However, the contents of the data memory for one cache unit written back to the main memory are the contents read by the already performed data pop, and are never read again, as long as the regularity of the stack access is followed. Impossible. Writing back data that is never read from the cache memory to the main storage device in this way has been a problem in increasing the speed.

(Third problem)
It is also assumed that the data push to the stack has been performed in the direction of increasing the memory address on the main storage device, and that this stack has been cached in the cache memory. Assume that certain data C, D,..., E are continuously pushed. Under this condition, a lot of data pushed in the stack, that is, C or D in this example, is stored in a memory area at an address lower than the address indicated by the stack pointer, which is an area where a push / pop operation is currently performed on the stack. Therefore, it is very unlikely that the data stored in the memory area of this low address will be read out by pop for a while.

  FIG. 37 shows this state. In FIG. 37, there is a stack pointer 933 in the memory area of the address 194, and the data of C, D,..., E is pushed continuously from the memory area of the address 80 far below, for example, to the memory area of the address 194. The state is shown. At this time, as shown in FIG. 37, one cache unit from address 80 to address 83 normally occupies the cache memory area unless the cache memory becomes full, and it is not written back to the main storage device. Absent. Only when the cache memory becomes full, the data is written back to the main memory, and the cache memory is reclaimed for another memory area.

  Performing write-back after the cache memory becomes zero and a request for a new cache memory area is generated has been a problem in increasing the speed.

  For example, as shown in FIG. 37, a memory area far below the memory area of the address 194 which is the current position of the stack pointer 933, for example, the memory area of the addresses 80 to 83 may be read by pop for the time being. Is very low. Therefore, unlike the related art disclosed in Patent Document 1, for example, the contents of a cache memory in one cache unit which is a memory area of addresses 80 to 83 are written back to the main storage device in advance. It can be envisaged as a means. As a result, it is expected that the memory access speed will be improved as compared with the case where the contents of the cache memory are hurriedly written to the main storage device when the margin of the cache memory is exhausted and a free area is created in the cache memory.

(Fourth problem)
It is further assumed that a data pop on the stack has been performed in the direction of decreasing memory addresses on the main memory, and that the stack has been cached in the cache memory. It is assumed that certain data F, G,..., H are successively popped. Under this condition, data that is currently being pushed in the address area having a value lower than the address indicated by the stack pointer, which is the area where the push / pop operation is performed on the stack, for example, the memory area at addresses 84 to 87 in this example. Is very likely to be read out immediately after a pop.

  This state is shown in FIG. In FIG. 38, the stack pointer 943 is located in the memory area at the address 91, and the data of F, G,..., H is continuously popped from the memory area at the address 196 to the memory area at the address 91. The state is shown. At this time, as shown in FIG. 38, normally, one cache unit from address 84 to address 87 is stored in one memory belonging to this area, for example, from the main memory unless the memory area at address 87 is accessed by executing pop. It is not read into the cache memory area. Then, for example, only when the memory area at the address 87 is accessed by executing the pop, the data is read from the main storage device to the cache memory.

  As described above, the speed of reading data from the main storage device to the cache memory area after the area belonging to one new cache memory unit is accessed for the first time and a data request for the new one cache memory area occurs is increased. Was an adverse effect in achieving

  For example, as shown in FIG. 38, one cache unit occupying the memory area immediately below the memory area at the address 91 which is the current position of the stack pointer 943, for example, the memory area at the addresses 84 to 87, is immediately popped up. Is very likely to be read by Therefore, unlike the related art disclosed in Patent Document 1, it is assumed that, for example, data of one cache unit, which is a memory area of such addresses 84 to 87, is read from the main storage device into the cache memory in advance. It can be envisaged as a solution. As a result, it is expected that the memory access speed will be improved as compared with the case where the contents of the main storage device are read into the cache memory in a hurry when an access is made to a memory area not existing in the cache memory.

  The present invention has been made in view of the above problems, and has as its object to provide a data memory cache device and a data memory cache system that improve the memory access speed.

  In order to solve the above-mentioned problem, an invention according to claim 1 is a data memory cache device to be used by being interposed between an arithmetic unit and a main storage device accessed by the arithmetic unit. Having a plurality of data areas, data held in each of the plurality of data areas is read and written to the main storage device at a time, and each of the plurality of data areas is divided into a plurality of small areas. The data held by each of the plurality of small areas is a data holding unit that is temporarily read / written from / to the arithmetic unit; and the data writing unit writes data from the arithmetic unit to successive addresses in the main storage device. There is a write request and a cache miss has occurred in the target data area, which is the data area corresponding to the address output by the arithmetic unit. In this case, after releasing the target data area, the target small area in the target data area, which is a small area corresponding to the address output by the arithmetic unit, is positioned in the address writing order in the earlier direction of the continuous writing. When the data is adjacent to a data area boundary which is a boundary of the target data area, the data output by the arithmetic unit is written to the target small area without reading data from the main storage device to the target data area. If the target small area is not adjacent to the data area boundary, data is read from the main storage device to the target data area, and then data output by the arithmetic unit is written to the target small area. And a control unit.

  According to the first aspect of the present invention, when a cache miss occurs at the time of continuous writing to consecutive addresses from the arithmetic unit, the control unit sets the data area to be written after releasing the data area. Since unnecessary data is not read from the main storage device, the memory access speed is improved. Further, the control unit selects whether or not to omit reading data from the opened data area according to whether the small area to be written is adjacent to the data area boundary. That is, when a cache miss occurs when the small area to be written is not at the data area boundary, the control unit reads data from the main storage device into the released data area. Therefore, the arithmetic unit can start the continuous writing not only from the address corresponding to the small area adjacent to the data area boundary but also from the address corresponding to the small area not adjacent to the data area boundary.

  The invention according to claim 2 is the data memory cache device according to claim 1, wherein the control unit detects a push access detection unit that detects the continuous write request from the arithmetic unit, and the push access detection unit detects the push access detection unit. A cache miss determining unit that determines whether there is a cache miss in the target data area when the unit detects the continuous write request; and a cache miss determination unit that detects the continuous write request when the push access detection unit detects the continuous write request. A boundary determination unit that determines whether the small region is adjacent to the data region boundary; and a data region release unit that releases the target data region when the cache miss determination unit determines the occurrence of the cache miss. When the data area release unit releases the target data area, the determination of the boundary determination unit is negative. In this case, data is read from the main storage device into the target data area released by the data area release unit, and when the determination by the boundary determination unit is affirmative, the target data released by the data area release unit is read. A refill unit that does not read data from the main storage device to an area, and a data writing unit that writes data output by the arithmetic unit to the target small area when the push access detection unit detects the request for continuous writing. It is provided with.

  According to the second aspect of the present invention, the push access detection unit detects a continuous write request, the cache miss determination unit determines whether there is a cache miss in the target data area, and the boundary determination unit determines that the target small area is The data area release unit determines whether or not it is adjacent to the data area boundary, the data area release unit releases the target data area according to the determination of the cache miss determination unit, and the refill unit is released according to the determination of the boundary determination unit. The data is read into the target data area, and the data writing unit writes data from the arithmetic unit into the target small area. For this reason, the control unit can easily realize a process of omitting the reading of data from the opened data area according to whether the small area to which data is to be written is adjacent to the data area boundary.

  According to a third aspect of the present invention, in the data memory cache device according to the second aspect, the data holding unit holds a plurality of appropriate flags respectively indicating release or non-release of the plurality of data areas. The refill unit further includes an appropriate flag holding unit, and the refill unit is configured such that, even when the appropriate flag corresponding to the target data area is set to a side indicating open, when the determination of the boundary determining unit is negative, Data is read from the main storage device into the target data area, and when the determination by the boundary determination unit is affirmative, data is not read from the main storage device into the target data area.

  According to the third aspect of the present invention, the data holding unit includes the appropriate flag holding unit, and the refill unit sets the appropriate flag corresponding to the target data area not only when the target data area is opened, but also when the target data area is opened. Also indicates whether data is to be read from the main storage device to the target data area according to the position of the target small area. For this reason, even when the target data area is open, unnecessary reading is avoided, thereby further improving the memory access speed. When the target small area is not adjacent to the data area boundary, the refill unit reads data from the main storage device to the target data area, so that the arithmetic unit performs continuous writing on the small area adjacent to the data area boundary. It is possible to start from an address corresponding to a small area which is not adjacent to the data area boundary as well as an address to be assigned.

  The invention according to claim 4 is the data memory cache device according to claim 2 or 3, wherein the data holding unit determines whether the plurality of data areas are used for either continuous writing or continuous reading. The control unit further includes a plurality of stack flag holding units that hold a plurality of stack flags respectively indicating that the data writing unit writes the data when the determination by the boundary determination unit is affirmative. After completion, the stack flag corresponding to the target data area is set to the positive side, and if the determination of the boundary determination unit is negative, after the data writing unit finishes writing the data, A stack flag setting unit that does not change the stack flag corresponding to the target data area is further provided.

  According to the invention described in claim 4, the data holding unit includes the stack flag holding unit, and the control unit includes the stack flag setting unit that operates the stack flag according to the position of the target small area after writing the data. Therefore, in the course of continuous writing, the control unit uses the non-use period of the data bus to release the data in the data area for which writing has been completed before releasing the data area due to a cache miss. When a configuration is used in which data is written back in advance, use of the stack flag can avoid unnecessary use of data in the data area not allocated to the stack. Further, even when the control unit adopts a configuration in which data is read from the main storage device in advance to a data area before reading in a continuous reading process, the data in the data area not allocated to the stack can be obtained by using the stack flag. It is possible to avoid performing unnecessary reading for.

  The invention according to claim 5 is the data memory cache device according to any one of claims 2 to 4, wherein the plurality of data areas are associated with a middle part of an address of the main storage device. , Each of the plurality of small areas is associated with a lower part of the address of the main storage device, and one or more data areas correspond to the same value of the middle part of the address of the main storage device. The data holding unit further includes a plurality of tag holding units that hold a plurality of tags each indicating an upper part of an address of data held by the plurality of data areas, and the control unit is configured to output the arithmetic unit. An address extracting unit that extracts the upper part, the middle part, and the lower part from the address to be copied, and the cache miss determining unit is configured to extract the middle part extracted by the address extracting unit. The value indicated by the tag associated with each of the one or more data areas corresponding to the minutes and the upper part extracted by the address extraction unit are compared, and if none of them match, the cache miss has occurred. The boundary determination unit determines that the small area corresponding to the lower part extracted by the address extraction unit out of the plurality of small areas is the early in the continuous writing of the data area to which the small area belongs in order of address. By determining whether or not the target small area is adjacent to the data area boundary by determining whether or not the target area is adjacent to the boundary located in the direction, the data area release unit, the push access detection unit, the When a request for continuous writing is detected, and when the cache miss determination unit determines the occurrence of the cache miss, the Opening the target data area by opening any of the one or more data areas corresponding to the minutes, the control unit sets a tag associated with the data area opened by the data area opening unit, A tag updating unit that updates the upper part extracted by the address extracting unit; wherein the data writing unit corresponds to the middle part extracted by the address extracting unit and the upper part extracted by the address extracting unit. The small area corresponding to the lower part extracted by the address extraction unit in the data area associated with the tag holding the part is set as the target small area, and the data output by the arithmetic unit is written to the target small area. Things.

  According to the fifth aspect of the present invention, the data holding unit includes a plurality of tag holding units, the address extraction unit extracts each address portion from the address output by the arithmetic unit, and the cache miss determination unit sets the address extraction unit. Performs a cache miss determination based on the extracted address part and the tag associated with the data area, and determines whether the target small area is adjacent to the data area boundary based on the extracted address part. The data area release unit performs release of the data area based on the address portion extracted by the address extraction unit, the tag update unit updates the tag associated with the released data area, and the data write unit Performs writing of data output by the arithmetic unit based on the address portion and the tag extracted by the address extracting unit. For this reason, the control unit further easily and appropriately performs the process of omitting the reading of data into the released data area and the data writing process according to whether the small area to be written is adjacent to the data area boundary. Can be realized.

  In the present invention, the lower part of the address of the main storage device refers to an example in which each small area corresponds to the third and fourth digits excluding the first and second digits from the least significant digit of the address in the embodiment. As shown, it is a part adjacent to the lower side of the middle part, and does not necessarily have to include the lowest part.

  According to a sixth aspect of the present invention, there is provided a data memory cache device for use by interposing between an arithmetic unit and a main storage device accessed by the arithmetic unit, wherein the data memory cache device is associated with an address of the main storage device. A data holding unit having a plurality of data areas for holding data of addresses to be read, and a data holding unit for performing continuous reading, that is, reading data from a continuous address of the main storage device to the arithmetic unit. And a controller that releases the data area in which the continuous reading has been completed without writing back the data held in the data area in which the continuous reading has been completed to the main storage device.

  According to the invention described in claim 6, the control unit writes back the read data area to the main storage device, the data held by the read data area, when the arithmetic unit continuously reads data from consecutive addresses. Open without any. The data area that holds data that is no longer read again by continuous reading is free of trouble even if released, and is written back to the main storage device as long as the data held by the data area is useless data. It is not necessary. As described above, the control unit releases the data area holding unnecessary data without writing back the data, thereby improving the memory access speed without impairing the operation of the arithmetic unit.

  According to a seventh aspect of the present invention, in the data memory cache device according to the sixth aspect, data held in each of the plurality of data areas is read and written to the main storage device at a time, and the plurality of data Each of the areas is divided into a plurality of small areas, data held by each of the plurality of small areas is read and written to the arithmetic unit at a time, and the control unit reads the main memory from the arithmetic unit. When there is a request for continuous reading, which is the reading of data from consecutive addresses of the device, the address output by the arithmetic unit in the target data area, which is a data area corresponding to the address output by the arithmetic unit, Data is read out from the corresponding small area, the target small area, to the arithmetic unit, and the target small area is read in the address order. When adjacent to a data area boundary that is a boundary of the target data area located in the slower direction of the continuous reading, the target data is written back from the target data area to the main storage device without being written back. When the area is released and the target small area is not adjacent to the data area boundary, the target data area is not released.

  According to the invention described in claim 7, the control unit selects whether or not to release the target data area according to whether or not the small area to be read is adjacent to the data area boundary. That is, the control unit releases the target data area when the small area to be read is located at the data area boundary, and does not release it when it is not located at the data area boundary. For this reason, the arithmetic unit can end the continuous reading not only at the address corresponding to the small area adjacent to the data area boundary but also at the address corresponding to the small area not adjacent to the data area boundary.

  The invention according to claim 8 is the data memory cache device according to claim 7, wherein the data holding unit holds a plurality of appropriate flags respectively indicating release or unrelease of the plurality of data areas. The apparatus further includes a proper flag holding unit, and the control unit releases the target data area by setting a proper flag associated with the target data area to a side indicating release.

  According to the invention described in claim 8, the control unit sets the appropriate flag to the predetermined side to release the target data area, so that the target data area can be easily released.

  According to a ninth aspect of the present invention, in the data memory cache device according to the eighth aspect, the control unit detects a pop access detection unit that detects the continuous read request from the arithmetic unit, and the pop access detection unit detects the pop access detection unit. When the unit detects the request for continuous reading, a boundary determination unit that determines whether the target small area is adjacent to the data area boundary, and the pop access detection unit detects the request for continuous reading. In the case, the data read unit that reads the data of the target small area to the arithmetic unit, and when the determination by the boundary determination unit is affirmative, after the data is read by the data read unit, the data is read from the target data area. Release the appropriate flag associated with the target data area without writing back data to the main storage device. Set to the side, if the target small area is not adjacent to the data area boundary is one and a proper flag setting unit is not changed the appropriate flag associated with the said target data area.

  According to the ninth aspect of the present invention, the pop access detecting section detects a request for continuous reading, the boundary determining section determines whether or not the target small area is adjacent to the data area boundary, and the data reading section determines The data of the target small area is read out to the arithmetic unit, and the appropriate flag setting unit sets the appropriate flag according to the determination by the boundary determining unit. For this reason, the control unit can easily realize the process of opening the target data area according to whether the small area to be read is adjacent to the data area boundary.

  According to a tenth aspect of the present invention, there is provided a data memory cache device for use by interposing between an arithmetic unit and a main storage device accessed by the arithmetic unit, and having a plurality of data areas for holding data. The data held in each of the plurality of data areas is read and written to the main storage device at a time, and each of the plurality of data areas is divided into a plurality of small areas. The data held by each of the arithmetic units is a data holding unit that is temporarily read and written to the arithmetic unit, and the arithmetic unit has a continuous read request for reading data from consecutive addresses in the main storage device. The address output by the arithmetic unit in a target data area that is a data area corresponding to the address output by the arithmetic unit; Data is read from the target small area, which is the corresponding small area, to the arithmetic unit, and the target small area is a boundary of the target data area located in the slower direction of the continuous reading with respect to the address order. When the target data area is adjacent to the area boundary, a setting is made to prohibit data write-back from the target data area to the main storage device when the target data area is released, and the target small area is set in the data area. And a control unit that does not perform the setting when it is not adjacent to the boundary.

  According to the tenth aspect of the present invention, when the arithmetic unit reads the data area continuously from the consecutive addresses, the control unit sends the read data area to the main storage device when the data area is opened. Since the setting for prohibiting data write-back is performed, the memory access speed is improved. Further, the control unit selects whether or not to perform a setting to prohibit write-back according to whether or not the small area to be read is adjacent to the data area boundary. That is, when the small area to be read is at the data area boundary, the control unit performs the setting to prohibit the write-back, and does not perform the setting when it is not at the data area boundary. For this reason, the arithmetic unit can end the continuous reading not only at the address corresponding to the small area adjacent to the data area boundary but also at the address corresponding to the small area not adjacent to the data area boundary.

  The data memory cache device according to claim 11, wherein the data holding unit stores the data held in the plurality of data areas and the data held in an address corresponding to the main storage device. And a plurality of dirty flag holding units for holding a plurality of dirty flags respectively indicating a match and a mismatch with the control unit, wherein the control unit sets a dirty flag corresponding to the target data area on the side indicating the match In this way, the above setting is performed.

  According to the eleventh aspect, the data holding unit includes the dirty flag holding unit, and the control unit sets the dirty flag to a predetermined side, thereby performing a setting for prohibiting write-back. For this reason, the control unit can easily perform setting for prohibiting write-back.

  According to a twelfth aspect of the present invention, in the data memory cache device according to the eleventh aspect, the control unit detects a pop access detection unit that detects the continuous read request from the arithmetic unit, and the pop access detection unit When the unit detects the request for continuous reading, a boundary determination unit that determines whether the target small area is adjacent to the data area boundary, and the pop access detection unit detects the request for continuous reading. In the case, when the data reading unit that reads the data of the target small area to the arithmetic unit and the boundary determination unit determines that the data is read by the data reading unit, the data reading unit corresponds to the target data area. The dirty flag is set to the side indicating the match, and when the determination of the data area boundary determination unit is negative, , In which and a dirty flag setting unit is not changed the dirty flag corresponding to the target data area.

  According to the twelfth aspect of the present invention, the pop access detecting section detects a request for continuous reading, the boundary determining section determines whether or not the target small area is adjacent to the data area boundary, and the data reading section determines The data of the target small area is read out to the arithmetic unit, and the dirty flag setting unit sets the dirty flag according to the determination of the boundary determining unit. For this reason, the control unit can easily realize the process of setting the prohibition of the write-back in accordance with whether the small area to be read is adjacent to the data area boundary.

  According to a thirteenth aspect of the present invention, in the data memory cache device according to the ninth or twelfth aspect, the data holding unit determines whether the plurality of data areas are used for either continuous writing or continuous reading. A plurality of stack flag holding units each holding a plurality of stack flags respectively indicating the plurality of stack flags, wherein the control unit controls the data read unit to read the data when the determination by the boundary determination unit is affirmative. After the end, the stack flag corresponding to the target data area is set to the positive side, and if the determination by the boundary determination unit is negative, after the data reading unit finishes reading the data, A stack flag setting unit that does not change the stack flag corresponding to the target data area is further provided.

  According to the thirteenth aspect, the data holding unit includes the stack flag holding unit, and the control unit includes the stack flag setting unit that operates the stack flag according to the position of the target small area after reading the data. Therefore, the control unit uses the non-use period of the data bus to store the data in the data area from which data has been read out in the course of continuous reading, before releasing the data area due to a cache miss. In the case of employing a configuration in which data is written back to the device in advance, by using a stack flag, it is possible to avoid unnecessary use of data in a data area not allocated to the stack.

  The invention according to claim 14 is the data memory cache device according to claim 9, 12 or 13, wherein the plurality of data areas are associated with a middle part of an address of the main storage device, Each of the plurality of small areas is associated with a lower part of the address of the main storage device, and one or more data areas correspond to the same value of the middle part of the address of the main storage device, The data holding unit further includes a plurality of tag holding units that hold a plurality of tags each indicating an upper part of an address of data held by the plurality of data areas, and the control unit includes an address output by the arithmetic unit. Further comprising an address extracting unit for extracting the upper part, the middle part, and the lower part from the above, wherein the boundary determining unit extracts the address extracted from the plurality of small areas by the address extracting unit. By determining whether or not the small area corresponding to the lower part is adjacent to a boundary of the data area to which the small area belongs in the order of address in the slower direction of the continuous reading, the target small area is The data reading unit determines whether or not it is adjacent to a data area boundary, and associates the data reading unit with a tag corresponding to the middle part extracted by the address extraction unit and indicating the upper part extracted by the address extraction unit. The small area corresponding to the lower part extracted by the address extraction unit in the obtained data area is set as the target small area, and the data of the target small area is read out to the arithmetic unit.

  According to the invention described in claim 14, the data holding unit includes a plurality of tag holding units, the address extraction unit extracts each address portion from the address output by the arithmetic unit, and the boundary determination unit outputs the extracted address. The data reading unit determines whether or not the target small area is adjacent to the data area boundary based on the portion, and reads the data to the arithmetic unit based on the address portion and the tag extracted by the address extracting unit. . For this reason, the control unit can more easily realize the setting of releasing the unnecessary data area after the continuous reading has been completed without writing back, or the setting of prohibiting the writing back due to the release of the unnecessary data area.

  An invention according to claim 15 is a data memory cache device for use interposed between an arithmetic unit and a main storage device accessed by the arithmetic unit, wherein the data memory cache device is associated with an address of the main storage device. A data holding unit having a plurality of data areas for holding data of addresses to be written, and a period for executing continuous writing that is writing of data from the arithmetic unit to continuous addresses of the main storage device, In addition, during a period in which a data bus for transferring data between the data holding unit and the main storage device is not used, the address order is positioned in a direction of continuous writing earlier than continuous writing currently performed. A control unit for writing back data from the data area in the data holding unit to the main storage device.

  According to the invention described in claim 15, during the period in which the continuous writing is performed, the control unit deletes the data in the data area located in the direction of the continuous writing earlier than the current continuous writing with respect to the address order. Before the data area is released, the data is written back to the main storage device in advance using the non-use period of the data bus (that is, free time). This increases the memory access speed because the control unit does not need to perform write-back when releasing the data area that is likely to have completed the continuous writing and is therefore unlikely to be immediately read later. I do.

  The invention according to claim 16 is the data memory cache device according to claim 15, wherein the control unit detects the continuous write request from the arithmetic unit and the push access detection unit. An offset calculating unit that calculates an offset address that is an address shifted from the address output by the arithmetic unit at a predetermined interval in the direction of the continuous writing when the unit detects the request for the continuous writing; and A cache miss determining unit for determining whether there is a cache miss, a transfer busy determining unit for determining whether the data bus is in use, and the cache miss determining unit determining that there is no cache miss, and When the busy determination unit determines that the data bus is not used, In which the data area corresponding to full set address and a write-back unit that performs write back of data to the main storage device.

  According to the invention of claim 16, the push access detection unit detects a request for continuous writing, the offset calculation unit calculates an offset address, the cache miss determination unit determines whether or not a cache miss has occurred for the offset address, A transfer busy determining unit determines whether or not the data bus is in use, and a write-back unit determines a data area corresponding to the offset address according to the determination of the cache miss determining unit and the determination of the transfer busy determining unit. Writes data back to the main storage device. Therefore, the control unit writes the data in the data area which is likely to be the data area for which the continuous writing has been completed to the main storage device using the unused period of the data bus before the data area is released. The returning process can be easily and appropriately realized.

  The invention according to claim 17 is the data memory cache device according to claim 16, wherein the plurality of data areas are associated with a middle part of an address of the main storage device, and One or more data areas correspond to the same value of the portion, and each of the plurality of data areas is divided into a plurality of small areas associated with the lower part of the address. The data held in each of the areas is temporarily read and written to the main storage device, the data held in each of the plurality of small areas is temporarily read and written to the arithmetic unit, and the data holding unit includes: The image processing apparatus further includes a plurality of tag holding units that hold a plurality of tags each indicating an upper part of an address of data held by the plurality of data areas, wherein the control unit outputs the arithmetic unit. An address extracting unit that extracts the upper part, the middle part, and the lower part from the dress, wherein the offset calculating unit detects the address when the push access detecting unit detects the request for continuous writing. An address deviated from the address represented by the middle part and the high part extracted by the extraction unit at a predetermined interval in the direction of the continuous writing earlier is calculated as the offset address, and the cache miss determination unit is Comparing the value indicated by the tag associated with each of the one or more data areas corresponding to the middle part of the offset address with the upper part of the offset address, and if none of the values match, a cache miss occurs. Is determined to have occurred.

  According to the invention described in claim 17, the data holding unit includes a plurality of tag holding units, the address extraction unit extracts each address portion from the address output by the operation unit, and the offset calculation unit sets the address extraction unit. An offset address is calculated based on the extracted address portion, and the cache miss determining unit determines a cache miss based on the address portion extracted by the address extracting unit and the tag associated with the data area. Therefore, the control unit can easily calculate the offset address and determine the cache miss.

  An invention according to claim 18 is a data memory cache device for use interposed between an arithmetic unit and a main storage device accessed by the arithmetic unit, wherein the data memory cache device is associated with an address of the main storage device. A data holding unit including a plurality of data areas for holding data of addresses to be read, and a period during which continuous reading of reading data from a continuous address of the main storage device to the arithmetic unit is performed, and During a period in which a data bus for transferring data between the data holding unit and the main storage device is not used, the address sequence is located in a direction in which continuous reading is earlier than continuous reading which is currently being performed. A control unit for writing back data from the data area in the data holding unit to the main storage device.

  According to the invention described in claim 18, the controller reads the data in the data area positioned in the direction of the continuous reading earlier than the current continuous reading with respect to the address order during the period of performing the continuous reading. Before the data area is released, the data is written back to the main storage device in advance using the non-use period of the data bus (that is, free time). This increases the memory access speed because the control unit does not need to perform write-back when releasing the data area that is likely to have completed the continuous read operation and is therefore unlikely to be read again later. I do.

  The invention according to claim 19 is the data memory cache device according to claim 18, wherein the control unit detects a pop access detection unit that detects the continuous read request from the arithmetic unit, and the pop access detection unit detects the pop access detection. An offset calculating unit that calculates an offset address that is an address shifted from the address output by the arithmetic unit at a predetermined interval in a direction in which the continuous reading is performed, when the unit detects the request for the continuous reading, A cache miss determining unit for determining whether there is a cache miss, a transfer busy determining unit for determining whether the data bus is in use, and the cache miss determining unit determining that there is no cache miss, and If the busy determination unit determines that the data bus is not used, the From the data area corresponding to Ttoadoresu those and a write back unit which performs write back of data to the main storage device.

  According to the invention of claim 19, the pop access detection unit detects a request for continuous reading, the offset calculation unit calculates an offset address, the cache miss determination unit determines whether or not a cache miss has occurred for the offset address, A transfer busy determining unit determines whether or not the data bus is in use, and a write-back unit determines a data area corresponding to the offset address according to the determination of the cache miss determining unit and the determination of the transfer busy determining unit. Writes data back to the main storage device. Therefore, the control unit writes the data in the data area which is likely to be the data area for which continuous reading has been completed to the main storage device in advance using the unused period of the data bus before the data area is released. The returning process can be easily and appropriately realized.

  The invention according to claim 20 is the data memory cache device according to claim 19, wherein the plurality of data areas are associated with a middle part of an address of the main storage device, and One or more data areas correspond to the same value of the portion, and each of the plurality of data areas is divided into a plurality of small areas associated with the lower part of the address. The data held in each of the areas is temporarily read and written to the main storage device, the data held in each of the plurality of small areas is temporarily read and written to the arithmetic unit, and the data holding unit includes: The image processing apparatus further includes a plurality of tag holding units that hold a plurality of tags each indicating an upper part of an address of data held by the plurality of data areas, wherein the control unit outputs the arithmetic unit. An address extracting unit that extracts the upper part, the middle part, and the lower part from the dress, wherein the offset calculating unit detects the address when the pop access detecting unit detects the continuous read request. An address deviated from the address represented by the middle part and the high part extracted by the extraction unit at a predetermined interval in the direction in which the continuous reading is performed earlier is calculated as the offset address, and the cache miss determination unit calculates Comparing the value indicated by the tag associated with each of the one or more data areas corresponding to the middle part of the offset address with the upper part of the offset address, and if none of the values match, a cache miss occurs. Is determined to have occurred.

  According to the twentieth aspect, the data holding unit includes a plurality of tag holding units, the address extracting unit extracts each address portion from the address output by the arithmetic unit, and the offset calculating unit sets the address extracting unit. An offset address is calculated based on the extracted address portion, and the cache miss determining unit determines a cache miss based on the address portion extracted by the address extracting unit and the tag associated with the data area. Therefore, the control unit can easily calculate the offset address and determine the cache miss.

  The invention according to claim 21 is the data memory cache device according to claim 16, 17, 19 or 20, wherein the data holding unit uses the plurality of data areas for either continuous writing or continuous reading. A plurality of stack flag holding units each holding a plurality of stack flags each indicating whether or not the cache miss determination unit has determined that there is no cache miss, and the transfer busy determination unit When it is determined that the data bus is not used, only when the stack flag corresponding to the data area corresponding to the offset address is set to the positive side, the data area corresponding to the offset address is This is for writing back data to the main storage device.

  According to the twenty-first aspect, the data holding unit includes the stack flag holding unit, and the write-back unit also selects whether or not to perform data write-back with reference to the stack flag. Thereby, the write-back unit can avoid performing useless write-back on a data area where data other than continuous writing has been written or a data area where data has been read other than continuous reading.

  The invention according to claim 22 is the data memory cache device according to claim 16, 17, 19, 20, or 21, wherein the data holding unit indicates that the plurality of data areas are released or not released. A plurality of appropriate flag holding units for holding the appropriate flags, wherein the write-back unit determines that the cache miss determination unit determines that there is no cache miss, and the transfer busy determination unit determines that the data bus is not used. When the determination is made, furthermore, only when the appropriate flag corresponding to the data area corresponding to the offset address is set to the side indicating the non-open state, the data area corresponding to the offset address is transferred to the main storage device. This is for writing back data.

  According to the twenty-second aspect, the data holding unit includes the appropriate flag holding unit, and the write-back unit selects whether or not to perform data write-back with reference to the appropriate flag. Thus, the write-back unit can avoid performing useless write-back on the data area that has already been released.

  An invention according to claim 23 is a data memory cache device for use interposed between an arithmetic unit and a main storage device accessed by the arithmetic unit, wherein the data memory cache device is associated with an address of the main storage device. A data holding unit including a plurality of data areas for holding data of addresses to be read, and a period during which continuous reading of reading data from a continuous address of the main storage device to the arithmetic unit is performed, and During a period in which a data bus for transferring data between the data holding unit and the main storage device is not used, the position of the address is located in the direction of continuous reading slower than the current continuous reading with respect to the address order. A control unit for reading data from the main storage device into a data area in the data holding unit.

  According to the twenty-third aspect of the present invention, the control unit sets the non-use period (i.e., idle time) of the data bus to the data area where the reading is expected to be performed later during the period of performing the continuous reading. Using this, data is read from the main storage device in advance. Thus, the control unit can save time for reading data from the main storage device to the data area from which data is to be read. As a result, the memory access speed is improved.

  According to a twenty-fourth aspect of the present invention, in the data memory cache device according to the twenty-third aspect, the control unit is configured to detect the continuous read request from the arithmetic unit and the pop access detection unit. An offset calculating unit that calculates an offset address, which is an address shifted from the address output by the arithmetic unit at a predetermined interval in a slower direction of the continuous reading when the unit detects the request for the continuous reading; and A transfer busy determination unit for determining whether or not the data bus is in use; and when the transfer busy determination unit determines that the data bus is not used, the transfer of the data from the main storage device to the data area corresponding to the offset address. And a refill unit for reading.

  According to the invention described in claim 24, the pop access detection unit detects a request for continuous reading, the offset calculation unit calculates an offset address, and the transfer busy determination unit determines whether the data bus is in use. And the refill unit reads the data from the main storage device into the data area corresponding to the offset address according to the determination of the transfer busy determination unit. For this reason, the control unit can easily realize the process of reading data from the main storage device in advance to the data area where the reading is expected to be performed by using the non-use period of the data bus.

  The invention according to claim 25 is the data memory cache device according to claim 24, wherein the data holding unit determines whether or not the plurality of data areas are used for either continuous writing or continuous reading. Further comprising a plurality of stack flag holding units for holding a plurality of stack flags shown, wherein the refill unit stores a data area corresponding to the offset address when the transfer busy determination unit determines that the data bus is not used. Data is read from the main storage device to the data area corresponding to the offset address only when the corresponding stack flag is set positively.

  According to the twenty-fifth aspect, the data holding unit includes the stack flag holding unit, and the refill unit selects whether to read the data with reference to the stack flag. Thus, the refill unit can avoid performing unnecessary reading on a data area that has not been set as a target of continuous writing, that is, a data area that is not set as a target of continuous reading.

  According to a twenty-sixth aspect of the present invention, in the data memory cache device according to the twenty-fourth or twenty-fifth aspect, the data holding unit holds a plurality of appropriate flags indicating release or non-release of the plurality of data areas. A plurality of appropriate flag holding units, wherein the refill unit is configured to release the appropriate flag corresponding to the data area corresponding to the offset address when the transfer busy determining unit determines that the data bus is not used. Data is read from the main storage device to the data area corresponding to the offset address only when set to the indicated side.

  According to the twenty-sixth aspect, the data holding unit includes the appropriate flag holding unit, and the refill unit refers to the appropriate flag and selects whether or not to read data. Thereby, the refill unit can avoid performing useless reading on the unreleased data area.

  The invention according to claim 27 is the data memory cache device according to any one of claims 24 to 26, wherein the plurality of data areas are associated with a middle part of an address of the main storage device. And one or more data areas correspond to the same value of the middle part, and each of the plurality of data areas is divided into a plurality of small areas corresponding to the lower part of the address. The data held by each of the plurality of data areas is read and written to the main storage device at a time, and the data held by each of the plurality of small areas is read and written to the arithmetic unit at a time, and The data holding unit further includes a plurality of tag holding units that hold a plurality of tags each indicating an upper part of an address of data held by the plurality of data areas, and the control unit includes An address extraction unit that extracts the upper part, the middle part, and the lower part from an address output by the unit, wherein the offset calculation unit detects that the pop access detection unit has detected the continuous read request. And calculating, as the offset address, an address shifted from the address represented by the middle part and the high part extracted by the address extraction unit at a predetermined interval in the slower direction of the continuous reading. .

  According to the twenty-seventh aspect, the data holding unit includes a plurality of tag holding units, the address extraction unit extracts each address portion from the address output by the arithmetic unit, and the offset calculation unit sets the address extraction unit. An offset address is calculated based on the extracted address portion. For this reason, the control unit can easily calculate the offset address.

  The invention according to claim 28 is the data memory cache device according to claim 27, wherein the control unit is associated with each of the one or more data areas corresponding to the middle part of the offset address. Comparing the value indicated by the tag with the upper part of the offset address, and if none of the values match, a cache miss determination unit that determines that a cache miss has occurred for the offset address; and A data area release unit that releases any one of the one or more data areas corresponding to the middle part of the offset address when it is determined that a cache miss has occurred; and a data area that is released by the data area release unit. And a tag updating unit that updates a tag associated with the tag with the upper part of the offset address. It is intended.

  According to the invention described in claim 28, the cache miss determination unit caches the offset address based on the offset address calculated by the offset address calculation unit and the tag associated with the data area corresponding to the offset address. After making a determination of a mistake, the data area release unit releases the data area based on the offset address calculated by the offset address calculation unit, and the tag update unit updates the tag associated with the released data area. Therefore, the control unit can read data from the main storage device into the data area corresponding to the offset address even if there is a cache miss at the offset address.

  An invention according to claim 29 is a data memory cache system, wherein the data memory cache device according to any one of claims 1 to 28, an operation unit connected to the data memory cache device, and the data memory A main storage device connected to the cache device and accessed by the arithmetic unit.

  According to the invention described in claim 29, the data memory cache system is a data memory cache device of the present invention, an operation unit connected to the device, and a main storage device connected to the device and accessed by the operation unit. Therefore, the memory access speed can be increased.

  As described above, according to the data memory cache device and the data memory cache system of the present invention, the memory access speed can be increased.

  An embodiment of the invention according to the present patent application (hereinafter, appropriately referred to as “the present invention”) will be described with reference to the drawings.

(1. System configuration)
A data memory cache device according to the first embodiment of the present invention and a data memory cache system including the device (hereinafter, each will be simply referred to as “cache device” and “cache system” unless otherwise specified. 1) shows the block configuration of FIG. Since the instruction memory cache device and the instruction memory cache system are not directly related to the present invention, the description is omitted.

  The cache system 100 according to the present embodiment mainly includes an arithmetic unit 113, a memory management unit 115 (hereinafter, appropriately referred to as “MMU 115”), a stack-compatible data cache unit 117 (hereinafter, except for the case where it is particularly necessary to distinguish between them). A cache unit 117), a transfer control unit 119, and a main storage device 131. The cache unit 117 corresponds to one embodiment of the data memory cache device of the present invention.

  The arithmetic unit 113 is generally called an MPU or a CPU (in a narrow sense) or a processor, and fetches and executes various arithmetic instructions, data movement instructions, control instructions, and other instructions from an instruction memory. Hereinafter, the MPU is taken up as an example of the arithmetic unit 113, and is described as “MPU 113” as appropriate. Of course, this is not intended to limit the arithmetic unit of the present invention to the MPU.

  The MPU 113 particularly has a dedicated register SP (stack pointer) for storing a memory address. The memory address (memory address) indicated by the stack pointer is called a stack top. As the stack pointer, a general-purpose register Rm (register m) can be used in addition to the dedicated SP. Such an implementation is particularly effective when a general-purpose CPU is used as a Java (registered trademark) virtual machine.

  Hereinafter, unless otherwise confused, terms such as “stack pointer (SP)” or “stack pointer (SP) access” are used when a dedicated SP register is used and when a general-purpose register is used (for example, Rm or Rn). Is not particularly distinguished from the case where is used, and is used in a meaning including both.

  The MPU 113 prepares a push instruction (push instruction), a pop instruction (pop instruction), a load instruction (load instruction), a store instruction (store instruction), and other instructions as a part of the data movement instruction. The push instruction is an instruction for decrementing the content of the SP by 4 (that is, decrementing by 4) and writing 4-byte data to the stack top (writing from the MPU 113 to the memory). The pop instruction is an instruction to read data from the top of the stack, for example, by 4 bytes (read from the memory to the MPU 113) and add the contents of the SP by four. The load instruction is an instruction for performing memory reading at a relative address from the stack top. The store instruction is an instruction for performing memory writing at a relative address from the stack top. The MPU 113 prepares, as other data movement instructions, instructions for directly and randomly accessing a memory at an arbitrary address specified by various methods, such as a direct address, a register indirect address, and a register relative address.

  2A, 2B, 2C, and 2D, the “instruction” column on the left side shows typical instruction formats of push, pop, load, and store among these data movement instructions. . The push instruction is a specific example of an instruction for writing data to consecutive addresses in the main storage device 131. The pop instruction is a specific example of an instruction for reading data from consecutive addresses in the main storage device 131. The instruction format illustrated in FIG. 2 uses the general-purpose register Rm or the general-purpose register Rn as a stack pointer. Also, in this description, the unit of memory access by these instructions is 4 bytes, and the unit value for increasing / decreasing the stack pointer before and after data movement by the push / pop instruction is 4. However, this is an example, Any value is acceptable.

  The “instruction” column on the left side of FIG. 2A indicates the instruction format of the push instruction. In this format, the MPU 113 uses the Rm register as a stack pointer. The “operation” column on the right side of FIG. 2A shows the operation performed by executing this instruction.

  When this push instruction is executed, first, the content of Rm is decremented by four. Next, the contents of the Rn register are written to the memory by specifying the Rm indirect address. That is, the contents of the Rn register are written to the memory at the address indicated by the contents of the Rm register. Then, the push / pop modification bit is turned on. As shown in FIG. 1, the content of the push / pop modifier bit is used to notify the cache unit 117 of the execution of the push / pop instruction from the MPU 113 via the control line.

  The “instruction” column on the left side of FIG. 2B indicates the instruction format of the pop instruction. In this format, the MPU 113 uses the Rn register as a stack pointer. The “operation” column on the right side of FIG. 2B shows the operation performed by executing this instruction.

  When this pop instruction is executed, first, a push / pop modification bit is turned on. As described above, the content of the push / pop modifier bit is used to notify the cache unit 117 of the execution of the push / pop instruction from the MPU 113 via the control line. Next, the contents of the memory are read into the Rm register by specifying the Rn indirect address. That is, the contents of the memory at the address indicated by the contents of the Rn register are read into the Rm register. Then, the content of Rn is incremented by 4 (that is, incremented by 4).

  The “instruction” column on the left side of FIG. 2C indicates the instruction format of the load instruction. In this format, the MPU 113 uses the Rn register as a stack pointer. The “operation” column on the right side of FIG. 2C shows the operation performed by executing this instruction.

  When this load instruction is executed, first, the SP relative modification bit is turned on. As shown in FIG. 1, the contents of the SP relative modification bit are used to notify the cache unit 117 from the MPU 113 via the control line that the load / store instruction has been executed by specifying the SP relative address. Next, the contents of the memory are read into the Rm register by indirect addressing by adding an offset value to the contents of the Rn register. That is, the contents of the memory at the address indicated by the value obtained by adding the offset value to the contents of the Rn register are read into the Rm register. The contents of Rn used as SP are not added or subtracted.

  The “instruction” column on the left side of FIG. 2D indicates the instruction format of the store instruction. In this format, the MPU 113 uses the Rm register as a stack pointer. The “operation” column on the right side of FIG. 2D shows the operation performed by executing this instruction.

  When the store instruction is executed, the contents of the Rn register are written to the memory by indirect addressing by adding an offset value to the contents of the Rm register. That is, the contents of the Rn register are written to the memory at the address indicated by the value obtained by adding the offset value to the contents of the Rm register. Then, the SP relative modification bit is turned on. As described above, the content of the SP relative modification bit is used to notify the cache unit 117 from the MPU 113 via the control line that the load / store instruction has been executed by specifying the SP relative address. It is also the same as above that the content of Rm used as SP is not added or subtracted.

  When a data move instruction including these instructions is executed by the MPU 113, if the data move instruction accesses the external memory, the MPU 113 outputs a logical address of the external memory to be accessed to the virtual address bus. The cache read request or cache write request bit signal lines are turned on, respectively, depending on whether the data access is reading or writing data from the memory. If the data access is the writing of data to the memory, the MPU 113 simultaneously outputs the data to be written to the 32-bit data bus. The logical address output to the virtual data bus is converted into a physical address by the MMU 115 and output to the real address bus. The cache unit 117 receiving these data determines whether or not the memory to be accessed is present in the cache.

  As described above, the control signal lines used to access the memory from the MPU used in the present embodiment are four (4 bit) for transmitting push / pop qualification, SP relative qualification, cache read request, and cache write request. ). FIG. 3 shows possible combinations of the instructions executed by the MPU 113, the operations thereof, and the states of the control lines.

  FIG. 3A shows a case where both the cache read request and the cache write request are off (0). In this case, no operation related to read / write of the cache memory is performed regardless of the push / pop decoration and the SP relative decoration.

  FIG. 3B shows a case where the cache read request is off (0), the cache write request is on (1), and both the push / pop qualification and the SP relative qualification are off (0). That is, FIG. 3B shows the operation when a random write instruction to the memory is executed and the state of the control signal line at that time.

  FIG. 3C shows a case where the cache read request is off (0), the cache write request is on (1), the push / pop modifier is off (0), and the SP relative modifier is on (1). . That is, FIG. 3C shows the operation when the SP relative write (store) instruction for the memory is executed and the state of the control signal line at that time.

  FIG. 3D shows a case where the cache read request is off (0), the cache write request is on (1), the push / pop qualification is on (1), and the SP relative qualification is off (0). . That is, FIG. 3D shows the operation when the push instruction for the memory is executed and the state of the control signal line at that time.

  FIG. 3E shows a case where the cache read request is off (0), the cache write request is on (1), and both the push / pop qualification and the SP relative qualification are on (1). Usually, such a state is not assumed. That is, such a state does not normally occur.

  FIG. 3F shows a case where the cache read request is on (1), the cache write request is off (0), and both the push / pop qualification and the SP relative qualification are off (0). That is, FIG. 3F shows an operation when a random read instruction for the memory is executed and a state of the control signal line at that time.

  FIG. 3G shows a case where the cache read request is on (1), the cache write request is off (0), the push / pop qualification is off (0), and the SP relative qualification is on (1). . That is, FIG. 3G shows the operation when the SP relative read (load) instruction for the memory is executed and the state of the control signal line at that time.

  FIG. 3H shows a case where the cache read request is on (1), the cache write request is off (0), the push / pop qualification is on (1), and the SP relative qualification is off (0). . That is, FIG. 3H shows the operation when the pop instruction for the memory is executed and the state of the control signal line at that time.

  FIG. 3 (i) shows a case where the cache read request is on (1), the cache write request is off (0), and both the push / pop qualification and the SP relative qualification are on (1). Usually, such a state is not assumed. That is, such a state does not normally occur.

  FIG. 3 (j) shows a case where both the cache read request and the cache write request are on (1). Generally, such a state is not assumed regardless of the push / pop modification and the SP relative modification. That is, such a state does not usually occur.

  FIG. 4 is a block diagram showing the configuration of the cache unit 117. The cache unit 117 includes a data holding unit 300 and a control unit 200. The configuration of the data holding unit 300 is depicted in FIG. The data holding unit 300 of the cache unit 117 according to the present embodiment has a configuration of 256 sets and 4 ways. However, the data memory cache device of the present invention is not limited to this configuration, and can adopt any other configuration.

  FIG. 6 is a configuration diagram showing a configuration of a line included in the data holding unit 300 shown in FIG. As shown in FIG. 6, each line has a data area for holding data, a flag holding unit for holding three types of control bits (flags) used for control, and a tag holding unit for holding a tag. Part.

  Each data area holds 16-byte (4 words, 128 bits) data that is read and written to the main storage device 131 at a time, and has a storage capacity of 16 bytes. Each data area is divided into four small areas for holding data in units of one word (4 bytes) that are simultaneously read from and written to the MPU 113. Each tag holding unit holds a tag having a width of 20 bits. Each flag holding unit is a proper flag holding unit that holds a 1-bit valid flag (property flag), a dirty flag holding unit that holds a dirty flag (dirty flag), and a stack flag that holds a stack flag (stack flag). It has a holding part. FIG. 7 shows possible combinations of these three types of flags and the meanings of the combinations. FIG. 7 will be referred to in the description of the operation of the cache system 100 described later.

  Returning to FIG. 4, the control unit 200 controls the data holding unit 300. The control unit 200 includes a random write detection unit 5, a random read detection unit 6, an SP relative write detection unit 7, an SP relative read detection unit 8, a push access detection unit 11, a pop access detection unit 12, an address extraction unit 13, and an offset calculation. Unit 14, transfer busy determination unit 15, data writing unit 21, data reading unit 22, boundary determination unit 23, cache miss determination unit 24, line release unit 25, tag update unit 26, flag setting unit 27, refill unit 28, and write The back part 29 is provided as a main element.

  The random write detection unit 5 detects a data write request accompanying execution of a random write instruction from the MPU 113. More specifically, when the push / pop qualification and the SP relative qualification are negated and the cache write request is asserted, the random write detection unit 5 has a data write request accompanying the execution of the random write instruction. Is determined.

  The random read detection unit 6 detects a data read request accompanying the execution of a random read instruction from the MPU 113. More specifically, when the push / pop qualification and the SP relative qualification are negated and the cache read request is asserted, the random read detection unit 6 has a data read request accompanying the execution of the random read instruction. Is determined.

  The SP relative write detection unit 7 detects a data write request accompanying the execution of the SP relative write instruction from the MPU 113. More specifically, when both the SP relative modification and the cache write request are asserted, the push access detection unit 11 determines that there is a data write request accompanying the execution of the SP relative write instruction. The SP relative read detection unit 8 detects a data read request accompanying the execution of the SP relative read instruction from the MPU 113. More specifically, when both the SP relative modification and the cache read request are asserted, the SP relative read detection unit 8 determines that there is a data read request accompanying the execution of the SP relative read instruction.

  The push access detection unit 11 detects a data write request accompanying execution of a push instruction from the MPU 113. More specifically, when both the push / pop qualification and the cache write request are asserted, the push access detection unit 11 determines that there is a data write request accompanying the execution of the push instruction. The pop access detection unit 12 detects a data read request from the MPU 113 accompanying execution of the pop instruction. More specifically, when both the push / pop qualification and the cache read request are asserted, the pop access detection unit 12 determines that there is a data read request accompanying the execution of the pop instruction.

  The following elements in the control unit 200 include the above-described random write detection unit 5, random read detection unit 6, SP relative write detection unit 7, SP relative read detection unit 8, push access detection unit 11, and pop access detection unit 12 Performs an operation in accordance with each instruction based on the detection result of.

  From the 32-bit address output from the MPU 113, the address extraction unit 13 outputs the middle 8 bits of the address associated with each set (FIG. 5), the upper 20 bits of the address to be compared with the tag, and the small area ( The lower two bits associated with FIG. 6) are extracted. Here, the lower two bits are two bits adjacent to the lower side of the middle eight bits of the address, in other words, a part corresponding to the third and fourth bits from the lowest.

  When the MPU 113 executes the push instruction or the pop instruction, the offset calculation unit 14 calculates an offset address that is an address shifted from the address output by the MPU 113 at a predetermined interval. The offset address will be described later.

  The transfer busy determination unit 15 determines whether a data bus for transferring data between the cache unit 117 and the main storage device 131 is in use. More specifically, the transfer busy determination unit 15 determines that the data bus is in use when the transfer busy response output from the transfer control unit 119 is asserted. Here, the data bus corresponds to the transfer data bus in the example of FIG. 1 in which the transfer control unit 119 is interposed.

  The data writing unit 21 writes the data output by the MPU 113 to a small area corresponding to the address output by the MPU 113 when the MPU 113 requests data writing. The data reading unit 22 reads data from the small area corresponding to the address output by the MPU 113 to the MPU 113 when the MPU 113 requests data reading.

  When the MPU 113 executes the push instruction, the boundary determination unit 23 determines that the small area corresponding to the address output by the MPU 113 is the boundary of the data area to which the small area belongs, on the opposite side in the direction in which the address advances ( In the following, it is determined whether or not it is adjacent to a “line boundary”. Further, when the MPU 113 executes the pop instruction, the boundary determining unit 23 determines that the small area corresponding to the address output by the MPU 113 is a boundary in the direction in which the address is advanced among the boundaries of the data area to which the small area belongs. In this case, it is determined whether or not it is adjacent to the “line boundary”.

  In FIG. 6, assuming that the address rises downward, if the address output by the MPU 113 falls along with the execution of the push instruction, that is, if the address moves upward in FIG. Are located at the higher address (lower in FIG. 6) of the data area. In this case, as indicated by hatching at the right end of FIG. 6, among the four small areas belonging to the data area, the small area adjacent to the line boundary is the small area having the highest address (the lowest area in FIG. 6). Small area located). When the address output by MPU 113 increases with the execution of the pop instruction, that is, when the address moves downward in FIG. 6, the line boundary is located at the higher address of the data area (downward in FIG. 6). . In this case, as indicated by hatching at the right end of FIG. 6, among the four small areas belonging to the data area, the small area adjacent to the line boundary is the small area having the highest address (the lowest area in FIG. 6). Small area located). That is, the line boundary and the small area adjacent to the line boundary are common between the push instruction and the pop instruction.

  The cache miss determination unit 24 determines whether or not a cache miss has occurred in the data area corresponding to the address output by the MPU 113. When the offset calculation unit 14 calculates the offset address, the MPU 113 also determines whether a cache miss has occurred in the data area corresponding to the calculated offset address. The line release unit 25 releases the data area for which a cache miss has been determined. Hereinafter, the release of the data area is appropriately referred to as “release of a line” in accordance with a custom in the art. Further, since one data area is provided for each line, the data area is appropriately referred to as a “line”. Note that the line release unit 25 corresponds to a specific example of the data area release unit of the present invention.

  The flag setting unit 27 sets the three types of flags to the positive side or the negative side. The flag setting unit 27 includes three types of flag setting units corresponding to the three types of flags, namely, an appropriate flag setting unit, a dirty flag setting unit, and a stack flag setting unit, as indicated by reference numerals v, d, and s in FIG. Have. Further, the flag setting unit 27 may be provided for each corresponding line.

  The write-back unit 29 writes back data from the data area to the main storage 131 when a cache miss occurs in the data area corresponding to the address output by the MPU 113 and the data area is released as a result. Back). The refill unit 28 reads (refills) data from the main storage device 131 into the data area after a cache miss has occurred in the data area corresponding to the address output by the MPU 113 and, as a result, the data area has been released. Is what you do. The tag updating unit 26 updates a tag associated with the released data area with a new address.

(2. System operation)
The cache control performed by the cache system 100 according to the present embodiment will be described below with reference to FIGS.

(2-1. Random read)
FIG. 8 is a sequence diagram showing an operation of the cache system 100 when the MPU 113 executes a random read instruction. 8 and the following sequence diagrams incorporate a flowchart in order to also show details of the operation of the cache unit 117 at the same time. In the following sequence diagrams, broken lines with arrows represent signals exchanged between the MPU 113, the cache unit 117, and the main storage device 131.

  When the MPU 113 starts executing the random read instruction, the MPU 113 shown in FIG. 1 turns on (that is, asserts) a cache read request, and simultaneously outputs a logical address indicating a memory area to be read to the virtual address bus. Further, the MPU 113 keeps the SP relative modification and the push / pop modification off (that is, negated). By receiving these signals, the random read detection unit 6 of the cache unit 117 detects that the MPU 113 has issued a data read request accompanying execution of the random read instruction. Accordingly, the control unit 200 of the cache unit 117 turns on the cache busy response. The MPU 113 confirms that the cache busy response has been turned on, and turns off (ie, negates) the cache read request. In this specification, asserting a control signal is appropriately expressed as “turning on”, and negating is expressed as “turning off” as appropriate.

  The MMU 115 converts the upper 20 bits of the virtual address bus into the upper 20 bits of the physical address, and outputs it to the real address bus. The lower 12 bits of the virtual address bus are directly output to the real address bus.

  As described above, upon receiving the cache read request signal, control unit 200 first turns on the cache busy response signal. Next, in step S1, the cache miss determination unit 24 of the cache unit 117 selects one set in each way using the middle 8 bits of the real address extracted by the address extraction unit 13 as a key, and selects the selected set. Read the value of the tag.

  As illustrated in FIG. 5, it is assumed that the cache unit 117 according to the present embodiment has a configuration of 256 sets and 4 ways. Therefore, for example, the upper 20 bits of the address bus are “0001 1001 1100 0000 1111 (0x19C0F in hexadecimal notation)” in binary notation. For example, the middle 8 bits of the address bus are “0010 1000 (hexadecimal notation) in binary notation. It is assumed that the expression is 0x28 and the decimal expression is "40"). In this case, the cache miss determination unit 24 selects any one of the four lines included in the “set 40” as a line that may be used for the cache.

  Next, the cache miss determination unit 24 compares the upper 20 bits of the real address bus with the read tag value (20 bits), and if there is a match, the cache hits, that is, it is determined that no cache miss has occurred. It is determined (Yes in S1). In the above example, since the upper 20 bits of the address bus are “0x19C0F”, if any of the tags included in the line included in the set 40 is the same “0x19C0F”, the cache miss determination unit 24 determines that the cache has hit.

  The operations (S2 to S4, S21, S24) when it is determined that the cache hits (Yes in S1) are shown in the left column “random read” of “operation” in FIGS. 9B to 9G. 9B to 9E show the operations (S21, S24) when the cache hits (Yes in S1) and the valid flag of this line is 1 (Yes in S2). The state at this time corresponds to FIGS. 7 (e) to 7 (h). Since the contents of the line at this time match the contents of the main storage device 131 or are newer than the contents of the main storage device 131, the data reading unit 22 reads the lower 16 bits of the real address bus from all 16 bytes contained in this line. The data corresponding to the bit is read and output to a 32-bit data bus (S3). After that, the control unit 200 turns off the cache busy response signal.

  At this time, if the stack flag is 1, the operation state corresponds to the state shown in FIGS. 7F and 7H, and the flag setting unit 27 sets the stack flag as shown in FIGS. 9C and 9E. It is set to 0 (S3). The MPU 113 detects that the cache busy response signal has been turned off, and reads the data sent to the data bus (S10).

  The operations (S21, S24) when the cache hits but the valid flag is 0 (No in S2) are shown in FIGS. 9 (f) and 9 (g). The state at this time corresponds to FIGS. 7A and 7B. This state corresponds to the fact that the value of the upper 20 bits of the address bus coincides with the content of the tag, but the line has already been released and has not been actually cached. That is, in this state, since the content of the main storage device 131 is newer than the content of the line, the control unit 200 needs to perform a refill for reading the corresponding content of the main storage device 131 into the cache memory (S21). Become. After the refill unit 28 performs refilling (S21), the flag setting unit 27 sets the valid flag to 1 (S24), and if the stack flag is 1, sets it to 0 (S3).

  By the above operation, the state becomes the same as that of FIG. 9B. Thereafter, similarly to FIG. 9B, the data reading unit 22 changes the lower 16 bits of the real address bus from all 16 bytes included in this line. The corresponding data is read (S4) and output to a 32-bit data bus. After that, the control unit 200 turns off the cache busy response signal. The details of the refill (S21) will be described in the description of the next cache miss.

  On the other hand, as a result of comparing the upper 20 bits of the real address bus with the read tag value (20 bits), if there is no match in any of the ways included in the selected set, the cache miss determination unit 24 Is not hit, that is, it is determined that a cache miss has occurred (S1). The operation (S300, S21 to S23, S2, S3) at this time is shown in the left column “random read” of “operation” in FIG.

  When it is determined that a cache miss has occurred, first, the line release unit 25 selects one of the four lines in the same set and releases the line (S300). For example, the LRU algorithm (Least Recently Used) is used for selecting the line to be released (S31). This is performed by the “LRU replacer” included in each set of FIG. That is, the line opening unit 25 selects a line using the LRU replacer. This algorithm, as the name implies, is a way to release the least recently used, that is, those that have been used less frequently. Since the content does not directly relate to the essential part of the present invention, the description is omitted. The algorithm is not necessarily limited to this algorithm, and the line to be opened may be determined by another algorithm.

  Next, the line selected in this way is released. The operation of releasing the line depends on the state of each line, that is, the state indicated by the value of each flag of the line at that time, and the contents are shown in the right column of FIG.

  The state in FIG. 10A means that the line is not allocated as a cache of the main storage device 131, that is, it is released. Therefore, the line opening unit 25 does not need to open this line again (No in S31). This state is usually indicated by the fact that the valid flag is 0.

  In the states of FIGS. 10B and 10C, as shown in FIGS. 7E and 7F, the content of the line matches the content of the main storage device 131 (Yes in S32, No in S33). ). For this reason, the line release unit 25 does not need to write back, but only needs to set the valid flag to 0 to indicate that the line has been released (S36). The line opening unit 25 can set various flags using, for example, the flag setting unit 27. If the stack flag is set to 1 as shown in FIG. 10 (c), indicating that the stack has been allocated to the stack (stack), the line release unit 25 sets the stack flag when releasing the line. Is also set to 0 (S36).

  In the states of FIGS. 10D and 10E, the dirty flag is 1 (Yes in S33), and the contents of the line are stored in the main storage device 131 as shown in FIGS. The content has been updated more recently. Therefore, the line release unit 25 needs to write back the contents of the line to the main storage device 131. The line opening unit 25 can execute, for example, a write-back by activating the write-back unit 29. This write-back is performed at high speed and automatically through the transfer data bus and the external data bus by using the transfer control unit 119 shown in FIG. However, this method is not directly related to the essence of the present invention, and the description is omitted. After performing the write-back, the line release unit 25 sets the valid flag and the dirty flag to 0 to temporarily indicate that the line has been released (S36).

  A state in which the valid flag is 1 (Yes in S32), the dirty flag is 1 (Yes in S33), and the stack flag is 1 shown in FIG. 10E corresponds to the state in FIG. This state means that this line has been allocated to the stack. Therefore, in this case, the line release unit 25 releases the allocation to the stack and sets the stack flag to 0 when releasing the line as described above (S36).

  The states in which the valid flag shown in FIGS. 10F and 10G are 0 correspond to the states in FIGS. 7A to 7F. In this state, the values of the tags coincide with each other, but since this line has not been used as a cache, that is, has been released, the line release unit 25 does not need to perform write-back. If the stack flag has been set to 1, the line release unit 25 only sets the stack flag to 0 when releasing the line (S36).

  Thus, the release of one line is completed. Next, in order to use the released line as a cache, the refill unit 28 refills the contents of the 16-byte main storage device 131 including the requested address into this line. I do. This refill is also performed at high speed and automatically through the transfer data bus and the external data bus using the transfer control unit 119 shown in FIG. 1, but the description is omitted because this method is not directly related to the essence of the present invention. I do.

  The tag updating unit 26 writes the upper 20 bits of the real address into the tag associated with the refilled line (S22). Subsequently, the flag setting unit 27 sets the valid flag to 1, the dirty flag to 0, and the stack flag to 0, that is, the state of FIG. 7E (S23).

  Since the state in which step S23 is completed is the same as the state in FIG. 9B, the control unit 200 thereafter performs the same operation as in FIG. 9B (S2 to S4). That is, the data reading unit 22 reads data of the small area corresponding to the lower 4 bits of the real address bus from all 16 bytes included in the line where the tag is updated, and outputs the data to the 32-bit data bus ( S3). After that, the control unit 200 turns off the cache busy response signal. The MPU 113 detects that the cache busy response signal has been turned off, and reads the contents of the data sent through the data bus (S10).

(2-2. Random Write)
FIG. 11 is a sequence diagram showing an operation of the cache system 100 when the MPU 113 executes a random write instruction. When the MPU 113 starts executing a random write instruction, the MPU 113 shown in FIG. 1 turns on a cache write request, outputs a logical address indicating a memory area to be written to a virtual address bus at the same time, and further writes data to be written with a 32-bit width. Output to data bus. Further, the MPU 113 keeps the SP relative modification and the push / pop modification off. By receiving these signals, the random write detection unit 5 of the cache unit 117 detects that the MPU 113 has made a data write request accompanying the execution of the random write instruction. Accordingly, control unit 200 turns on the cache busy response. The MPU 113 confirms that the cache busy response has been turned on, and turns off the cache write request.

  Subsequently, similarly to the random read, the cache miss determining unit 24 selects a set and a way, and determines a cache hit or a cache miss (S1). Since this has already been described, the description is omitted here.

  The operations (S2, S11, S12) when it is determined that the cache hits (Yes in S1) are shown in the right column “random write” of “operation” in FIGS. 9B to 9G. 9B to 9E show the operations (S11 and S12) when the cache hits (Yes in S1) and the valid flag of this line is 1 (Yes in S2). The state at this time corresponds to FIGS. 7 (e) to 7 (h). Since the content of the line at this time matches the content of the main storage device 131 or is newer than the content of the main storage device 131, the data writing unit 21 stores the area corresponding to the lower 4 bits of the real address bus of this line in The contents of the data bus, that is, the data sent through the data bus are written (S11). Subsequently, the flag setting unit 27 sets the dirty flag to 1 as shown in FIGS. 9B and 9C if the dirty flag is not yet set to 1 (S12). After that, the control unit 200 turns off the cache busy response signal.

  At this time, if the stack flag is 1, the operation state corresponds to the states shown in FIGS. In this case, as shown in FIGS. 9C and 9E, the flag setting unit 27 sets the stack flag to 0. The MPU 113 detects that the cache busy response signal has been turned off, and knows that the random write has ended.

  The operations (S21, S24) when the cache hits but the valid flag is 0 (No in S2) are shown in FIGS. 9 (f) and 9 (g). The state at this time corresponds to FIGS. 7A and 7B. This state corresponds to the fact that the value of the upper 20 bits of the address bus coincides with the content of the tag, but the line has already been released and has not been actually cached. That is, in this state, since the content of the main storage device 131 is newer than the content of the line, it is necessary to refill the content of the corresponding main storage device 131 into the cache memory (S21). After the refill unit 28 performs the refill (S21), the flag setting unit 27 sets the valid flag to 1 (S24). Next, the data writing unit 21 writes the contents of the data bus in the area corresponding to the lower 4 bits of the real address bus of this line (S11). Thereafter, the flag setting unit 27 sets the dirty flag to 1 (S12).

  If the operation state corresponds to the state of FIG. 7B and the stack flag is 1, the control unit 200 releases the allocation of the line to the stack as shown in FIG. 9G. That is, the flag setting unit 27 sets the stack flag to 0 (S12).

  On the other hand, the operation when a cache miss is determined in step S1 (No in S1) is shown in the right column “random write” of “operation” in FIG. The line release unit 25 determines the line to be released by the LRU replacer from the set selected by the middle 8 bits of the address bus in order to secure a new line to be used for the cache, and releases the determined line (S300). ), A refill is performed to newly use the released line as a cache (S21). Since this operation is the same as the line opening in the random read described above, the description is omitted here.

  By these operations, the contents of the data area of the line match the contents of the main storage device 131, and the operation state becomes the state of FIG. 9B, and the control unit 200 thereafter performs the same operation as that of FIG. Do. That is, the data writing unit 21 writes the contents of the data bus into a small area corresponding to the lower 4 bits of the real address bus of the refilled line. Subsequently, the control unit 200 turns off the cache busy response signal. The MPU 113 detects that the cache busy response signal has been turned off, and knows that the random write has ended.

(2-3. SP relative read)
FIG. 12 is a sequence diagram showing the operation of the cache system 100 when the MPU 113 executes the SP relative read instruction. When the MPU 113 starts executing the SP relative read instruction, the MPU 113 turns on the cache read request and simultaneously outputs a logical address indicating a memory area to be read to the virtual address bus. At the same time, the MPU 113 turns on the SP relative modification signal. Upon receiving these signals, the SP relative read detection unit 8 of the cache unit 117 detects that the MPU 113 has issued a data read request accompanying execution of the SP relative read instruction. In this point, the operation of the SP relative read is different from that of the random read. Accordingly, the control unit 200 of the cache unit 117 turns on the cache busy response. The MPU 113 confirms that the cache busy response has been turned on, and turns off the cache read request.

  The MMU 115 converts the upper 20 bits of the virtual address bus into the upper 20 bits of the physical address, and outputs it to the real address bus. The lower 12 bits of the virtual address bus are directly output to the real address bus.

  As described above, upon receiving the cache read request signal, control unit 200 first turns on the cache busy response signal. Next, in step S1, the cache miss determining unit 24 selects one set in each way using the middle 8 bits of the real address extracted by the address extracting unit 13 as a key, and determines the tag value of the selected set. read out. The cache miss determination unit 24 further determines a cache hit or miss. These operations are the same as the operations in the random read.

  If the cache hits (Yes in S1) and the valid flag of this line is 1 (Yes in S2), the data reading unit 22 reads data corresponding to the lower 4 bits of the real address bus from this line, and The data is output to a data bus having a bit width (S4). After that, the control unit 200 turns off the cache busy response signal. The above operation is shown in the left column “SP relative read” of “operation” in FIGS. The MPU 113 detects that the cache busy response signal has been turned off, and reads the contents of the data bus (S10).

  If the cache hits (Yes in S1), but the valid flag is 0 (No in S2), as described above, this means that the value of the upper 20 bits of the address bus coincides with the contents of the tag of a certain line. However, this means that the line has already been released and has not been cached. Therefore, in this case, after the refill unit 28 performs the refill (S21), the flag setting unit 27 sets the valid flag to 1 (S24). After that, the control unit 200 performs the same operation as that of FIG. The operation at this time is shown in the left column “SP relative read” in FIGS.

  On the other hand, as a result of comparing the upper 20 bits of the real address bus with the read tag value (20 bits), the cache miss determination unit 24 determines which way in the set selected by the value of the middle 8 bits of the address bus. If no match is found, it is determined that the cache did not hit (cache miss), and one of the four lines in the same set is selected to release the line (S301). In step S301, unlike step S300 (FIG. 8), the flag setting unit 27 sets only the valid flag to 0 (S37) without setting the stack flag to 0 (S36). Otherwise, the process of step S301 is the same as step S300.

  Thereafter, the refill unit 28 refills the contents of the released line from the corresponding memory area of the main storage device 131 (S21). Subsequently, the tag updating unit 26 updates the tag associated with the refilled line (S22). Thereafter, the flag setting unit 27 sets the valid flag to 1 (S24). After that, the control unit 200 performs the same operation as in FIG. The operation at this time is shown in the left column “SP relative read” in FIG.

  Since the stack flag is not set in any of the states shown in FIGS. 13A to 13G, the state of the stack flag is maintained in the original state. Also in this point, the operation of the SP relative read is different from that of the random read.

(2-4. SP relative write)
FIG. 14 is a sequence diagram showing an operation of the cache system 100 when the MPU 113 executes the SP relative write instruction. When the MPU 113 starts executing the SP relative write instruction, the MPU 113 turns on a cache write request, outputs a logical address indicating a memory area to be read to a virtual address bus, and further writes data to be written to a 32-bit data bus. Output. At the same time, the MPU 113 turns on the SP relative modification signal. By receiving these signals, the SP relative write detection unit 7 of the cache unit 117 detects that the MPU 113 has issued a data write request accompanying the execution of the SP relative write instruction. This point is different from the operation at the time of executing the random write. Accordingly, the control unit 200 of the cache unit 117 turns on the cache busy response. The MPU 113 confirms that the cache busy response has been turned on, and turns off the cache read request.

  Subsequently, the cache miss determination unit 24 determines the selection of a set and a way and a cache hit or a cache miss by the same operation as step S1 in the SP relative read (S1). The operation when it is determined that a cache hit has occurred (No in S1) is shown in the right column “SP relative write” of “operation” in FIGS.

  If the cache hits (Yes in S1) and the valid flag of this line is 1 (Yes in S2), the data writing unit 21 stores the contents of the data bus in an area corresponding to the lower 4 bits of the real address bus of this line. Write (S11). Thereafter, the flag setting unit 27 sets the dirty flag to 1 as shown in FIGS. 13B and 13C if the dirty flag is not yet set to 1 (S13). Thereafter, the control unit 200 turns off the cache busy response signal. The operation at this time is shown in the right column “SP relative write” of “operation” in FIGS. The MPU 113 detects that the cache busy response signal has been turned off, and knows that the SP relative write has been completed.

  If the cache hits (Yes in S1) but the valid flag is 0 (No in S2), this means that the value of the upper 20 bits of the address bus coincided with the contents of the tag of a certain line as described above. Means that the line has already been released and not cached. Therefore, in this case, after the refill unit 28 performs the refill (S21), the flag setting unit 27 sets the valid flag to 1 (S24). After that, the control unit 200 performs the same operation as that of FIG. The operation at this time is shown in the right column “SP relative write” in FIGS.

  On the other hand, as a result of comparing the upper 20 bits of the real address bus with the read tag value (20 bits), the cache miss determination unit 24 determines which way in the set selected by the value of the middle 8 bits of the address bus. If no match is found, it is determined that the cache did not hit (cache miss), and one of the four lines in the same set is selected to release the line (S301).

  Thereafter, the refill unit 28 refills the contents of the released line from the corresponding memory area of the main storage device 131 (S21). Subsequently, the tag updating unit 26 updates the tag associated with the refilled line (S22). Thereafter, the flag setting unit 27 sets the valid flag to 1 (S24). After that, the control unit 200 performs the same operation as in FIG. The operation at this time is shown in the right column “SP relative write” in FIG.

  Since the stack flag is not set in any of the states shown in FIGS. 13A to 13G, the state of the stack flag is maintained in the original state. Also in this regard, the operation of the SP relative write differs from that of the random write, and is the same as the SP relative read.

(2-5. Pop)
FIG. 15 is a sequence diagram showing the operation of the cache system 100 when the MPU 113 executes the pop instruction. When the MPU 113 executes the pop instruction, the MPU 113 turns on the cache read request, and simultaneously outputs a logical address indicating a memory area to be popped to the virtual address bus. At the same time, the MPU 113 turns on the push / pop modification signal. By receiving these signals, the pop access detection unit 12 of the cache unit 117 detects that the MPU 113 has issued a data read request accompanying execution of the pop instruction. In this point, the operation of the pop differs from the random read and the SP relative read. Accordingly, the control unit 200 of the cache unit 117 turns on the cache busy response. The MPU 113 confirms that the cache busy response has been turned on, and turns off the cache read request and the push / pop modifier signal.

  The MMU 115 converts the upper 20 bits of the virtual address bus into the upper 20 bits of the physical address, and outputs it to the real address bus. The lower 12 bits of the virtual address bus are directly output to the real address bus.

  As described above, upon receiving the cache read request signal, control unit 200 first turns on the cache busy response signal. Next, in step S1, the cache miss determining unit 24 selects one set in each way using the middle 8 bits of the real address extracted by the address extracting unit 13 as a key, and determines the tag value of the selected set. Read, determine cache hit or miss. These operations are the same as the operations in the random read and the SP relative read, and thus the description is omitted.

  The value of the upper 20 bits of the real address bus matches the content of the tag of a certain line in the selected set (Yes in S1; that is, the cache hits), and the valid flag of this line is 1 (Yes in S2). ), The control unit 200 performs the operations of FIGS. At this time, the third bit of the real address bus (the fourth bit from the lower digit, that is, a bit representing the 2nd power digit, and so forth) and the second bit If both (the third bit from the lower digit, that is, the bit representing the 2nd power digit, and so on) are 1 (Yes in S51), the control unit 200 proceeds to FIG. The operation of the left column “pop from the highest address” is performed. That is, the data reading unit 22 reads the data corresponding to the lower 4 bits of the real address bus from this line, and outputs the data to the 32-bit data bus (S4). Thereafter, the control unit 200 turns off the cache busy response signal.

  Next, the flag setting unit 27 sets the valid flag of this line to 0 (S52), and releases this line. This is because this stack is emptied by popping data from the highest address. The flag setting unit 27 sets the valid flag to 0 and releases the line, but at this time, the write-back unit 29 does not perform write-back. This is because the contents of this line are not referred to again, and there is no need to write back and save it in the main memory.

  16B and 16D, if the stack flag of this line is off, as shown in the operation left column “pop from the highest address” in FIGS. 16B and 16D, the flag setting unit 27 turns on the stack flag ( S52). This is for storing that this line was used as a stack.

  Also, as shown in the operation left column “pop from the highest address” in FIGS. 16D and 16E, when the dirty flag of this line is on, the flag setting unit 27 turns off the dirty flag ( S52). Because this line is released, the dirty flag has no meaning. In addition, the flag setting unit 27 may turn off only the dirty flag in step S52 without turning off the valid flag, that is, without opening the line. Accordingly, when it becomes necessary to open the corresponding line later in step S300 or S301, the write-back (S34) can be prohibited (No in S33).

  If at least one of the third bit and the second bit of the real address bus is 0 (No in S51), the control unit 200 operates in the right column of FIG. 16B to FIG. pop ". That is, the data reading unit 22 reads the data corresponding to the lower 4 bits of the real address bus from this line, and outputs the data to the 32-bit data bus (S4). Thereafter, the control unit 200 turns off the cache busy response signal. The MPU 113 detects that the cache busy response signal has been turned off, and reads data as the content of the 32-bit data bus (S10). At this time, the flag setting unit 27 does not operate the flag.

  If the value of the upper 20 bits of the real address bus matches the content of the tag of a certain line in the selected set (Yes in S1), but the valid flag of this line is 0 (No in S2), the control unit Reference numeral 200 performs the operations shown in FIGS. In this case, the content of the tag of a certain line in the selected set coincided with the value of the upper 20 bits of the real address bus. However, this line corresponds to the fact that this line has already been released, so the refill unit 28 Refill is performed (S21). If both the third bit and the second bit of the real address bus are 1 (Yes in S55) as determined by the boundary determination unit 23 (S55), the control unit 200 proceeds to the left column of the operation in FIGS. The operation of “pop from the highest address” is performed.

  That is, the refill unit 28 refills the information stored in the corresponding address from the main storage device with respect to this line, and the flag setting unit 27 sets the valid flag to 1 (S25). Then, the data reading unit 22 reads data corresponding to the lower 4 bits of the real address bus from this line, and outputs the data to the 32-bit data bus (S4). Thereafter, the control unit 200 turns off the cache busy response signal.

  At this time, if the stack flag is 0, the flag setting unit 27 sets the stack flag to 1 ("pop" from the highest address in the left column of the operation in FIG. 16F; S53). Further, the flag setting unit 27 returns the valid flag to 0 (FIG. 16 (f), (g) operation left column “pop from top address”; S53). This is because this line is released by pop from the highest address.

  If at least one of the third bit and the second bit of the real address bus is 0 (No in S55), the control unit 200 operates in the right column of FIG. The operation of is performed. That is, even in this case, the flag setting unit 27 refills the information stored in the corresponding address from the main storage device for this line (S21), and the flag setting unit 27 sets the valid flag to 1. (S25). Then, the data reading unit 22 reads data corresponding to the lower 4 bits of the real address bus from this line, and outputs the data to the 32-bit data bus (S4). Thereafter, the control unit 200 turns off the cache busy response signal. Thereafter, the flag setting unit 27 does not operate the flag. Although FIG. 15 illustrates an example in which the processes of steps S21 and S25 are performed before the determination of step S55, the processes of steps S21 and S25 are performed after step S55 regardless of the determination. You may go.

  If there is no match between the value of the upper 20 bits of the real address bus and the content of the tag of the line in the selected set (No in S1), the cache miss determining unit 24 determines that the cache has missed, and The control unit 200 performs the operation of FIG. That is, the line release unit 25 releases one line from the set by the LRU algorithm (S301), and the refill unit 28 refills the information stored in the corresponding address from the main storage device for the line. Execute. Thereafter, the tag updating unit 26 updates the tag associated with the refilled line. Subsequently, the flag setting unit 27 sets the valid flag corresponding to the line to 1 and the dirty flag to 0 (S25). Next, the data read unit 22 reads data corresponding to the lower 4 bits of the real address bus from this line, and outputs the data to the 32-bit data bus (S4). Then, the control unit 200 turns off the cache busy response signal (FIG. 16A).

  Further, if both the third and second bits of the real address bus are 1 (Yes in S56) as determined by the boundary determination unit 23 (S56), the flag setting unit 27 sets the stack flag to 1 (FIG. 16). (A) Operation left column "pop from top address"; S54). Further, at this time, the flag setting unit 27 returns the valid flag to 0 (the leftmost column of the operation in FIG. 16A, “pop from the highest address”; S54). This is because this line is released by pop from the highest address.

  As described above, when the MPU 113 executes the pop instruction and the small area from which data is to be read is at the line boundary (Yes in S51, S55, and S56), the control unit 200 holds the line. This line is released without writing back the data to the main memory 131 (that is, v = 0 is set in S52, S53, and S54). A line for holding data that is no longer read again by reading by the pop instruction is free of trouble even if it is released, and since the data held by this line is useless data, it is written to the main storage device 131. There is no need to back. As described above, since the control unit 200 releases the line holding the unnecessary data without writing back the data, the memory access speed is improved without hindering the operation of the MPU 113.

  In addition, when the small area to be read is not at the line boundary (No in S51, S55, and S56), the control unit 200 does not open the line. For this reason, the MPU 113 can terminate the data reading by the pop instruction not only at the address corresponding to the small area adjacent to the line boundary but also at the address corresponding to the small area not adjacent to the line boundary.

  Further, as described above, in step S52, the dirty flag can be set to 0 without setting the valid flag to 0. As a result, when the MPU 113 executes another instruction or the like, the control unit 200 writes back the data of the line to the main storage device 131 (S300, S301) when releasing the line due to a cache miss (S300, S301). Step S34) is skipped. As a result, the memory access speed is improved.

  As shown in FIG. 17, after or during the above operation, if the transfer busy response signal is off, the transfer data bus is vacant, and the control unit 200 determines in advance a memory that may soon be needed. Perform a refill. Thereby, the memory access speed can be further increased. Specifically, when the transfer busy determination unit 15 detects that the transfer busy response signal is off (Yes in S61), the control unit 200 indicates the value of the tag included in the line and the set including the line. One line corresponding to the offset address whose upper 28 bits of the real address is one or two addresses larger than the upper 28 bits of the real address of the current SP is found, and the operation right column in FIG. 18 “SP approaches from below. The operation shown in FIG. That is, the offset calculation unit 14 calculates the above-described offset address, and the cache miss determination unit 24 determines whether or not a cache miss has occurred for the line corresponding to the offset address (S65).

  If the cache miss determination unit 24 can find such a line (Yes in S65), and the valid flag of the line is 1 (Yes in S67), the control unit 200 does nothing (the operation right in FIG. 18). Columns (b)-(e)).

  Although the cache miss determination unit 24 was able to find such a line (Yes in S65), if the valid flag of the line is 0 (No in S67) and the line is assigned to the stack ( (Yes in S69), the refill unit 28 refills the line (S21). Thereafter, the flag setting unit 27 sets the valid flag to 1 (S70) (the above is the operation right column (g) in FIG. 18).

  Although the cache miss determination unit 24 was able to find such a line (Yes in S65), if the valid flag of the line is 0 (No in S67) and the line is not assigned to the stack ( (No in S69), the control unit 200 does nothing (the right column (f) in FIG. 18).

  If the cache miss determination unit 24 cannot find such a line (No in S65), the address order is immediately above the current stack pointer SP, and it is highly likely that the line is immediately read by pop. This means that the memory area of the main storage device is not cached. For this reason, the control unit 200 executes refilling on the cache for an area of the main storage device in which the upper 28 bits of the real address are larger than the upper 28 bits of the real address of the current SP and the lower 4 bits are 0. (Operation right column (a) in FIG. 18; S21).

  Specifically, the line release unit 25 determines a line to be released by the LRU in a set corresponding to an address that is one greater than the upper 28 bits of the real address of the current stack pointer SP, and releases the determined line. (S301). Thereafter, the tag updating unit 26 updates the tag (S22), and the flag setting unit 27 sets the stack flag to 1 (S26). Next, the refill unit 28 refills the memory area of the main storage device in which the upper 28 bits of the real address are larger than the upper 28 bits of the real address of the current SP and the lower 4 bits are 0 in the line. (S21). Next, the flag setting unit 27 sets the valid flag of the line to 1 (S70).

  At the same time, as shown in FIG. 19, when the transfer busy response is off (Yes in S61), the offset calculating unit 14 determines the value of the tag included in the line and the higher address of the real address indicated by the set including the line. Calculate another offset address where the 28 bits are smaller than the upper 28 bits of the real address of the current SP. The cache miss determining unit 24 searches for a line corresponding to the offset address (S71). If the cache miss determination unit 24 can find such a line (Yes in S71), the control unit 200 performs the operation shown in the operation left column “SP moves upward” in FIG.

  That is, if the cache miss determination unit 24 can find such a line (Yes in S71), and the valid flag, dirty flag, and stack flag of the line are all 1 (Yes in S73), The write-back unit 29 performs write-back of the line (S75), and the flag setting unit 27 sets the dirty flag to 0 (S77) (the above, the left column (e) in FIG. 10).

  Whether such a line could not be found by the cache miss determination unit 24 (No in S71), or if any of the valid flag, the dirty flag, and the stack flag was 0 (S73). No), the control unit 200 does not execute anything (the left columns (a) to (d), (f), and (g) in FIG. 10).

  As described above, the control unit 200 writes back the data of the line that has been read in accordance with the pop command, that is, the data that will not be read again (S75), so that the line is released later (S300, There is no need to perform write-back (S34) in S301). Thereby, the memory access speed is improved.

(2-6. Push)
FIG. 20 is a sequence diagram showing the operation of the cache system 100 when the MPU 113 executes the push instruction. When the MPU 113 executes the push instruction, the MPU 113 turns on the cache write request signal, simultaneously outputs a logical address indicating a memory area to be read to a virtual address bus, and further outputs word data to be written to a 32-bit data bus. . At the same time, the MPU 113 turns on the push / pop modification signal. By receiving these signals, the push access detection unit 11 of the cache unit 117 detects that the MPU 113 has issued a data write request accompanying execution of the push instruction. In this respect, push operates differently from the random write and the SP relative write. Accordingly, the control unit 200 of the cache unit 117 turns on the cache busy response. The MPU 113 confirms that the cache busy response has been turned on, and turns off the cache write request and the push / pop decoration signal.

  Subsequently, the cache miss determining unit 24 determines the selection of a set and a way and a cache hit or cache miss by the same operation as in step S1 in the pop (S1). Since these operations are the same as the corresponding operations in the random write and the SP relative write, the description will be omitted.

  The value of the upper 20 bits of the real address bus matches the content of the tag of a certain line in the selected set (Yes in S1; that is, the cache hits), and the valid flag of this line is 1 (Yes in S2). ), The control unit 200 performs the operation of “push to the highest address” or the operation of the right column “push other than the highest address” in the left column of FIGS. 21B to 21E in the corresponding line. At this time, if both the third bit and the second bit of the real address bus are 1 (Yes in S51) as a result of the determination (S51) by the boundary determination unit 23, the control unit 200 proceeds to FIG. The operation "push to the highest address" in the left column is performed. That is, the data writing unit 21 reads the word data to be written from the 32-bit data bus and writes the word data to an area corresponding to the lower 4 bits of the real address bus of this line (S11). Thereafter, the control unit 200 turns off the cache busy response signal (the above, “push to the highest address” in the left column of the operation in FIGS. 21B to 21E).

  Next, if the dirty flag of this line is 0, the flag setting unit 27 sets the dirty flag to 1 (FIG. 21 (b), (c) operation left column "push at top address"; S15). If the stack flag of this line is 0, the flag setting unit 27 sets the stack flag to 1 ("push at top address" in the left column of the operation in FIGS. 21B and 21D; S15). Thereafter, the MPU 113 detects that the cache busy response signal has been turned off, and knows that the processing by the push instruction has been completed.

  If at least one of the third bit and the second bit of the real address bus is 0 (No in S51), the control unit 200 proceeds to the operation right column “other than the highest address” in FIGS. 21B to 21E. push "operation. That is, the data writing unit 21 reads the word data to be written from the 32-bit data bus and writes the word data to an area corresponding to the lower 4 bits of the real address bus of this line (S11). Thereafter, the control unit 200 turns off the cache busy response signal (the above, “push other than the highest address” in the right columns of the operation in FIGS. 21B to 21E). Next, if the dirty flag of this line is 0, the flag setting unit 27 sets the dirty flag to 1 ("push other than the highest address" in the right column of the operation in FIGS. 21B and 21C; S13). The flag setting unit 27 does not perform other flag operations. The MPU 113 detects that the cache busy response signal has been turned off, and knows that the processing by the push instruction has been completed.

  If the value of the upper 20 bits of the real address bus matches the content of the tag of a certain line in the selected set (Yes in S1), but the valid flag of this line is 0 (No in S2), the control unit Reference numeral 200 performs the operations shown in FIGS. In this case, the content of the tag of a certain line in the selected set coincides with the value of the upper 20 bits of the real address bus, but this line has already been released.

  If both the third bit and the second bit of the real address bus are 1 (Yes in S55) as a result of the determination (S55) by the boundary determination unit 23, the operation "leftmost address" in the left column of FIGS. The operation of “push” is performed. That is, the refill unit 28 does not refill the information stored in the corresponding address from the main storage device for this line, and the flag setting unit 27 sets the valid flag to 1 (S24).

  Next, the data writing unit 21 reads the word data to be written from the 32-bit data bus, and writes the word data to an area corresponding to the lower 4 bits of the real address bus of this line (S11). Subsequently, the control unit 200 turns off the cache busy response signal (the above, “push to the highest address” in the left column of the operation in FIGS. 21F and 21G). The MPU 113 detects that the cache busy response signal has been turned off, and knows that the processing by the push instruction has been completed. The flag setting unit 27 sets the dirty flag to 1 (operation “push at top address” in the left column of FIGS. 21F and 21G; S15). At this time, if the stack flag is 0, the flag setting unit 27 sets the stack flag to 1 ("push to highest address" in the left column of the operation in FIG. 21F); S15.

  If it is determined in step S55 that at least one of the third bit and the second bit of the real address bus is 0 (No in S55), the control unit 200 performs the operation in the rightmost column of FIG. The operation of "push to other than the upper address" is performed. That is, the refill unit 28 refills the information stored at the corresponding address from the main storage device for this line (S21). Next, the flag setting unit 27 sets the valid flag to 1 (S24). Subsequently, the data writing unit 21 reads the word data to be written from the 32-bit data bus, and writes the word data to an area corresponding to the lower 4 bits of the real address bus of this line (S11). Thereafter, the control unit 200 turns off the cache busy response signal. Accordingly, the flag setting unit 27 sets the dirty flag to 1.

  If it is determined in step S1 that there is no match between the value of the upper 20 bits of the real address bus and the contents of the tag of the line in the selected set (No in S1), the cache miss determination unit 24 has missed the cache. Judge. Accordingly, the control unit 200 performs the operation of FIG. That is, the line release unit 25 releases one line from this set by the LRU algorithm (S301). If both the third bit and the second bit of the real address bus are 1 (Yes in S56) as determined by the boundary determination unit 23 (S56), the refill unit 28 corresponds to this line from the main storage device. Do not refill the information stored at the address. Subsequently, the tag updating unit 26 changes the tag associated with the released line (S22). Next, the flag setting unit 27 sets the valid flag to 1, the dirty flag to 0, and the stack flag to 0 (S27). As a result, the state becomes the same as that of FIG. 21B, and the control unit 200 thereafter executes the operation of FIG. 21B.

  If it is determined in step S56 that at least one of the third bit and the second bit of the real address bus is 0 (No in S56), the refill unit 28 sends the corresponding address from the main storage device to this line. The stored information is refilled (S21). After that, the control unit 200 executes the processing of step S22 and subsequent steps, similarly to the case where the determination of step S56 is Yes.

  As described above, when the MPU 113 executes the push instruction and the small area in which the data is to be written is on the line boundary (Yes in S56), the control unit 200 performs the processing after the line release (S301) due to the cache miss. And unnecessary refilling (S21) is not performed. Therefore, the memory access speed is improved. Further, when a cache miss occurs when the small area to which data is to be written is not on the line boundary (No in S56), the control unit 200 performs refill (S21). For this reason, the MPU 113 can start the continuous writing of the data accompanying the push instruction not only from the address corresponding to the small area adjacent to the line boundary but also from the address corresponding to the small area not adjacent to the line boundary.

  In addition to the case where the line is released (S301) and the case where the valid flag is 0 indicating that the line is released (No in S2), the control unit 200 responds to the position of the small area where the data is to be written. (S55), whether or not to perform refilling (S21) is selected. Thus, even if the line is already open, unnecessary refills are avoided, thereby further improving the memory access speed.

  As shown in FIG. 22, after or during the above operation, if the transfer busy response signal is off, since the transfer data bus is free, the control unit 200 determines that the memory which is unlikely to be needed for the time being is required. Execute write back in advance. Specifically, when the transfer busy determination unit 15 detects that the transfer busy response signal is off (Yes in S61), the control unit 200 determines the value of the tag included in the line, which is a unit of address conversion of the MMU 115. Is the line corresponding to the offset address, which is an address larger than the upper 20 bits of the real address of the current SP, or the upper 28 bits of the real address indicated by the tag value included in the line and the set including the line However, one line corresponding to an address (also called an offset address) larger than the upper 28 bits of the real address of the current SP by one or more is found in the left column "SP moved away" in the operation left column in FIG. Perform the operation shown. That is, the offset calculation unit 14 calculates the above-described offset address, and the cache miss determination unit 24 determines whether a cache miss has occurred for the line corresponding to the offset address (S81).

  Even when the cache miss determination unit 24 can find such a line (Yes in S81), at least one of the valid flag, the dirty flag, and the stack flag of the line is 0 (No in S73). Then, the control unit 200 does nothing (the left columns (b) to (d), (f), and (g) in FIG. 18). If the cache miss determination unit 24 can find such a line (Yes in S81) and all of the valid flag, dirty flag, and stack flag of the line are 1 (Yes in S73), the write-back unit 29 Then, the line is written back (S75). Subsequently, the flag setting unit 27 sets the dirty flag to 0 (S77) (the left column (e) in FIG. 18). As a result, when this line is subsequently released by the LRU algorithm, it is not necessary to perform write-back again, and the processing can be speeded up.

  If the cache miss determination unit 24 cannot find such a line (No in S81), the control unit 200 does nothing (the left column (a) in FIG. 18).

(3. Operation example 1)
An operation example of the data memory cache system according to the embodiment of the present invention will be described in detail with reference to FIGS. 23 to 29, assuming that a general-purpose CPU that executes a program described in C language is used as MPU 113. I do.

  A program written in the C language uses, for example, a stack structure that grows from an upper address to a lower address. The program uses a dedicated stack pointer (SP) existing in the general-purpose CPU, uses a general-purpose register existing in the general-purpose CPU as a frame pointer (FP), and executes access to this stack structure. An example of the stack structure at this time is shown in FIG. In this example, only a stack structure related to execution of one function is shown. Actually, a stack structure corresponding to the number of function calls (calls) already executed has a structure stacked below.

  Next, how this structure is generated (changed) by a new function call in the C language will be described. When a C-language function is called, first, the side that calls the function uses the push instruction at the top of the stack to generate arguments required for processing on the function side. This is to pass this argument to the function. FIG. 24 shows a stack structure immediately after the generation of the argument.

  Next, a function call is executed. At this time, a push instruction is executed, and the return address from the function is saved on the stack. FIG. 25 shows the stack structure immediately after executing this function call.

  Next, the execution of the program shifts to the called function side. The called function first executes a push instruction, and saves registers used in the function including the frame pointer to the stack. FIG. 26 shows the stack structure immediately after the register is saved.

  Next, the called function sets the value of the stack pointer to the frame pointer, and subtracts the size of the stack frame from the stack pointer to generate a stack frame. As a result, the stack pointer moves to a lower address, and a stack frame is generated between the stack pointer and the frame pointer. FIG. 27 shows a stack structure immediately after a stack frame is generated.

  Next, the called function executes a frame pointer relative read / write instruction, a stack pointer relative read / write instruction, a random read / write instruction, etc. to access an argument or access a stack frame. Access necessary information and execute function processing. It may also perform other function calls if necessary.

  Upon termination of the processing of the function, the called function adds the size of the stack frame to the stack pointer in order to discard the used stack frame. Then, the pop instruction is executed to restore the saved register. The stack structure at this time is restored to the same state as the stack structure immediately after the function call, and is shown in FIG.

  Next, a pop instruction is executed, an address for returning to the function on the calling side is taken out, and the program execution is returned from the called function to the called function by the return instruction. The stack structure at this time is completely the same as the stack structure immediately after the argument to be passed to the function is generated, and is shown in FIG. On the returning calling function side, the size of the argument sequence is added to the stack pointer in order to discard the argument sequence. For example, in the example of FIG. 24, the value is a value corresponding to two times the word size.

  By the above processing, the stack structure returns to the structure before starting the function call processing. The stack structure at this time is as shown in FIG.

  FIG. 28 shows the state of the cache line immediately after the generation of the stack frame in a series of processes related to the above function call. As shown in FIG. 28, a portion other than the stack frame is used as a stack, and therefore, the stack flag of the line is set to 1. Since the unit of the cache line is 16 bytes and the unit of the stack structure is 4 bytes, the boundary between the stack frame and the register save stack does not always coincide with the boundary of the cache line.

  According to the present invention, the stack flag is set to 1 in a line where the register save stack and the stack frame coexist. The stack flag is set to 0 in a line where the stack frame and the argument string coexist. If an access is made to an argument sequence or a stack frame during execution of a function process, the access is normally performed by a random read / write instruction, so that the stack flag set to 1 also changes to 0. come. Accordingly, the stack flag also changes to 0 for the line where the register save stack and the stack frame coexist, and the line where the argument sequence and the return address coexist. FIG. 29 shows the state of the flag of each line at this time.

(4. Operation example 2)
FIGS. 30 to 34 show another operation example of the data memory cache system according to the embodiment of the present invention in a case where a general-purpose CPU that executes a program described in the Java (registered trademark) language is used as MPU 113. This will be described in detail using.

  The program described in the C language is executed by, for example, an interpreter described in the C language. This interpreter has a Java (registered trademark) program counter necessary for implementing a Java (registered trademark) virtual machine in addition to a program counter for executing a program described in C language. The stack structure also has a Java (registered trademark) stack structure necessary for mounting a Java (registered trademark) virtual machine, in addition to a stack structure for executing a program described in C language.

  As the Java (registered trademark) stack structure, for example, a stack structure that grows from an upper address toward a lower address can be used. In the Java (registered trademark) stack structure, for example, a general-purpose register existing in a general-purpose CPU is used as a stack pointer (SP), and access is performed to the Java (registered trademark) stack structure.

  FIG. 30 shows an example of the Java (registered trademark) stack structure. FIG. 30 shows a Java (registered trademark) stack structure corresponding to processing of one method (corresponding to a function in the C language). Actually, the number of stack structures corresponding to the method calls (calls) that have occurred so far is a structure that is stacked below.

  Next, how this stack structure is generated (changed) by a new method call in the Java (registered trademark) language will be described. First, a method caller that calls a new method sets an argument to be used for processing in the method by executing a push instruction at the top of the stack. FIG. 31 shows a Java (registered trademark) stack structure immediately after the argument string generation. This argument string is used to pass a value required for processing on the called method side to the called method side from the method calling side.

  Next, the method call is executed. The return Java (registered trademark) address from the method is saved in the C language stack. The saving of this address is not directly related to the Java (registered trademark) stack structure, and therefore the description is omitted. By this method call, control of the Java (registered trademark) program shifts to the called method side. On the called Java (registered trademark) method side, if it is necessary to save registers to be used, the values of these registers are saved on the C language stack. The saving of this register is not directly related to the Java (registered trademark) stack structure, and therefore, the description is omitted.

  Next, in the called method, in order to generate an area for a local variable required in the processing executed by itself, the method corresponding to the size of the area of the local variable is obtained from the value of the Java (registered trademark) stack pointer. Subtract the value. FIG. 32 shows a Java (registered trademark) stack structure immediately after the generation of the local variable area.

  In the called method, an argument or a local variable is accessed by an SP relative read / write instruction, which is a Java (registered trademark) stack pointer relative address designation, and the method is executed.

  Since the Java (registered trademark) language is a stack-oriented language, the operand in the Java (registered trademark) instruction is always specified as a relative to the Java (registered trademark) stack pointer. For example, in an addition (add) instruction, the operand is not explicitly specified, but is automatically set to the top and second of the Java (registered trademark) stack. Therefore, to execute the add instruction, the Java interpreter reads the two values from the operand stack in the Java stack by executing the pop instruction twice, and executes the addition. Is stored at the top of the operand stack in the Java (registered trademark) stack by executing a push instruction. FIG. 33 shows a Java (registered trademark) stack structure in which this processing is being executed.

  The called method may call another method as needed. When the processing in the called method ends, the operand stack in the Java (registered trademark) stack becomes empty. Then, in order to discard the local variable area and the argument sequence, a value corresponding to the total size thereof is added to the Java (registered trademark) stack pointer. At this time, the Java (registered trademark) stack structure returns to the Java (registered trademark) stack structure before starting the Java (registered trademark) method calling process. The Java (registered trademark) stack structure at this time is shown in FIG.

  FIG. 34 shows the state of the cache line during execution of the above-described Java (registered trademark) method invocation processing. As shown in FIG. 34, the stack flag of the line generated for this method calling process is set to 1. Further, as the Java (registered trademark) stack pointer moves away from the stack bottom, write-back is executed during a time when the transfer busy response signal is off at a line distant from the stack pointer, and the dirty flag of the line is set to 0. FIG. 34 also shows the state in which it is closed.

  INDUSTRIAL APPLICABILITY The data memory cache device and the data memory cache system of the present invention improve the memory access speed, and are industrially useful.

FIG. 1 is a block diagram illustrating a configuration of a data memory cache system according to an embodiment of the present invention. FIG. 4 is an explanatory diagram showing each instruction format and operation of push, pop, load, and store instructions. FIG. 4 is an explanatory diagram illustrating a relationship between an instruction executed by an MPU and a state of each control line. FIG. 2 is a block diagram showing a configuration of the cache unit of FIG. 1 corresponding to the data memory cache device according to the embodiment of the present invention. FIG. 5 is a block diagram illustrating a configuration of a data holding unit of the cache unit in FIG. 4. FIG. 6 is an explanatory diagram illustrating a line configuration of a data holding unit in FIG. 5. It is a figure which shows the possible combination of a valid flag, a dirty flag, and a stack flag, and the state of the line which it means. FIG. 2 is an operation sequence diagram of the cache system of FIG. 1 when an MPU executes a random read instruction. FIG. 9 is an explanatory diagram showing the contents of an operation corresponding to the state of each line when a random read / random write instruction is executed. It is explanatory drawing which shows the content of the operation | movement corresponding to the state of each line at the time of opening | release of a line and SP moving upward. FIG. 2 is an operation sequence diagram of the cache system of FIG. 1 when an MPU executes a random write instruction. FIG. 2 is an operation sequence diagram of the cache system of FIG. 1 when an MPU executes an SP relative read instruction. FIG. 9 is an explanatory diagram showing the contents of an operation corresponding to the state of each line when executing an SP relative read / SP relative write instruction. FIG. 2 is an operation sequence diagram of the cache system in FIG. 1 when an MPU executes an SP relative write instruction. FIG. 2 is an operation sequence diagram of the cache system of FIG. 1 when an MPU executes a pop instruction. FIG. 9 is an explanatory diagram showing the contents of an operation corresponding to the state of each line when a pop instruction is executed. FIG. 16 is an operation sequence diagram illustrating another process that proceeds in parallel with the process of FIG. 15 when the MPU is executing the pop instruction. It is a figure which shows the content of the operation | movement corresponding to the state of each line at the time of execution that SP moved away from the bottom and SP approached from the bottom. FIG. 16 is an operation sequence diagram illustrating still another process that proceeds in parallel with the process of FIG. 15 when the MPU is executing the pop instruction. FIG. 2 is an operation sequence diagram of the cache system of FIG. 1 when an MPU executes a push instruction. FIG. 14 is a diagram illustrating the contents of an operation corresponding to the state of each line when a push instruction is executed. FIG. 22 is an operation sequence diagram illustrating another process that proceeds in parallel with the process of FIG. 21 when the MPU is executing the push instruction. FIG. 3 is a diagram illustrating a stack structure of a C language. FIG. 9 is a diagram illustrating a stack structure immediately after an argument is generated. FIG. 3 is a diagram illustrating a stack structure immediately after a function call. FIG. 7 is a diagram illustrating a stack structure immediately after register saving. FIG. 3 is a diagram illustrating a stack structure immediately after a stack frame is generated. FIG. 11 is a diagram illustrating a state of a cache line immediately after a stack frame is generated. FIG. 7 is a diagram illustrating a state of a cache line after random access. It is a figure showing a Java (registered trademark) stack structure. FIG. 4 is a diagram illustrating a Java (registered trademark) stack structure immediately after an argument is generated. FIG. 3 is a diagram illustrating a Java (registered trademark) stack structure immediately after a local variable area is generated. FIG. 4 is a diagram showing a Java (registered trademark) stack structure during function processing. It is a figure showing the state of the cache line under function processing. FIG. 11 is a diagram showing a state in which, when a cache miss occurs in a push in a conventional stack cache system, one unit of content is read from a main storage device to a cache memory. FIG. 11 is a diagram showing a state in which a unit of contents is written back from a cache memory to a main storage device when a cache miss occurs in a pop in a conventional stack cache system. FIG. 13 is a diagram illustrating a state in which data stored in a low-address memory area is very unlikely to be read due to pop for a while; FIG. 11 is a diagram illustrating a state in which an address area having a value lower than the address indicated by the stack pointer is very likely to be immediately read out by popping.

Explanation of reference numerals

5 Random Write Detector 6 Random Read Detector 7 SP Relative Write Detector 8 SP Relative Read Detector 11 Push Access Detector 12 Pop Access Detector 21 Data Writer 22 Data Reader 23 Boundary Judge 24 Cache Miss Judge 25 Line release unit (data area release unit) 26 Tag update unit 27 Flag detection unit 28 Refill unit 29 Write back unit 100 Data memory cache system 113 Operation unit (MPU) 115 Memory management unit (MMU)
117 Stack-compatible data cache unit (data memory cache device)
119 transfer control unit 131 main storage device 200 control unit 300 data holding unit 910, 920, 930, 940 stack memory 913, 923, 933, 943 stack pointer

Claims (29)

A data memory cache device for use by being interposed between an arithmetic unit and a main storage device accessed by the arithmetic unit,
It has a plurality of data areas for holding data, and the data held by each of the plurality of data areas is read and written to the main storage device at a time, and each of the plurality of data areas is a plurality of small areas. And a data holding unit that data held by each of the plurality of small areas is read and written to the arithmetic unit at a time,
A cache miss occurs in the target data area, which is a data area corresponding to an address output from the arithmetic unit, when the arithmetic unit requests continuous writing of data to continuous addresses in the main storage device. Then, after releasing the target data area, the target small area in the target data area, which is a small area corresponding to the address output by the arithmetic unit, is positioned in the early direction of the continuous writing with respect to the address order. In the case where the target data area is adjacent to a data area boundary, data output from the arithmetic unit without reading data from the main storage device to the target data area is transferred to the target small area. When writing, if the target small area is not adjacent to the data area boundary, the Data memory cache device and a control unit for writing the data to be output the arithmetic unit after performing the loading of data into the target data area to the target small area. The control unit includes:
A push access detection unit that detects the request for the continuous writing from the arithmetic unit;
When the push access detection unit detects the request for continuous writing, a cache miss determination unit that determines whether there is a cache miss for the target data area;
When the push access detection unit detects the request for continuous writing, a boundary determination unit that determines whether the target small area is adjacent to the data area boundary,
A data area release unit that releases the target data area when the cache miss determination unit determines the occurrence of the cache miss;
When the data area release unit releases the target data area, when the determination of the boundary determination unit is negative, data is read from the main storage device to the target data area released by the data area release unit. A refill unit that does not read data from the main storage device to the target data area released by the data area release unit when the determination by the boundary determination unit is positive;
2. The data memory cache device according to claim 1, further comprising: a data writing unit that writes data output by the arithmetic unit to the target small area when the push access detection unit detects the request for continuous writing. The data holding unit includes:
The apparatus further includes a plurality of appropriate flag holding units that hold a plurality of appropriate flags respectively indicating release or unopening of the plurality of data areas,
The refill unit is configured to return the main storage device to the target data area even when the appropriate flag corresponding to the target data area is set to a side indicating open, when the determination of the boundary determination unit is negative. 3. The data memory cache device according to claim 2, wherein data is read from the main storage device to the target data area when the boundary determination unit determines that the data is read. The data holding unit includes:
Further comprising a plurality of stack flag holding unit holding a plurality of stack flags indicating whether the plurality of data areas are used for either continuous writing or continuous reading,
The control unit includes:
If the determination by the boundary determination unit is affirmative, after the data writing unit finishes writing the data, a stack flag corresponding to the target data area is set to a positive side, and the boundary determination unit determines 4. The stack flag setting unit according to claim 2, further comprising a stack flag setting unit that does not change a stack flag corresponding to the target data area after the data writing unit finishes writing the data when the determination is negative. Data memory cache device. The plurality of data areas are associated with a middle portion of an address of the main storage device, and each of the plurality of small regions is associated with a lower portion of an address of the main storage device, One or more data areas correspond to the same value in the middle part of the device address,
The data holding unit includes:
The apparatus further includes a plurality of tag holding units that hold a plurality of tags each indicating an upper part of an address of data held by the plurality of data areas,
The control unit includes:
An address extraction unit that extracts the upper part, the middle part, and the lower part from an address output by the arithmetic unit,
The cache miss determination unit includes a value indicated by a tag associated with each of the one or more data areas corresponding to the middle portion extracted by the address extraction unit, and the upper portion extracted by the address extraction unit. Are compared, it is determined that the cache miss has occurred if none match,
The boundary determination unit is configured such that a small region corresponding to the lower part extracted by the address extraction unit among the plurality of small regions is located in an address order in an earlier direction of the continuous writing of the data region to which the small region belongs. Determining whether or not the target small area is adjacent to the data area boundary,
The data area release unit is configured to, when the push access detection unit detects the request for continuous writing, and when the cache miss determination unit determines the occurrence of the cache miss, extract the medium extracted by the address extraction unit. Releasing the target data area by releasing any of the one or more data areas corresponding to the portion;
The control unit includes:
A tag update unit that updates a tag associated with the data area released by the data area release unit to the upper part extracted by the address extraction unit,
The data writing unit is configured to extract the address extraction unit in a data area corresponding to the middle part extracted by the address extraction unit and associated with a tag holding the upper part extracted by the address extraction unit. 5. The data memory cache device according to claim 2, wherein the small area corresponding to the lower part is set as the target small area, and data output by the arithmetic unit is written to the target small area. A data memory cache device for use by being interposed between an arithmetic unit and a main storage device accessed by the arithmetic unit,
A data holding unit that is associated with an address of the main storage device and includes a plurality of data areas for holding data of the corresponding address;
When performing continuous reading, which is reading of data from the continuous addresses of the main storage device to the arithmetic unit, the data area in the data holding unit where the continuous reading is completed is terminated. A data memory cache device comprising: a control unit that releases data held in the data area without writing back to the main storage device. Data held by each of the plurality of data areas is read and written to the main storage device at a time, and each of the plurality of data areas is divided into a plurality of small areas, and each of the plurality of small areas is The retained data is read and written to the operation unit at a time,
The control unit is a data area corresponding to an address output by the arithmetic unit when a request for continuous reading, which is reading of data from consecutive addresses in the main storage device, is issued from the arithmetic unit. Data is read from the target small area, which is a small area corresponding to the address output by the arithmetic unit in the data area, to the arithmetic unit, and the target small area is slow in the continuous reading with respect to the address order. In the case where it is adjacent to a data area boundary that is a boundary of the target data area located in the direction, the target data area is released without performing data write-back from the target data area to the main storage device, 7. The target data area is not released when the target small area is not adjacent to the data area boundary. Placing data memory cache device. The data holding unit includes:
The apparatus further includes a plurality of appropriate flag holding units that hold a plurality of appropriate flags respectively indicating release or unopening of the plurality of data areas,
8. The data memory cache device according to claim 7, wherein the control unit releases the target data area by setting a proper flag associated with the target data area to a side indicating release. The control unit includes:
A pop access detection unit that detects the request for continuous reading from the arithmetic unit;
A boundary determination unit that determines whether the target small area is adjacent to the data area boundary when the pop access detection unit detects the request for continuous reading;
A data reading unit that reads data of the target small area to the arithmetic unit when the pop access detection unit detects the request for continuous reading;
When the determination by the boundary determination unit is affirmative, after the data is read by the data read unit, the data is associated with the target data area without writing back the data from the target data area to the main storage device. Setting the appropriate flag set to the open side, and when the target small area is not adjacent to the data area boundary, an appropriate flag setting unit that does not change the appropriate flag associated with the target data area 9. The data memory cache device according to claim 8, comprising: A data memory cache device for use by being interposed between an arithmetic unit and a main storage device accessed by the arithmetic unit,
It has a plurality of data areas for holding data, and the data held by each of the plurality of data areas is read and written to the main storage device at a time, and each of the plurality of data areas is a plurality of small areas. And a data holding unit that data held by each of the plurality of small areas is read and written to the arithmetic unit at a time,
When there is a continuous read request for reading data from consecutive addresses in the main storage device from the arithmetic unit, the target unit in the target data area, which is a data area corresponding to the address output by the arithmetic unit, Data is read from the target small area, which is a small area corresponding to the address output by the arithmetic unit, to the arithmetic unit, and the target small area is located in the slower direction of the continuous reading with respect to the address order. In the case of being adjacent to the data area boundary which is the boundary of the target data area, when the target data area is subsequently released, a setting is made to prohibit write-back of data from the target data area to the main storage device, When the target small area is not adjacent to the data area boundary, the control unit does not perform the setting. Data memory cache device to obtain. The data holding unit includes:
The apparatus further includes a plurality of dirty flag holding units that hold a plurality of dirty flags indicating match and mismatch between data held by the plurality of data areas and data held at an address corresponding to the main storage device, respectively.
11. The data memory cache device according to claim 10, wherein the control unit performs the setting by setting a dirty flag corresponding to the target data area to a side indicating the match. The control unit includes:
A pop access detection unit that detects the request for continuous reading from the arithmetic unit;
A boundary determination unit that determines whether the target small area is adjacent to the data area boundary when the pop access detection unit detects the request for continuous reading;
A data reading unit that reads data of the target small area to the arithmetic unit when the pop access detection unit detects the request for continuous reading;
When the determination by the boundary determination unit is affirmative, after the data is read by the data reading unit, the dirty flag corresponding to the target data region is set to the side indicating the match, and the data region boundary determination unit 12. The data memory cache device according to claim 11, further comprising: a dirty flag setting unit that does not change the dirty flag corresponding to the target data area when the determination of the above is negative. The data holding unit includes:
Further comprising a plurality of stack flag holding unit holding a plurality of stack flags indicating whether the plurality of data areas are used for either continuous writing or continuous reading,
The control unit includes:
If the determination by the boundary determination unit is positive, after the data reading unit finishes reading the data, the stack flag corresponding to the target data area is set to the positive side, and the boundary determination unit determines 13. The stack flag setting unit according to claim 9, further comprising a stack flag setting unit that does not change a stack flag corresponding to the target data area after the data reading unit finishes reading the data when the determination is negative. Data memory cache device. The plurality of data areas are associated with a middle portion of an address of the main storage device, and each of the plurality of small regions is associated with a lower portion of an address of the main storage device, One or more data areas correspond to the same value in the middle part of the device address,
The data holding unit includes:
The apparatus further includes a plurality of tag holding units that hold a plurality of tags each indicating an upper part of an address of data held by the plurality of data areas,
The control unit includes:
An address extraction unit that extracts the upper part, the middle part, and the lower part from an address output by the arithmetic unit,
The boundary determination unit may determine that, among the plurality of small regions, the small region corresponding to the lower part extracted by the address extraction unit is located in the slowest direction of the continuous reading of the data region to which the small region belongs with respect to the address order. Determining whether or not the target small area is adjacent to the data area boundary,
The data reading unit is extracted by the address extracting unit in a data area corresponding to the middle part extracted by the address extracting unit and associated with a tag indicating the upper part extracted by the address extracting unit. 14. The data memory cache device according to claim 9, 12 or 13, wherein a small area corresponding to the lower part is set as the target small area and data of the target small area is read out to the arithmetic unit. A data memory cache device for use by being interposed between an arithmetic unit and a main storage device accessed by the arithmetic unit,
A data holding unit that is associated with an address of the main storage device and includes a plurality of data areas for holding data of the corresponding address;
A period during which continuous writing is performed from the arithmetic unit to continuous addresses in the main storage device, and data is transferred between the data holding unit and the main storage device. During a period in which the data bus is not used, writing back data from the data area in the data holding unit, which is located in the direction of the continuous writing earlier than the continuous writing currently performed with respect to the address order, to the main storage device. A data memory cache device comprising: The control unit includes:
A push access detection unit that detects the request for the continuous writing from the arithmetic unit;
When the push access detection unit detects the request for continuous writing, an offset calculation unit that calculates an offset address that is an address shifted from the address output by the arithmetic unit at a predetermined interval in an earlier direction of the continuous writing,
A cache miss determining unit that determines whether there is a cache miss for the offset address,
A transfer busy determination unit that determines whether the data bus is in use;
When the cache miss determination unit determines that there is no cache miss and the transfer busy determination unit determines that the data bus is not used, the data transfer from the data area corresponding to the offset address to the main storage device is performed. The data memory cache device according to claim 15, further comprising: a write-back unit that performs write-back. The plurality of data areas are associated with a middle part of the address of the main storage device, and one or more data areas correspond to the same value of the middle part,
Each of the plurality of data areas is divided into a plurality of small areas associated with the lower part of the address,
Data held by each of the plurality of data areas is read and written to the main storage device at a time, and data held by each of the plurality of small areas is read and written to the arithmetic unit at a time,
The data holding unit includes:
The apparatus further includes a plurality of tag holding units that hold a plurality of tags each indicating an upper part of an address of data held by the plurality of data areas,
The control unit includes:
An address extraction unit that extracts the upper part, the middle part, and the lower part from an address output by the arithmetic unit,
The offset calculation unit, when the push access detection unit detects the request for continuous writing, determines whether the continuous writing is fast from the address represented by the middle part and the high order part extracted by the address extraction unit. An address shifted with a predetermined interval in the direction is calculated as the offset address,
The cache miss determination unit compares a value indicated by a tag associated with each of the one or more data areas corresponding to the middle part of the offset address with the upper part of the offset address, and 17. The data memory cache device according to claim 16, wherein it is determined that a cache miss has occurred when they do not match. A data memory cache device for use by being interposed between an arithmetic unit and a main storage device accessed by the arithmetic unit,
A data holding unit that is associated with an address of the main storage device and includes a plurality of data areas for holding data of the corresponding address;
Data for transferring data between the data holding unit and the main storage device during a period in which a continuous read operation of reading data from a continuous address of the main storage device to the arithmetic unit is performed. Control for writing back data from the data area in the data holding unit, which is located in the direction of continuous reading earlier than the current continuous reading with respect to the address order, to the main storage device during the period when the bus is unused. And a data memory cache device. The control unit includes:
A pop access detection unit that detects the request for continuous reading from the arithmetic unit;
When the pop access detection unit detects the request for continuous reading, an offset calculation unit that calculates an offset address that is an address that is shifted from the address output by the arithmetic unit at a predetermined interval in an earlier direction of the continuous reading,
A cache miss determining unit that determines whether there is a cache miss for the offset address,
A transfer busy determination unit that determines whether the data bus is in use;
When the cache miss determination unit determines that there is no cache miss and the transfer busy determination unit determines that the data bus is not used, the data transfer from the data area corresponding to the offset address to the main storage device is performed. 19. The data memory cache device according to claim 18, further comprising: a write-back unit that performs write-back. The plurality of data areas are associated with a middle part of the address of the main storage device, and one or more data areas correspond to the same value of the middle part,
Each of the plurality of data areas is divided into a plurality of small areas associated with the lower part of the address,
Data held by each of the plurality of data areas is read and written to the main storage device at a time, and data held by each of the plurality of small areas is read and written to the arithmetic unit at a time,
The data holding unit includes:
The apparatus further includes a plurality of tag holding units that hold a plurality of tags each indicating an upper part of an address of data held by the plurality of data areas,
The control unit includes:
An address extraction unit that extracts the upper part, the middle part, and the lower part from an address output by the arithmetic unit,
The offset calculation unit is configured to, when the pop access detection unit detects the request for continuous reading, start the continuous reading from the address represented by the middle part and the high order part extracted by the address extraction unit. An address shifted with a predetermined interval in the direction is calculated as the offset address,
The cache miss determination unit compares a value indicated by a tag associated with each of the one or more data areas corresponding to the middle part of the offset address with the upper part of the offset address, and 20. The data memory cache device according to claim 19, wherein when it does not match, it is determined that a cache miss has occurred. The data holding unit includes:
Further comprising a plurality of stack flag holding unit holding a plurality of stack flags indicating whether the plurality of data areas are used for either continuous writing or continuous reading,
The write-back unit further corresponds to the data area corresponding to the offset address when the cache miss determination unit determines that there is no cache miss, and when the transfer busy determination unit determines that the data bus is not used. 21. The data memory according to claim 16, wherein write-back of data from the data area corresponding to the offset address to the main storage device is performed only when the stack flag is set to the positive side. Cache device. The data holding unit includes:
The apparatus further includes a plurality of appropriate flag holding units that hold a plurality of appropriate flags respectively indicating release or unopening of the plurality of data areas,
The write-back unit further corresponds to the data area corresponding to the offset address when the cache miss determination unit determines that there is no cache miss, and when the transfer busy determination unit determines that the data bus is not used. 21. The write-back of data from the data area corresponding to the offset address to the main storage device is performed only when the appropriate flag is set to the side indicating the unreleased state. 22. The data memory cache device according to item 21. A data memory cache device for use by being interposed between an arithmetic unit and a main storage device accessed by the arithmetic unit,
A data holding unit that is associated with an address of the main storage device and includes a plurality of data areas for holding data of the corresponding address;
Data for transferring data between the data holding unit and the main storage device during a period in which a continuous read operation of reading data from a continuous address of the main storage device to the arithmetic unit is performed. A control unit that reads data from the main storage device to a data area in the data holding unit that is located in a direction in which the continuous reading is performed later than the current continuous reading in the address order during a period in which the bus is not used. A data memory cache device comprising: The control unit includes:
A pop access detection unit that detects the request for continuous reading from the arithmetic unit;
When the pop access detection unit detects the request for continuous reading, an offset calculation unit that calculates an offset address that is an address shifted from the address output by the arithmetic unit at a predetermined interval in the slow direction of the continuous reading,
A transfer busy determination unit that determines whether the data bus is in use;
24. The data memory cache according to claim 23, further comprising: a refill unit that reads data from the main storage device into a data area corresponding to the offset address when the transfer busy determination unit determines that the data bus is not used. apparatus. The data holding unit includes:
Further comprising a plurality of stack flag holding unit holding a plurality of stack flags indicating whether the plurality of data areas are used for either continuous writing or continuous reading,
The refill unit, when the transfer busy determination unit determines that the data bus is not used, only when the stack flag corresponding to the data area corresponding to the offset address is set to a positive value, 25. The data memory cache device according to claim 24, wherein data is read from said main storage device to a data area corresponding to an offset address. The data holding unit includes:
The apparatus further includes a plurality of appropriate flag holding units that hold a plurality of appropriate flags respectively indicating release or unopening of the plurality of data areas,
The refill unit is configured such that, when the transfer busy determination unit determines that the data bus is not used, the appropriate flag corresponding to the data area corresponding to the offset address is set to a side indicating release. 26. The data memory cache device according to claim 24, wherein data is read from the main storage device to a data area corresponding to the offset address. The plurality of data areas are associated with a middle part of the address of the main storage device, and one or more data areas correspond to the same value of the middle part,
Each of the plurality of data areas is divided into a plurality of small areas associated with the lower part of the address,
Data held by each of the plurality of data areas is read and written to the main storage device at a time, and data held by each of the plurality of small areas is read and written to the arithmetic unit at a time,
The data holding unit includes:
The apparatus further includes a plurality of tag holding units that hold a plurality of tags each indicating an upper part of an address of data held by the plurality of data areas,
The control unit includes:
An address extraction unit that extracts the upper part, the middle part, and the lower part from an address output by the arithmetic unit,
The offset calculation unit, when the pop access detection unit detects the request for the continuous reading, performs the continuous reading from the address represented by the middle part and the high part extracted by the address extraction unit. 27. The data memory cache device according to claim 24, wherein an address shifted by a predetermined interval in a direction is calculated as the offset address. The control unit includes:
A value indicated by a tag associated with each of the one or more data areas corresponding to the middle part of the offset address is compared with the upper part of the offset address. A cache miss determining unit that determines that a cache miss has occurred for the address;
A data area release unit that releases any one of the one or more data areas corresponding to the middle part of the offset address when the cache miss detection unit determines the occurrence of the cache miss;
28. The data memory cache device according to claim 27, further comprising: a tag updating unit that updates a tag associated with the data area released by the data area releasing unit to the upper part of the offset address. A data memory cache device according to any one of claims 1 to 28,
An arithmetic unit connected to the data memory cache device;
A main memory connected to the data memory cache and accessed by the arithmetic unit;

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