JP2015060376A - Cache memory control program, processor including cache memory, and cache memory control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve cache memory utilization efficiency.SOLUTION: Provided is a processor-readable cache memory control program for causing a processor to execute a cache memory control process, the cache memory control process including: a stack memory cache area group allocating step of allocating a stack memory cache area group including a plurality of cache areas to a stack memory area for a sub-routine invoked in a program; and a cache area allocating step of maintaining the plurality of cache areas in the stack memory cache area group in a first dedicated cache area allocated to an active first sub-routine, second dedicated cache areas allocated to a second number of second sub-routines invoked just before the first sub-routine, and a third number of free cache areas.

Description

  The present invention relates to a cache memory control program, a processor incorporating a cache memory, and a cache memory control method.

  In recent server systems, the performance of processors has been improved. However, the memory access speed by the CPU is slow, which is a bottleneck for improving performance. The processor has a cache memory in addition to the CPU. When a memory access by the CPU occurs, the cache memory is checked first, and if a cache hit occurs, the cache memory is accessed. When a cache miss occurs, the main memory is accessed. Access to the cache memory is 100 to 300 times faster than access to the main memory. Therefore, in order to improve the memory access performance by the CPU, it is important that the cache is hit as much as possible and the main memory is not accessed.

  On the other hand, subroutines such as functions and modules are called hierarchically in the program. This local variable in the function or module becomes necessary when the function or module is called (call), and becomes unnecessary when the function or module is terminated and returned (return). Therefore, when a function or module is called, a stack memory area for the function or module is secured, and the local variable is recorded in the stack memory area. When the function or module ends, the stack memory area is released.

  A stack memory area for each program is formed in the main memory. When the CPU reads / writes local variables, it accesses the stack memory area in the main memory. The cache memory in the CPU is also used for this memory access. That is, when a memory access to a local variable in the stack memory area is performed, a cache hit determination of the cache memory is performed. If a cache hit occurs, data in the cache memory is accessed, and if a cache miss occurs, the stack memory area in the main memory is accessed. Is accessed.

  Regarding the control of the cache memory for the data in the stack memory area, there are the following patent documents.

JP 2001-273137 A JP 2004-38345 A

  The stack memory area and the cache memory as described above have the following problems. Since local variables are data that is used particularly frequently when executing a called function or module, it is desirable to ensure a cache hit.

  However, the local variable of the function or module that has already been called is temporarily stored in the cache memory. However, if the called function or module is executed for a long time, the local function of the function or module being executed Memory access to, will expel local variables of previously called functions and modules stored in the cache memory. Therefore, when the function or module being executed is terminated and execution of the previously called function or module is resumed, cache misses may increase due to memory access to the local variable.

  Also, when accessing a local variable immediately after a function or module is called, a cache miss occurs because the local variable is not yet stored in the cache memory, and other data in the cache memory is saved to the main memory. Otherwise, local variables of the called function or module cannot be written into the cache memory, and a certain amount of overhead is required.

  Furthermore, when multiple functions or modules are called continuously in a short period of time, these local variables are stored in the cache memory one after another, so that other data is evicted from the cache memory and cached for other data. Miss hits increase.

  The above problem is caused by the fact that a plurality of functions and modules share a cache memory, so that local variables in a plurality of stack memory areas influence each other in the shared cache memory.

  Therefore, in one aspect, an object of the present invention is to provide a cache memory control program for improving a cache hit rate for a local variable in a stack memory area, a processor having a cache memory, and a cache memory control method.

A first aspect of the embodiment is a processor-readable cache memory control program for causing a processor to execute a cache memory control process,
The cache memory control process includes:
A stack memory cache area group allocating step for allocating a stack memory cache area group having a plurality of cache areas to a stack memory area for a subroutine called in the program;
A plurality of cache areas in the stack memory cache area group are divided into a first dedicated cache area allocated to the first subroutine being executed, and a second number called immediately before the first subroutine. A cache area allocating step for maintaining the second dedicated cache area allocated to the second subroutine and the third number of free cache areas.

  According to the first aspect, the utilization efficiency of the cache memory is increased.

It is a block diagram of the server in this Embodiment. It is a block diagram of the hardware and software of the server in this Embodiment. It is a flowchart figure which shows the outline of the dynamic allocation of the cache area | region in this Embodiment. It is a figure which shows the process in which the compiler 21 compiles the source code of an application program into a machine language. It is an example of the characteristic of the cache size versus the cache hit rate obtained by the above characteristic investigation. It is a figure which shows about the allocation about the structure of a cache area | region, and a private area acquisition request. It is a figure which shows an example of a conversion table. It is a flowchart figure of a 1st example about determination process S16 with respect to the exclusive area acquisition request shown in FIG. It is a figure explaining the case where a dedicated cache area is allocated to a dedicated area acquisition request. It is a flowchart figure of a 2nd example about determination process S16 with respect to the exclusive area acquisition request shown in FIG. It is a figure explaining the process which replaces a dedicated cache area between a dedicated area acquisition request and an allocated dedicated area acquisition request. It is a figure which shows an estimated cache hit rate. FIG. 10 is a diagram showing an allocated dedicated area list LIST-FREE and an unallocated dedicated area list LIST-DEMAND. It is a flowchart figure of the 1st example of regular allocation review process S18. It is a figure for demonstrating the 1st example of regular allocation review process S18. It is a flowchart figure of the 2nd example of regular allocation review process S18. It is a figure for demonstrating the 2nd example of regular allocation review process S18. It is a flowchart figure of the 3rd example of periodical allocation review process S18. It is a figure for demonstrating the 3rd example of regular allocation review process S18. It is a figure which shows the process in the server system of process S2 and S3 of FIG. It is a flowchart figure corresponding to the process in the server system of FIG. It is a figure which shows the process in the server system of process S13, S16, S19 of FIG. It is a flowchart figure corresponding to the process in the server system of FIG. It is a flowchart figure of this exclusive area acquisition request determination process S16 (2). It is a figure which shows the replacement process of the sector ID conversion table when the process 22 of an application program switches. It is a figure which shows the relationship between the cache memory and stack memory area in 2nd Embodiment. It is a figure which shows the local variable of a function, and the variable data in a stack memory area. It is a figure which shows the function and stack memory area in a program. It is a figure explaining the problem of the cache memory with respect to a stack memory area. It is a figure explaining the problem of the cache memory with respect to a stack memory area. In the second embodiment, the time T1 during which the function E is being executed, the stack memory area ST at the time T2 when the function E is finished and recalled, and the stack memory cache area group 130-ST in the cache memory 130 FIG. In the second embodiment, the time T1 during which the function E is being executed, the stack memory area ST at the time T3 when the function E is finished and recalled, and the stack memory cache area group 130-ST in the cache memory 130 are FIG. It is a figure explaining the number N of N 2nd exclusive cache areas allocated to N functions called immediately before the function under execution. It is a figure explaining the number M of the M dedicated free cache areas allocated to the M functions scheduled to be called continuously immediately after the function being executed. It is a figure which shows control of the sector ID conversion table by the cache memory control program in 2nd Embodiment. It is a flowchart figure which shows a compilation process and an object process starting process. It is a flowchart figure of a function call back process. It is a flowchart figure of a function call process.

  The following is a table of contents of the present embodiment.

[First Embodiment]
[Outline of dynamic allocation of cache area of this embodiment]
[Allocate dedicated cache area in dedicated area acquisition request S15, S16]
[Memory access S13 using a dedicated cache area]
[Release dedicated cache area with dedicated area release request]
[Details of cache area dynamic allocation processing according to this embodiment]
[Index for determining the allocation of a cache area]
[Real cache hits]
[Locality of memory access]
[Effective usage of cache, effective usage of actual cache, cache disruption]
[Dedicated area acquisition request determination processing S16 (1)]
[Dedicated area acquisition request determination processing S16 (2)]
[Regular allocation review process S18]
[Regular allocation review process S18 (1)]
[Regular allocation review process S18 (2)]
[Regular allocation review process S18 (3)]
[Replacement process of sector ID conversion table at process switching]
[Second Embodiment]
Hereinafter, the present embodiment will be described according to the above table of contents.

[First Embodiment]
FIG. 1 is a configuration diagram of a server in the present embodiment. The server includes a processor unit 10, a main memory 16, an input / output unit 17 such as a keyboard and a display device, and a large-capacity storage 18 such as a hard disk. The processor unit 10 includes a CPU 12 that executes machine language instructions, a cache unit 13 that includes a cache memory and a cache memory control unit, and a bus interface 14 that controls access from the CPU to the main memory 16.

  The storage 18 stores an operation system (OS), middleware (M-Ware) such as a comparator, and an application program (APL). These programs are loaded into the main memory 16 when the server is started and executed by the CPU 12. The main memory 16 stores data necessary for execution of processes included in the application program APL. Further, the access speed to the main memory 16 is extremely slow compared to the access speed to the cache memory by the CPU 12. On the other hand, the capacity of the cache memory is very small compared to the capacity of the main memory 16.

  FIG. 2 is a block diagram of the hardware and software of the server in this embodiment. The hardware 1 has the configuration shown in FIG. 1, and FIG. 2 particularly shows a main memory 16, a cache system 13, and a CPU 12.

  The cache system 13 includes a cache memory 130 composed of a high-speed semiconductor memory such as SRAM, a sector ID conversion table 131 that is referred to when accessing the cache memory 130, and a size of a dedicated cache area that is set. It has a sector information setting unit 132, a cache address conversion unit 133 used when accessing the cache memory, and the like.

  In the present embodiment, the CPU 12 executes a machine language instruction to which a local sector ID is added in addition to a normal machine language instruction. As will be described later, the local sector ID is used to identify an area of the cache memory used by the machine language instruction.

  When dynamically allocating cache memory areas (cache sectors) to various processes of an application program, the OS 20 associates cache sector IDs to be assigned to local sector IDs in the sector ID conversion table 131. The sector ID conversion table 131 is referred to when accessing the cache memory, and converts the local sector ID added to the machine language instruction into a cache sector ID indicating the used area in the cache memory. In this way, OS20 dynamically allocates a dedicated cache area for the various processes and processes in the program, and uses the dedicated cache area allocated for the processes and processes in the process. Can do.

  The cache sector information setting unit 132 in the cache system 13 sets how much cache size is allocated to a cache memory area (cache sector). As will be described later, when allocating a dedicated cache area, the OS 20 sets the cache size in the cache sector information setting unit 132. The cache address conversion unit 133 converts the memory access address by the CPU 12 into an address of the cache memory.

  2 includes an operation system (OS) 20, middleware 21 such as a compiler for converting an application program into a machine language, and an application program group 22 having a plurality of application programs.

  A function control management unit 201 in the OS manages a function called in each process of the application program. In general, the function control management unit 201 manages data used in a function as stack data when the function is called, and releases the stack data when the function is read back.

  The OS 20 executes processing of each process while switching multitasks (or multiprocesses). The process management unit 202 performs switching control of each process. In the present embodiment, in particular, the process management unit 202 switches the sector ID conversion table 131 in the cache system 13 every time the process is switched. Thereby, it is possible to dynamically allocate an appropriate cache area corresponding to each process. Details will be described later.

  The interrupt processing process 203 is an OS interrupt processing program that is executed when an IO interrupt or an exceptional interrupt from an internal program occurs. This interrupt processing process includes a dedicated area acquisition request and a dedicated area release request. Details will be described later.

  In this embodiment, the OS 12 allocates, for example, a shared cache area, a dedicated cache area, and a disturbance processing cache area in the cache memory in response to a dedicated area acquisition request issued in the process of the application program. Execute dynamically. This dynamic allocation is performed based on the memory access characteristics of the processing corresponding to the dedicated area acquisition request (hereinafter, “corresponding processing”), the cache memory access status at the time of the dedicated area acquisition request, and the like. The cache allocation management unit 204 controls the dynamic allocation of these cache areas.

  The above-mentioned shared cache area (or shared area) is an area of cache memory that is shared and used by multiple processes and corresponding processes. When a certain process or corresponding process uses the shared cache area, other processes In some cases, the data stored in the shared cache area may be evicted by corresponding processing.

  On the other hand, a dedicated cache area (or dedicated area) is an area of cache memory that is allocated to a dedicated area acquisition request, and memory access in the processing subject to the dedicated area acquisition request is the dedicated cache area allocated to it. Use space. Therefore, data in the dedicated cache area is not evicted by memory access of other processes or corresponding processing, and data in the shared cache area or other dedicated cache area is not evicted by accessing the dedicated cache area. .

  The disturbance processing cache area is a cache memory area allocated to a dedicated area acquisition request for a corresponding process having a very high cache miss hit rate of the corresponding process, and is a kind of dedicated cache area. In the disturbance processing cache area, the cache control is performed separately from the shared cache area and other dedicated cache areas. Therefore, the cache miss ratio of the corresponding process to which the disturbance cache area is assigned avoids the data in the shared cache area and other dedicated cache areas being evicted and the subsequent cache miss ratio increases. . The disturbance processing cache area may be allocated to a plurality of dedicated area acquisition requests. By providing the disturbance processing cache area, it is possible to prevent the data in the shared cache area and the dedicated cache area from being evicted due to the high cache miss hit rate due to the disturbance processing, and it is possible to suppress the cache hit rate from being extremely lowered.

  Examples of processing steps executed by the cache allocation management unit 204 include the following. First, in the development environment, investigate the memory access characteristics such as the memory access frequency and the cache hit rate when a dedicated cache area is allocated for each process and the target process targeted by the dedicated area acquisition request. A characteristic investigation step to be performed; second, a step of replacing the sector ID conversion table 131 in the cache system 13 at the time of process switching; and third, a cache between the shared cache area, the dedicated cache area, and the disturbance processing cache area. An area replacement determination process, and fourth, an update process of the sector ID conversion table based on the cache area replacement determination result, an update process of the size setting of the allocated cache area of the cache sector information setting unit 132, and the like.

  The compiler of the middleware 21 converts the application program described in the source code into an executable machine language (object code). In addition to general compilation processing, this compiler uses a machine language instruction for a dedicated area acquisition request that requests allocation of a dedicated cache area that is issued appropriately in each process, and a dedicated area release that releases the allocated dedicated area. Add the requested machine language instruction. In addition, the compiler adds a unique local sector ID within the process to each dedicated area acquisition request issued. Then, the compiler adds the local sector ID to the machine language instruction that uses the acquired dedicated cache area. Thereby, in response to a dedicated area acquisition request, a dedicated cache area is dynamically allocated to the cache area used in the target process, and the entire cache memory area can be used effectively. That is, it is possible to increase the cache effective utilization level and the actual cache effective utilization level described later.

  The application program (APL) 22 is compiled into a machine language that is an execution format of the application program. Thereby, the CPU 12 executes the machine language of this application program.

[Outline of dynamic allocation of cache area of this embodiment]
FIG. 3 is a flowchart showing an outline of dynamic allocation of cache areas in the present embodiment. First, the system is operated in a development environment in which the application program APL is installed on the server (S1). First, the compiler is executed by the processor (CPU) to compile the application program APL (S2). A portion related to the dynamic allocation of the cache area in the compiling step S2 will be described below.

  FIG. 4 is a diagram illustrating a process in which the compiler 21 compiles the source code of the application program into a machine language. The compiler converts the source code APL_SC of the application program into a machine language (object code) APL_OC that is the execution format. A general compiler function is to convert an object code into a machine language instruction having an instruction part and an operand.

  In the present embodiment, the compiler further issues a dedicated area acquisition request 30 for requesting allocation of the cache memory to the dedicated cache area and a corresponding dedicated area release request 34 in a plurality of processes in the application program. Insert as appropriate. As shown in FIG. 4, the dedicated area acquisition request 30 is a machine language instruction having, for example, a process ID, a local sector ID, and the priority of the target process of the dedicated area acquisition request 30. In each process, the dedicated area acquisition request 30 is issued to request the OS 20 to allocate a dedicated cache area at a portion where processing is to be performed while occupying the cache area.

  The process ID is identification information of the operation process PR1 managed by the OS20. The local sector ID is local identification information in the process PR1 for identifying the target process 32 of the dedicated area acquisition request 30, and is identification information for identifying the allocated dedicated cache area.

  The priority is a value indicating the priority of the handling process 32, and is represented by, for example, 8 levels of 0-7. However, since it is necessary to prioritize the processing in the OS, the user program is restricted such that priority is assigned only to 0-5, for example.

  On the other hand, the dedicated area release request 34 has the same process ID and local sector ID as the dedicated area acquisition request 30 paired therewith. As a result, the dedicated cache area allocated by the OS 20 is released, and a shared cache area is allocated instead for the corresponding processing.

  Further, the compiler assigns a local sector ID for identifying the dedicated cache area used by the instruction to the instruction between the dedicated area acquisition request 30 and the dedicated area release request 34 and generates an instruction with a local sector ID. . Therefore, the instruction in the target process 32 targeted by the dedicated area acquisition request executes memory access using the allocated dedicated cache area based on the local sector ID. However, not all instructions between the dedicated area acquisition request 30 and the dedicated area release request 34 need to use the dedicated cache area. For such an instruction, by designating the local sector ID to, for example, “0”, memory access can be executed using a shared cache area as in the case of a normal instruction instead of a dedicated cache area.

  A plurality of dedicated area acquisition requests 30 may be issued in the process PR1. A dedicated area release request 34 corresponding to the dedicated area acquisition request 30 is issued at a position appropriate for releasing the dedicated area.

  Returning to FIG. 3, the characteristics of the dedicated area acquisition request are checked in the development environment (S3). In this embodiment, a part of the area in the cache memory is dynamically allocated to a specific process or a part of the process in the process as a dedicated cache area. The purpose of dynamic allocation is to improve the total number of cache hits per unit time of the cache memory by appropriately allocating a dedicated cache area, and to suppress the number of cache misses as much as possible. For this reason, information for determining whether or not a dedicated cache area should be allocated in response to a dedicated area acquisition request is required.

There are various types of processing targeted by the dedicated area acquisition request of each process. For example:
"The entire process is the target process of the dedicated area acquisition request and requests the dedicated cache area to be used by the entire process"
"The target processing of the dedicated area acquisition request is a part of the process in the process"
“The target processing of the dedicated area acquisition request accesses a wide area of the memory, expels the data in the cache area and disturbs it”
"The processing that is the target of the dedicated area acquisition request stores the data in the cache area in a fixed manner, and there is almost no cache miss"
"Target processing can be completed in a very short time"
“The target process has a significantly different cache hit rate when the dedicated cache area is used than when the shared cache area is used.”
By examining these in advance, it is possible to appropriately determine whether or not a dedicated cache area should be allocated to a dedicated area acquisition request during actual operation.

  Therefore, in step S3, we investigate the characteristics of how much the cache hit rate improves when the allocation of the dedicated cache area is permitted for the dedicated area acquisition request in the machine language application program compiled under the development environment. To do. Specifically, a dedicated cache area is allocated only to the dedicated area acquisition request subject to characteristic investigation, and the size of the dedicated cache area is gradually increased from 0 to (1) memory per short time in each case. The number of accesses (memory access frequency) and (2) the cache hit rate in the dedicated cache area are acquired.

  FIG. 5 is a characteristic example of the cache size versus the cache hit rate obtained by the above characteristic investigation. The cache hit rate H (x) at each cache size when the cache size x on the horizontal axis is increased from 0 corresponds to the vertical axis. In general, this cache size vs. cache hit rate characteristic shows that an increase in cache size does not contribute significantly to an increase in the cache hit rate in a small cache size range, but an increase in cache size causes a cache hit in a certain cache size range. The rate increases rapidly, and the cache hit rate does not increase much for a size larger than a certain cache size.

  Therefore, the cache size x1 at the point where the straight line (dashed line) extending from the origin in FIG. 5 is in contact with the cache hit rate characteristic H (x) is the reference point where the increase in the cache size contributes most to the improvement of the cache hit rate. .

  At the stage of examining the cache hit rate in FIG. 5, the number of memory accesses per unit time (memory access frequency), the number of cache hits, and the number of cache misses are acquired at the same time.

  FIG. 20 is a diagram showing processing in the server system in steps S2 and S3 of FIG. FIG. 21 is a flowchart corresponding to the processing in the server system of FIG. With reference to these drawings, the processes in steps S2 and S3 in FIG. 3 will be described.

  First, the source code of the application program is input from the input unit of the server system (S201). Then, the compiler 21 compiles the source code of the application program and converts it into object code (machine language) (S202). This conversion into machine language instructions is as described in FIG.

  Next, system operation is started from the input part of the server system in the development environment (S301). In response to this, the process management unit 202 in the OS 20 performs process startup processing and performs system operation processing (S302).

  While the process is running in this development environment, the cache allocation management unit 204 in the OS 20 grants the request to each dedicated area acquisition request included in the application program whose characteristics are to be investigated, and allocates the dedicated Instructions are executed while using the cache area, and the memory access frequency and cache hit rate are measured. In this case, the cache allocation management unit 204 measures the memory access frequency and the cache hit rate at each size while changing the size of the dedicated cache area from 0 to the maximum value (S303). Thereby, the characteristic graph shown in FIG. 5 is generated.

  At the start of the characteristic investigation, the cache allocation management unit 204 reads the sector ID conversion table 131 of the process corresponding to the special area acquisition request for the characteristic investigation target, and stores the cache sector of the dedicated cache area to be assigned to the local sector ID to be investigated The ID is associated and the size set in the dedicated cache area is assigned (S304). In addition, a local sector ID corresponding to a dedicated area acquisition request other than the check target is associated with a cache sector ID = 0 indicating a shared cache area. As a result, a dedicated cache area having a size designated only for the local sector ID of the process to be investigated is generated in the cache memory 130 (S305).

  The process management unit 202 starts the investigation target process when preparation for starting the characteristic investigation is completed (S306), and the investigation target process in the application program 22 is executed (S307). During the execution of the process to be investigated, memory access is executed using the allocated dedicated cache area.

  Steps S303 to S307 are repeatedly executed until the investigation of the characteristics of all dedicated area acquisition requests of all processes is completed. When all the processing is completed, the cache allocation management unit 204 records the memory access frequency and the cache hit rate of the investigation target process, and terminates the characteristic investigation (S308).

  Returning to FIG. 3, when the system is operated in the production environment (S10), the following processing is executed. The OS 12 checks the cache hit rate of the dedicated cache area acquired by the shared cache area and the dedicated area acquisition request in the background (S11). In this investigation, the memory access frequency in the shared cache area and the dedicated cache area is also acquired. Specifically, investigation is performed using a counter for an access function to each area, a counter for the number of cache hits, and the like.

  The OS 20 calculates the appropriate ratio between the shared cache area and the dedicated cache area, the actual cache effective usage for each dedicated area acquisition request, and the like based on the above investigation results. As will be described later in detail, the appropriate ratio of the shared / dedicated area is calculated by the ratio of the number of memory accesses to both areas. In addition, the effective usage rate of the real cache is obtained by multiplying the difference between the cache hit rate when the dedicated cache area is used and when using the shared cache area by the memory access frequency, and then by multiplying the priority. Is required. This will be described in detail later.

  Then, the CPU 12 executes the instruction with the local sector ID described in FIG. 4 (S13). The execution of this instruction will be described in detail later.

  Furthermore, the OS 20 performs dynamic allocation processing for the cache area (S14). In the dynamic allocation processing of the area in the cache memory, first, when a dedicated area acquisition request is issued (S15), the cache allocation management unit 204 in the OS 20 should allocate a dedicated cache area for the dedicated area acquisition request. Whether or not it is a dedicated cache area, a shared cache area, or a disturbance processing cache area is assigned (S16).

  Second, at a regular allocation review timing (S17), the cache allocation management unit 204 in the OS 20 executes a periodic allocation review process (S18). The periodic allocation review process includes (1) a process for determining whether or not to replace the allocated dedicated cache area of the allocated dedicated area acquisition request and the unallocated dedicated cache area requested by the unallocated dedicated area acquisition request; 2) Judgment whether or not a part of the shared cache area should be allocated as a dedicated cache area in response to an unallocated dedicated area acquisition request. (3) Conversely, the allocated dedicated cache area is released and changed to a shared cache area. A process for determining whether or not to perform the process is included. In the regular allocation review process S18, the cache allocation management unit 204 replaces the dedicated cache area and allocates or releases the dedicated cache area according to the determination result.

  Third, when a dedicated area release request is issued (S19), the cache allocation management unit 204 performs a release request process for releasing the requested dedicated cache area to become a part of the shared cache area (S20). ).

  The above steps S11-S20 are repeated until the system operation ends.

  FIG. 6 is a diagram showing the configuration of the cache area and the allocation for the dedicated area acquisition request. The cache memory 130 has a shared cache area 130_1 and a dedicated cache area 130_2 that is a dynamic allocation area. The dedicated cache area 130_2 includes a plurality of dedicated cache areas assigned to the dedicated area acquisition request and a disturbance processing cache area. That is, the disturbance processing cache area is a kind of dedicated cache area.

  The cache memory 130 is divided into a shared cache area and a dedicated cache area, and sector IDs are assigned in order from 0 to each area. The shared cache area has sector ID = 0. The shared cache area is a cache area that is shared by a plurality of processes and target processes within the processes. On the other hand, the dedicated cache area is a cache area having a size permitted by the determination and occupied and used by the target process of the allocated dedicated area acquisition request. Furthermore, in the disturbance cache area, which is a form of the dedicated cache area, the memory access of the target process of the dedicated area acquisition request is performed for a wide range of addresses. Assigned when data is expelled and disturbed. Therefore, a disturbance processing cache area may be allocated for a plurality of dedicated area acquisition requests.

  As described above, the dedicated area acquisition request is issued for each process in the application program APL or for each target process in the process, and a dedicated cache area is assigned to the dedicated area acquisition request according to the determination result. Therefore, the dedicated cache area is not always allocated, and the shared cache area may be allocated and the allocation of the dedicated cache area may be waited as an unallocated dedicated area acquisition request. This is because the cache memory 130 has upper limits on the size and the number of divisions.

  In the example shown in FIG. 6, the shared cache area 130_1 is allocated to the dedicated area acquisition request 0 of the process 1 and the dedicated area acquisition requests 0 and 3 of the process 2 as a result of the determination. In addition, sector IDs = 1, 2, and 3, which are dedicated cache areas, are assigned to the process 2 dedicated area acquisition requests 1, 2, and 4, respectively. As a result of determination, sector ID = 4, which is a disturbance processing cache area, is assigned to process 3 dedicated area acquisition request 0.

  FIG. 22 is a diagram showing processing in the server system in steps S13, S16, and S19 of FIG. FIG. 23 is a flowchart corresponding to the processing in the server system of FIG. With reference to these drawings, allocation of a dedicated cache area by a dedicated area acquisition request, memory access using the dedicated cache area, and release of a dedicated cache area by a dedicated area release request will be described.

[Allocate dedicated cache area in dedicated area acquisition request S15, S16]
First, a dedicated area acquisition request is issued within the process of the application program 22 (S400). A local sector ID is given to this dedicated area acquisition request. In response to this, the cache allocation management unit 204 in the OS 20 determines whether or not the allocation of the dedicated cache area is permitted (S401). This determination process will be described later. When the allocation is permitted, the cache allocation management unit 204 sets the cache size of the dedicated cache area to be allocated in the cache sector information setting unit 132 and stores the local sector ID in the sector ID conversion table 131 in the cache system 13. The sector ID of the allocated area is set in the column of the cache sector ID corresponding to (S402).

  FIG. 7 is a diagram illustrating an example of the conversion table. In FIG. 7, in response to a dedicated area acquisition request 30 with process ID = 2 and local sector ID = 2, cache sector ID = 2 with respect to local sector ID = 2 in the conversion table 131 with process ID = 2. The sector ID of the dedicated cache area is entered.

[Memory access S13 using a dedicated cache area]
When the process of the application program 22 is executed, an instruction (machine language instruction) with a local sector ID for identifying a dedicated cache area to be used is issued (S403). Then, the CPU 12 interprets and executes the instruction with the local sector ID (S403-1). In this execution, the CPU 12 refers to the sector ID conversion table 131 and acquires a cache sector ID corresponding to the local sector ID (S403-2). That is, it is as shown as S403-2 in FIG.

  Then, the cache address conversion unit 133 converts the memory access address into an address in the cache memory, and performs cache access to the dedicated area acquisition request cache area of the cache sector ID = 2 in the cache memory 130 (S403-3). Here, when a cache miss hit occurs, the main memory 16 is accessed via the bus interface 14 (S403-4). In the case of a cache hit, data in the dedicated cache area is read or data is written to the dedicated cache area.

  As described above, when a dedicated cache area is allocated, memory is accessed using the dedicated cache area to which instructions in the process are allocated.

[Release dedicated cache area with dedicated area release request]
Next, when a dedicated area release request is issued in the process of the application program 22 (S404), the cache allocation management unit 204 executes a dedicated cache area release process (S405). Specifically, the cache sector ID corresponding to the local sector ID in the sector ID conversion table is changed to ID = 0 of the shared cache area (S406). That is, it is as shown as S406 in FIG. In addition, the size of the cache sector ID to be released in the cache sector information setting unit 132 is changed to zero.

[Details of cache area dynamic allocation processing according to this embodiment]
Details of the cache area dynamic allocation processing will be described below. As shown in FIG. 3, the dynamic allocation process includes a determination process S16 for a dedicated area acquisition request and a determination process S18 at a periodic allocation review timing. Before describing them in order, an index for determining cache area allocation will be described.

[Index for determining the allocation of a cache area]
[Real cache hits]
The purpose of dividing the cache memory into a shared cache area and a plurality of dedicated cache areas (including a disturbance processing cache area) is to maximize the number of cache hits per unit time of the entire cache memory. The number of cache hits per unit time can be obtained by the following equation.
Cache hits per unit time = cache hit rate * memory access frequency (1)
Therefore, when a dedicated cache area is allocated to a dedicated area acquisition request, if the number of cache hits of the target process of the dedicated area acquisition request is high, the total cache hit count can be increased by allocating the dedicated cache area to the request. it can. Rather than assigning a dedicated cache area to a target process with a high cache hit rate but a low memory access frequency, it is better to assign a dedicated cache area to a target process with a high memory access frequency even if the cache hit rate is slightly lower. , (1) can be increased, the number of times to shorten the time for accessing the main memory is increased, and the memory access as a whole can be shortened.

On the other hand, there is a priority in the processing of application programs, and there is a demand for particularly speeding up a specific application program or a specific process. The higher the request, the higher the processing priority. Therefore, in practice, the purpose of dynamic allocation of cache areas is to maximize the following number of actual cache hits.
Actual cache hit count = Σ (Process cache hit count * Processing priority) (2)
That is, in the above equation (2), Σ means that the number of cache hits of the process targeted for the dedicated area acquisition request multiplied by the priority of the process is accumulated for all processes.

[Locality of memory access]
Next, there are processes with high locality of memory access and those with low locality in the processing of the target of the dedicated area acquisition request. The locality of the memory access is high if the address area of the memory access is concentrated in a narrow range, and the locality is low if it is distributed in a wide range. When the locality of the memory access of the target process is low, the cache hit rate is low. However, increasing the cache size may increase locality and increase the cache hit rate.

  The relationship between the locality and the cache size can be understood from an example of the characteristic curve of the cache hit rate with respect to the cache size shown in FIG. In this example, when the cache size is small, the cache hit rate is not improved because the cache size is small compared to the address range for memory access. However, by increasing the cache size, the cache size catches up with the memory access address range, and the cache hit rate is improved. Even if the cache size is made larger than the reference value x, the cache hit rate is not improved.

  Furthermore, when the locality of memory access is extremely high, even if the cache size is increased, the cache hit rate cannot be improved, and the cache miss hit rate remains high. If such a process with a high cache miss hit rate is assigned to the shared cache area, cache misses occur frequently and expel data of other processes. Such processing is called disturbance processing.

  Therefore, for such disturbance processing, allocating a dedicated cache area rather than allocating a shared cache area is beneficial for improving the cache hit rate of the shared cache area. However, since such disturbance processing frequently causes cache miss hits even if a dedicated cache area is allocated, the actual cache hit rate of Expression (2) does not increase. Therefore, it is effective to allocate a cache area for disturbance processing to the disturbance processing, and to allocate a common disturbance processing cache area to a plurality of disturbance processes to isolate these processes from other cache areas. is there.

[Effective usage of cache, effective usage of actual cache, cache disruption]
Next, as an index for determining whether or not to allocate a dedicated cache area in response to a dedicated area acquisition request, the cache effective usage, the actual cache effective usage, and the cache disturbance power will be described.

The cache effective utilization is a degree indicating how much the cache hit number when the shared cache area is allocated is improved over the cache hit number when the dedicated cache area is allocated. That is, the cache effective utilization is as shown in the following equation (3).
Effective cache utilization = {(cache hit rate in dedicated area−cache hit rate in shared area) * memory access frequency} / size of dedicated cache area used (3)
In other words, the effective cache utilization (degree) is the difference in the cache hit rate that indicates how much the cache hit rate increases when the dedicated cache area is allocated rather than when the shared cache area is allocated. This is an index indicating an increase in the number of cache hits multiplied by (number of memory accesses per unit time) per unit cache area.

  In this case, the cache hit rate for the dedicated area and the memory access frequency can be acquired from the result of the characteristic investigation performed in advance, and the cache hit rate for the shared area can be acquired during the actual operation. If a dedicated cache area has already been allocated, the cache hit rate can be acquired for the allocated dedicated cache area. Therefore, for the allocated dedicated cache area, the actual cache hit ratio for the allocated cache size is obtained, and the ratio of the cache hit ratio for the same cache size in the previous characteristic survey is obtained from the previous characteristic survey. The estimated cache hit rate can be obtained by multiplying the cache hit rate against the cache size. The estimated cache hit rate will be described in detail later.

Next, the application program process has the above-described priorities, and it is necessary to preferentially improve the number of cache hits as the processing has a higher priority. Therefore, as shown in the following equation (4), the actual cache effective usage can be calculated by multiplying the above-mentioned cache effective usage by the priority of the corresponding processing.
Effective usage of actual cache = Effective usage of cache * Corresponding processing priority (4)
In equations (3) and (4), the cache hit rate for the dedicated area is H (x) in FIG. 5, the cache hit rate for the shared area is BASEH, the memory access frequency is MACCESS, and the size of the dedicated cache area is x In addition, when the corresponding processing priority is replaced with PRIORITY, the actual cache effective utilization degree of Expression (4) is as follows.
Real cache effective usage = [{H (x) −BASEH} * MACCESS * PRIORITY] / x (4)
As for the actual cache effective usage, the estimated cache hit rate can be used for the allocated dedicated cache area.

  The effective cache usage of equation (3) and the actual cache effective usage of equation (4) multiplied by priority are mainly to determine whether or not a dedicated area should be allocated to a dedicated area acquisition request. Used as an indicator.

Next, as the locality of the memory access described above is extremely high, the ability to expel data of other processes becomes stronger when assigned to the same shared cache area as other processes. This expelling power is assumed to be a cash disturbance power. This cache disturbing force can be calculated by multiplying the cache miss hit rate (1-cache hit rate) by the memory access frequency as shown in the following equation (5).
Cache disturbance power = (1-Cache hit rate) * Memory access frequency (5)
The cache disturbance force is a value that is contrary to the effective use of the cache. The cache disturbance power can be calculated for each process or for each process in advance because the cache hit rate and the memory access frequency are acquired in the characteristic investigation under the development environment. Processing that exceeds the standard value with this cache disturbing power is regarded as cache disturbing processing, and it is isolated from the shared cache area and other dedicated cache areas and allocated to the disturbing cache area, so that the cache hit rate of other processes Can be suppressed.

  The cache disturbance power is used as an index for determining whether or not to allocate a dedicated area for disturbance processing when determining whether or not to allocate a dedicated area in response to a dedicated area acquisition request.

[Dedicated area acquisition request determination processing S16 (1)]
FIG. 8 is a flowchart of a first example of the determination process S16 for the dedicated area acquisition request shown in FIG. In the first determination process, the cache allocation management unit 204 in the OS 20 calculates and determines the cache disturbing power (formula (5)) of the target process of the dedicated area acquisition request (S30), and there is a cache disturbing power. If it is higher than the first reference value (YES in S31), a disturbance processing cache area is allocated to the dedicated area acquisition request (S32).

  Furthermore, when the cache disturbance power is less than or equal to the first reference value (NO in S31), the cache allocation management unit 204 calculates the actual cache effective usage (expression (4)) of the target process of the dedicated area acquisition request. If the real cache effective usage is higher than the second reference value (YES in S34), a dedicated cache area is allocated to the dedicated area acquisition request (S35), and the actual cache effective usage is When the value is equal to or smaller than the second reference value (NO in S34), a shared cache area is allocated to the dedicated area acquisition request (S36).

  FIG. 9 is a diagram for explaining a case where a dedicated cache area is allocated to a dedicated area acquisition request. Assume that a dedicated area acquisition request 30 is issued in the divided state of the cache memory 130 of (1) in FIG. In this case, the actual cache validity of the target process of the dedicated area acquisition request is calculated based on the formula (4). If the actual cache validity is higher than the second reference value, a dedicated cache area with a cache sector ID = 2 is allocated to the dedicated area acquisition request 30 as in the cache memory 130 of (2) in FIG. . As a result, the allocated dedicated cache area is hereinafter referred to as an allocated dedicated area, and the allocated dedicated area acquisition request is referred to as an allocated dedicated area acquisition request.

  Furthermore, the size of the dedicated cache area to be allocated will be described. As shown in FIG. 5, the cache hit rate of processing increases rapidly by increasing the cache size, and saturates at a certain reference cache size x1. Therefore, it is desirable to calculate the actual cache effective usage based on the cache hit rate at the reference cache size x1 in the characteristic curve of cache size vs. cache hit rate in FIG. When the actual cache effective usage calculated in this way is larger than the second reference value, the size of the dedicated cache area allocated to the dedicated area acquisition request is set to the reference cache size x1. desirable.

  Thus, by automatically assigning the cache size of the dedicated cache area to the reference cache size x1, it is possible to assign an optimum cache size.

  According to FIG. 9, when the dedicated cache areas are successively assigned to the dedicated area acquisition requests whose actual cache effective usage is higher than the second reference value, the cache memory 130 overflows with the dedicated cache area. Therefore, it is possible to avoid overflowing the cache memory with the dedicated cache area by optimizing the balance between the shared cache area and the dedicated cache area by the periodic allocation review process (3) described later.

[Dedicated area acquisition request determination processing S16 (2)]
FIG. 10 is a flowchart of a second example of the determination process S16 for the dedicated area acquisition request shown in FIG. In the second determination process, the cache allocation management unit 204 in the OS 20 calculates the cache disturbance force of the target process for the dedicated area acquisition request and allocates the disturbance process cache area when it is larger than the first reference value (S30). , S31, S32) is the same. Then, when the cache disturbance power is equal to or less than the first reference value, the cache allocation management unit 204 performs the processing for the dedicated area acquisition request and the actual cache effective utilization level (preferably the actual cache effective utilization value of the allocated dedicated area). If the replacement rate is more efficient (YES in S37), a dedicated area is allocated to the dedicated area acquisition request, the allocated dedicated area is released, and both are switched. (S39). Conversely, if it is not efficient to replace (NO in S37), the shared cache area is allocated to the dedicated area acquisition request (S40).

  FIG. 11 is a diagram for explaining processing for exchanging a dedicated cache area between a dedicated area acquisition request and an allocated dedicated area acquisition request. When the dedicated area acquisition request 30 is issued in the divided state such as the cache memory 130 in FIG. 11 (1), if the cache disturbance power of the target process is equal to or less than the first reference value, It is determined whether or not the number of cache hits in the entire cache memory can be increased by replacing and assigning a new dedicated area.

  In the example shown in FIG. 11, the actual cache effective usage of the target process of the dedicated area acquisition request exceeds the overhead value required for the replacement than the actual cache effective usage of the allocated dedicated area with the cache sector ID = 2. Therefore, the allocated dedicated area is released and moved to the shared cache area. Instead, a new dedicated cache area is allocated to the dedicated area acquisition request.

  Therefore, the comparison determination S37 will be described.

  First, the cache hit rate is handled differently depending on whether the dedicated cache area has already been allocated or not yet allocated. The estimated cache hit rate is used for the allocated dedicated area, and the cache hit rate acquired in the preliminary survey is used for the unallocated dedicated area.

  FIG. 12 is a diagram showing an estimated cache hit rate. In the figure, the horizontal axis represents the cache size and the vertical axis represents the cache hit rate. The solid line H (x) is a characteristic curve of the cache hit rate with respect to the cache size obtained in the preliminary survey. On the other hand, in the case of the allocated dedicated cache area, the cache hit rate for the allocated cache size x2 can be acquired from a counter in the cache system.

In that case, the ratio SH (x2) / H (x2) between the current cache hit rate SH (x2) at the cache size x2 and the cache hit rate H (x2) at the preliminary survey is By multiplying the cache hit rate H (x) with respect to the cache size, an estimated cache hit rate SH (x) can be obtained. That is, it is as the following formula (6).
SH (x) = {SH (x2) / H (x2)} * H (x) (6)
If this estimated cache hit rate SH (x) is used, the actual cache effective usage of the allocated dedicated cache area can be derived from the above equation (4) as the following equation (7).
CCn = [{SH (x) −BASEH} * MACCESSn * PRIORITYn] / x (7)
Here, n indicates a target process for a dedicated area acquisition request. Therefore, Equation (7) is the actual cache effective utilization rate using the estimated cache hit rate SH (x) for a certain target process. Then, the effective usage rate of the real cache in response to the unallocated dedicated area acquisition request is as shown in the above equation (4) and is as follows.
Real cache effective usage n = [{H (x) −BASEH} * MACCESSn * PRIORITYn] / x (4)
A dedicated cache area of a certain size x is allocated to the dedicated area acquisition request. Therefore, in order to determine replacement with the allocated dedicated cache area, it is effective to consider the increase value of the actual cache effective usage per unit area (the increase rate of the actual cache effective usage). By using this, it is possible to consider how much the actual cache effective utilization level changes depending on whether the size of the allocated dedicated cache area is incremented by 1 or minus 1.

The increase rate CHHn (x) of the actual cache effective usage is an increase amount of the actual cache effective usage when the size of the dedicated cache area to be allocated is increased from x-1 to x. Equation (8) is obtained.
CHHn (x) = {SH (x) −SH (x-1)} * MACCESSn * PRIORITYn (8)
As can be seen from equation (8), CHHn (x) is the rate of increase in the effective number of effective real cache usage since it is not divided by the area size x as in equation (7). Hereinafter, the equation (8) is referred to as an increase rate of the number of actual cache effective uses.

If the dedicated area is not allocated to the dedicated area acquisition request, the estimated cache hit rate SH (x) cannot be used. Therefore, the cache hit rate H (x) in the preliminary survey is used to execute the above equation (8). The increase rate CHHn (x) of the cache effective number is expressed by the following equation (9).
CHHn (x) = {H (x) −H (x-1)} * MACCESSn * PRIORITYn (9)
In the determination step S37 of the present embodiment, the allocated dedicated area list LIST-FREE in which the increase rate of the actual cache effective usage number of Expression (8) is calculated for the allocated dedicated cache area is used. Hereinafter, the allocated dedicated area list LIST-FREE will be described.

  FIG. 13 is a diagram showing an allocated dedicated area list LIST-FREE and an unallocated dedicated area list LIST-DEMAND. The right side of FIG. 13 shows the allocated dedicated area list LIST-FREE. In the cache memory 130, when the allocated dedicated area (cache sector ID = 1, 2) is replaced with the shared cache area (cache sector ID = 0), the formula shows how the increase rate of the effective number of actual caches is ( 8) and registered in the allocated dedicated area list LIST-FREE in ascending order of increase rate. A small increase rate means that the number of real cache hits decreases when the allocated dedicated area is replaced with the unit area only, and does not contribute to the effective use of the current cache memory. To do.

  As described above, in the allocated dedicated area list LIST-FREE on the right side of FIG. 13, the increasing rates (LIST-FREE.CHH) are arranged in ascending order of increasing rate.

  The left side of FIG. 13 shows the unallocated dedicated area list LIST-DEMAND. In the cache memory 130, when a dedicated area is not allocated for a dedicated area acquisition request, a shared area is allocated, and a dedicated area is allocated only for a part of the size for the dedicated area acquisition request. In this case, since the remaining sizes are allocated to the shared areas, unallocated dedicated areas that are not allocated to these dedicated areas are included in this unallocated dedicated area list LIST-DEMAND.

  Then, when the unallocated dedicated area is replaced from the shared area to the dedicated area, the increase rate of the actual cache effective usage number is calculated by the equation (9), and the unallocated order is increased in descending order. Register in the dedicated area list LIST-DEMAND. A large increase rate means that the number of actual cache hits increases when the unallocated dedicated area is replaced from the shared area to the dedicated area, which means that the replacement greatly contributes to effective use of the cache memory. To do.

  As described above, in the unallocated dedicated area list LIST-DEMAND on the left side of FIG. 13, the increasing rates (LIST-DEMAND.CHH) are arranged in descending order of increasing rate.

  Therefore, in the determination step S37 of the present embodiment, an increase in the effective number of actual caches when the dedicated area is allocated to the dedicated area acquisition request 30, and the allocation registered in the allocated dedicated area list LIST-FREE. If the difference in the decrease in the effective cache effective usage count of the dedicated dedicated area exceeds the overhead value required for replacement, it is determined that the dedicated area should be allocated to the dedicated area acquisition request after replacement.

This determination is made based on whether or not the following equation (10) is satisfied.
y * CCn (y) −Σ (m = 1−y) LIST-FREEm.CHH> OVH2 * {Σ (m = 1−y) LIST-FREEm.PRIORITY} (10)
Here, y indicates the size y of the dedicated area, m indicates the number in the list, LIST-FREEm.CHH indicates the rate of increase in the effective number of actual caches used, OVH2 indicates the overhead value required for replacement, LIST- FREEm.PRIORITY indicates the priority of the processing. That is, the overhead value OVH2 is weighted with priority.

  The cache allocation unit 204 in the OS 20 determines Expression (10) from y = 1, and sets the maximum size y that satisfies the condition of Expression (10) as the size of the dedicated area allocated to the dedicated area acquisition request. That is, the exchange indicated by the arrow between the dedicated area acquisition request 30 and the allocated dedicated area list LIST-FREE shown in FIG. 13 is performed. As a result, the allocated dedicated area corresponding to the size y is released to the shared area. If any size y does not satisfy Expression (10), a dedicated area is not allocated to the dedicated area acquisition request.

  As shown in FIG. 12, the characteristics of the cache hit rate tend to increase rapidly when the cache size is increased to some extent. Therefore, by increasing the size y of the dedicated area to be newly allocated from 1, a size y that satisfies the expression (10) may be found. In particular, the condition of formula (10) may be satisfied when the size y is near the reference value x1.

  The relationship between the cache size y that satisfies the condition of Expression (10) and the cache size requested by the dedicated area acquisition request 30 is, for example, as follows. If the cache size y that satisfies the condition is less than or equal to the requested cache size, the cache memory efficiency can be improved by assigning a size from the cache size y to the requested cache size. On the other hand, when the cache size y exceeds the required cache size, it is preferable not to allocate the dedicated area by determining that the condition of the expression (10) is not satisfied.

  FIG. 24 is a flowchart of the dedicated area acquisition request determination process S16 (2). The same processes as those in FIG. 10 are given the same numbers. First, the cache allocation management unit 204 determines whether or not the cache disturbance power exceeds the first reference value (S30, 31), and if it exceeds, allocates a dedicated disturbance processing cache area (S32). As a result, in the sector ID conversion table 131, the cache sector ID of the disturbance processing cache area is linked to the local sector ID of the dedicated area acquisition request (S32-1).

  If the cache disturbance power does not exceed the first reference value, the cache allocation management unit 204 determines whether to allocate a dedicated cache area based on whether there is a size y satisfying the equation (10). Perform (S37, 38). If the condition is not satisfied, the cache allocation management unit 204 allocates a shared area to the dedicated area acquisition request (S40), and if the condition is satisfied, allocates a dedicated area of size y to the dedicated area acquisition request. Is instructed to the hardware (S39).

  In hardware, the cache allocation management unit 204 sets a dedicated cache area to be newly allocated and its size y in the cache sector information setting unit 132 (S39-1). In addition, the cache sector ID of the allocated dedicated area to be replaced is deleted and the size is changed at the same time (S39-1). Then, the cache allocation management unit 204 associates the cache sector ID of the allocated dedicated cache area with the local sector ID of the dedicated area acquisition request in the sector ID conversion table 131 (S39-2).

[Regular allocation review process S18]
Next, three examples of the regular allocation review process S18 in FIG. 3 will be described. In response to the dedicated area acquisition request, the cache allocation management unit 204 in the OS 20 determines whether to allocate a dedicated cache area or to replace it with an allocated dedicated area.

  On the other hand, the cache allocation management unit 204 periodically allocates an allocated dedicated area allocated to the dedicated area acquisition request and an unallocated dedicated area that has not yet been allocated to the dedicated area acquisition request, for example, every 2 seconds. If the ratio of the size of the shared area and the total dedicated area deviates from the ideal value based on the access frequency ratio (Example 1 and Example 2) whether or not to replace, the shared area is not designated as a dedicated area. A determination is made as to whether to newly allocate the dedicated area acquisition request for allocation or to release the allocated dedicated area and replace it with the shared area (example 3). In these determinations, the above-mentioned allocated dedicated area list LIST-FREE and unallocated dedicated area list LIST-DEMAND are used.

[Regular allocation review process S18 (1)]
FIG. 14 is a flowchart of a first example of the periodic allocation review process S18. FIG. 15 is a diagram for explaining a first example of the periodic allocation review process S18. In FIG. 14, in the periodic allocation review process S18, the cache allocation management unit 204 determines whether to replace the unallocated dedicated area and the allocated dedicated area (S50). In this determination processing, the increase rate CHHn (x) of the actual cache effective usage number of the unallocated dedicated area in the unallocated dedicated area list LIST-DEMAND described in FIG. 13 and the allocation in the allocated dedicated area list LIST-FREE The increase rate CHHn (x) of the actual cache effective usage number of the dedicated dedicated area is compared (S51). For example, as shown by an arrow in FIG. 15, the comparison target is the highest increase rate at the top in the unallocated dedicated area list LIST-DEMAND and the minimum at the top in the allocated dedicated area list LIST-FREE. The rate of increase is compared, and the rate of increase below is compared.

If the condition of the following equation (11) is satisfied, it can be considered that efficiency is improved by replacement (S52).
LIST-DEMANDm.CHH-LIST-FREEm.CHH> OVH2 * LIST-FREEm.PRIORITY (11)
Here, m indicates the order of the list, OVH2 indicates the overhead value required for replacement, and LIST-FREEm.PRIORITY indicates the priority of processing in the allocated dedicated area list LIST-FREE. In other words, if the difference from the increase rate of the unallocated dedicated area to be compared to the increase rate of the allocated dedicated area exceeds the overhead value OVH2 associated with the replacement, the efficiency is considered to increase. It is.

  The condition of Expression (11) is determined in order from the top (m = 1) of both lists, and is repeatedly determined until the order in which this condition is not satisfied. However, since priority LIST-FREEm.PRIORITY is included in equation (11), the value on the right side varies depending on the priority. Therefore, not only the highest increase rate CHH in the allocated dedicated area list LIST-FREE but also the highest increase ratio CHH in the highest level in the unassigned dedicated area list LIST-DEMAND. The lower rate of increase CHH is also included in order. If combinations that satisfy equation (11) are found, they become the replacement targets. Then, for the next increase rate CHH in the unallocated dedicated area list LIST-DEMAND, the same comparison as described above is performed, and a combination satisfying Expression (11) is detected.

  When it is considered that the efficiency is improved by the replacement, the cache allocation management unit 204 performs a process of replacing the unallocated dedicated area and the allocated dedicated area (S53). Specifically, the cache sector information setting unit 132 newly allocates a dedicated area to the unallocated dedicated area, registers the allocated size, and newly sets the local sector ID of the unallocated dedicated area acquisition request in the sector ID conversion table. The cache sector ID of the dedicated area to be allocated is linked. Conversely, the cache sector information setting unit 132 cancels the registration of the allocated dedicated area, and the cache sector ID linked to the local sector ID of the allocated dedicated area acquisition request in the sector ID conversion table is changed to the shared area ID. Change to

  When the replacement process is performed, the increase rate of the replaced dedicated area is moved from the unallocated dedicated area list LIST-DEMAND to the allocated dedicated area list LIST-FREE, and at the same time from the allocated dedicated area list LIST-FREE. Move to the unallocated private area list LIST-DEMAND. Further, the list is sorted again based on the value of the increase rate CHH in each list.

  If the efficiency is not considered to be improved by the replacement, the cache allocation management unit 204 does not perform the process of replacing the unallocated dedicated area and the allocated dedicated area (S54).

[Regular allocation review process S18 (2)]
FIG. 16 is a flowchart of a second example of the regular allocation review process S18. FIG. 17 is a diagram for explaining a second example of the periodic allocation review process S18. In FIG. 16, in the periodic allocation review process S18, the cache allocation management unit 204 determines whether to replace the unallocated dedicated area and the allocated dedicated area (S60). In this determination processing, as shown in FIG. 17, the dedicated cache area size x of the increase rate CHH ₁ (x) of the actual cache effective usage number of the _first unallocated dedicated area in the unallocated dedicated area list LIST-DEMAND is increased. While increasing the increase rate CHHm (x) of the effective number of actual caches in the allocated dedicated area in the allocated dedicated area list LIST-FREE from the top, the cumulative values of the two are compared (S61).

This determination S61 is made based on whether or not the following equation (10) is satisfied.
Σ (x = 1-y) LIST-DEMAND ₁ .CHH (x) −Σ (m = 1-y) LIST-FREEm.CHH>
OVH2 * {Σ (m = 1-y) LIST-FREEm.PRIORITY} (12)
Where y is the size of the dedicated area, y is the number in the list, LIST-DEMAND ₁ .CHH, LIST-FREEm.CHH is the rate of increase in the effective number of real caches, and OVH2 is required for replacement Indicates the overhead value, and LIST-FREEm.PRIORITY indicates the priority of the processing. Again, the overhead value OVH2 is weighted by priority.

The cache allocation unit 204 in the OS 20 performs the determination of Expression (12) while increasing from y = 1, and detects the maximum size y that satisfies the condition of Expression (12). That is, the increase rate CHH ₁ (x) of the actual cache effective usage number is an increase amount of the actual cache effective usage number when the unit size is increased. Then, as shown in FIG. 12, the cache hit rate tends to increase as the size x of the dedicated cache area increases, so the increase rate CHH ₁ (x) of the actual cache effective number of unallocated dedicated areas is maximized. The size x of the possible dedicated cache area is compared with the increase rate of the allocated dedicated area of the same size, and is to be replaced. This is the same idea as that of Expression (10).

  When it is considered that efficiency is improved by replacing the above equation (12), the cache allocation management unit 204 performs a process of replacing the unallocated dedicated area and the allocated dedicated area (S63). When the efficiency is not considered to be improved by the replacement, the cache allocation management unit 204 does not perform the replacement process (S64).

  The relationship between the cache size requested by the unallocated dedicated area acquisition request 30 and the cache size y satisfying Expression (12) is the same as that described with reference to FIG. 13 for the dedicated area acquisition request determination process (2). That is, if the cache size y satisfying Expression (12) is equal to or smaller than the requested cache size, a size between the size y and the requested size is assigned. When the cache size y exceeds the requested cache size, the replacement process is not performed because Expression (12) is not satisfied.

[Regular allocation review process S18 (3)]
FIG. 18 is a flowchart of a third example of the periodic allocation review process S18. FIG. 19 is a diagram for explaining a third example of the periodic allocation review process S18. In the third example of the periodic allocation review process S18, if there is a divergence between the ideal size of the shared cache area based on the actual weighted memory access ratio and the actual size of the shared cache area, the shared cache area In order to bring the area closer to the ideal size ratio, a replacement process is performed to allocate the shared cache area as a dedicated cache area to an unallocated dedicated area acquisition request or to release the allocated dedicated cache area and allocate it to the shared cache area.

  In the left and right cache memories 130 shown in FIG. 19, a solid line indicates an actual size ratio, and a broken line indicates an ideal size ratio. Since the shared cache area is larger than the ideal size in the cache memory 130 on the left side, it is desirable to allocate that amount as a dedicated area to an unallocated dedicated area acquisition request. On the other hand, since the shared cache area of the right cache memory 130 is smaller than the ideal size, it is desirable to release the allocated dedicated area and change it to the shared area.

The ideal size of the shared cache area is obtained by the following equations (13) and (14).
MACCESSXn = Σ (m = 1-n) MACCESSm * PRIORITYm (13)
RSIZE _SHR = CEIL {(MACCESSX _SHR / MACCESSX _ALL ) * SIZE _ALL } (14)
Here, MACCESSXn indicates the total value of the weighted memory access amounts of the n target processes, MACCESSm indicates the memory access amount of the target process m, and PRIORITYm indicates the priority of the process m. RSIZE _SHR indicates the ideal size of the shared cache area (SHR), and MACCESSX _SHR , MACCESSX _ALL , and SIZE _ALL indicate the amount of access to the shared cache area (SHR), the amount of access to all cache areas, and the total cache area. Indicates the size. CEIL means rounding up.

  Therefore, since the total value of the weighted memory access amounts of the n target processes is obtained by Expression (13), the weighted memory access amounts of all the target processes that use the shared cache area can be calculated by Expression (13). Similarly, the weighted memory access amounts of all the target processes that use the entire dedicated cache area or the entire cache area can be similarly calculated by Expression (13).

Equation (14) is obtained by dividing the ideal size RSIZE _SHR of the shared cache area by dividing the total cache area size (SIZE _ALL ) by the weighted memory access to the shared area and the dedicated area (MACCESSX _SHR / MACCESSX _ALL ). ing. Therefore, the ideal size RSIZE _SHR of the shared cache area is obtained based on the weighted memory access number ratio between the shared area and the dedicated area.

Then, the ideal size of the shared cache area described above is compared with the actual size, and it is determined whether or not the difference exceeds the overhead value OVH1 required for replacement. The determination is made based on whether or not the following equation (15) is satisfied.
ABS {MACCESSX _SHR -MACCESSX _ALL * (SIZE _SHR / SIZE _ALL )> OVH1 (15)
Here, ABS indicates an absolute value.

Expression (15) is a first weighted access frequency MACCESSX _SHR obtained by weighting the memory access frequency in the target process allocated to the shared cache area during the process execution by the priority of each target process, and the memory access of each target process. Cumulative value of weighted access frequency weighted by priority of each target process MACCESSX _ALL Second weighted access of shared cache area that is divided by size ratio (SIZE _SHR / SIZE _ALL ) of shared cache area and dedicated cache area Conditional expression when the difference from the frequency MACCESSX _ALL * (SIZE _SHR / SIZE _ALL ) is higher than the overhead value OVH1. When this conditional expression is satisfied, the allocated dedicated cache area is replaced with a shared cache area or the shared cache area is replaced with an unallocated dedicated cache area by a size corresponding to the difference.

The above equation (15) becomes the following equation (16) when the entire equation is multiplied by SIZE _ALL / MACCESSX _ALL .
ABS {(MACCESSX _SHR / MACCESSX _ALL ) * SIZE _ALL -SIZE _SHR }> OVH1 * (SIZE _ALL / MACCESSX _ALL ) (16)
ABS {(RSIZE _SHR -SIZE _SHR )}> OVH1 * (SIZE _ALL / MACCESSX _ALL ) (16)
That is, it is the same as determining whether the difference between the ideal size RSIZE _SHR of the shared cache area based on the actual weighted access frequency ratio and the actual size SIZE _SHR exceeds the overhead value.

  Therefore, if the above formula (15) or (16) is satisfied, the allocated dedicated cache area is replaced with the shared cache area so that the size of the shared cache area approaches the ideal size, or conversely, the shared cache area Replace the area with the unallocated dedicated cache area.

  Therefore, in the present embodiment, as shown on the left side of FIG. 19, when the actual size is larger than the ideal size of the shared area, the size (number of WAYs) of the dedicated area candidate list is increased and In the periodic review, it is recorded that a dedicated area can be allocated in response to an unallocated dedicated area acquisition request. Conversely, as shown on the right side of FIG. 19, when the actual size is smaller than the ideal size of the shared area, the size (number of WAYs) of the dedicated area borrowing list is increased. Record that the area can be allocated a shared area.

  In the periodic review, as shown on the left side of FIG. 19, the dedicated area is allocated from the head of the unallocated dedicated area list LIST-DEMAND by the size (number of WAYs) of the dedicated area candidate list. Alternatively, as shown on the right side of FIG. 19, the dedicated area is released from the top of the allocated dedicated area list LIST-FREE by the size (number of WAYs) of the dedicated area borrowing list.

  Describing again according to the flowchart of FIG. 18, the cache allocation management unit 204 determines the necessity of replacing the shared area and the dedicated area based on the difference between the ideal size and the actual size of the shared area (S70). Specifically, if the size of the dedicated area candidate list is positive (S71), a dedicated area is allocated to an unallocated dedicated area acquisition request (S72). On the other hand, if the size of the dedicated area borrowing list is positive (S73), the allocated dedicated area is released (S74).

  When the difference between the ideal size and the actual size of the shared area does not exceed the overhead value, the cache allocation management unit 204 executes the periodic allocation review processing (1) and (2) described with reference to FIGS. ).

  In the third example above, it is desirable to allocate the cache size (number of ways) recorded in the dedicated area candidate list.

[Replacement process of sector ID conversion table at process switching]
FIG. 25 is a diagram showing a sector ID conversion table replacement process when the application program process 22 is switched. When the switching source operation process 22A stops the process, the process management unit 202 in the OS performs the process stop processing (S81), and simultaneously controls the cache allocation management unit 204 to switch the sector ID conversion table. Instructed (S83), the sector ID conversion table of the switching source operation process 22A is replaced with the sector ID conversion table of the switching destination operation process 22B (S84). Thereafter, the process management unit 202 starts the process operation of the switching destination operation process 22B (S86).

  As described above, when the process is switched, the process management unit 202 causes the cache allocation management unit 204 to replace the sector ID conversion table, and the switching destination process accesses the memory based on the cache memory division state of the sector ID conversion table. .

  In the first embodiment, in the determination (1) for the dedicated area acquisition request in FIG. 8, if the actual cache effective usage of the target process of the dedicated area acquisition request exceeds the second reference value, the dedicated area is determined. Assigned. In this determination, whether or not a dedicated area is allocated may be determined using, as an index, the cache effective utilization level that is not multiplied by the priority in Expressions (4) and (7).

  In the first embodiment, in the determination (2) for the dedicated area acquisition request in FIG. 10-13, whether the dedicated area is allocated to the dedicated area acquisition request by using the increase rate of the actual cache effective usage number as a determination index. Judged whether or not. Also in this determination, the presence / absence of dedicated area allocation may be determined using as an index the increase rate of the number of cache effective uses not multiplied by the priority in equations (8) and (9).

  In the first embodiment, the periodic allocation review (1), (2), and (3) may be similarly determined using an index that does not consider the priority.

[Second Embodiment]
The second embodiment relates to a cache memory control program for a stack memory area that stores a local variable of a subroutine when a subroutine such as a function or a module is called in the program.

  As described above, the OS collectively stores and manages local variables of subroutines called hierarchically in the stack memory area in the main memory. When the subroutine program reads or writes a local variable, memory access is executed to the stack memory area in the main memory. In memory access to this stack memory area, as in normal memory access processing, cache hit determination is first performed in the cache memory, and access to the stack memory area in the main memory in the case of a cache miss hit is performed. Is called.

  The subroutine includes a function and a module. In the following embodiment, a function that is one of the subroutines will be described as an example. However, when a module is called (call) or called back (return), it is the same as when a function is called or called back. Function arguments are treated as local variables.

  FIG. 26 is a diagram illustrating the relationship between the cache memory and the stack memory area according to the second embodiment. A cache memory 130 is provided adjacent to the CPU (or CPU core) 12. When the CPU 12 executes a memory access to a local variable in the function, a cache hit determination is performed on the cache memory. If the cache hit occurs, the data in the cache memory is accessed, and if a cache miss occurs, the external interface 14 is accessed. Data in the stack memory area in the main memory 16 is accessed.

  Various data and programs are stored in the main memory 16. For example, when the program PR is executed, a heap area for storing variables and array data and a stack memory area ST for storing local variables of functions to be called are stored in the main memory 16 for each program PR1-PR4. Secured.

  The stack memory area has the following stack structure. That is, when functions A, B, C, D, A, and C are called hierarchically in a program, local variable data of the called functions are stored in the stack memory area in that order. Is done. As shown in FIG. 26, when functions A, B, C, D, A, and C are called in order, local variables of functions A, B, C, D, A1, and C1 are stored in the stack memory area. Data is stored in order. When the execution of the function is completed and the function is called back, the stack memory area corresponding to the called function is released. Therefore, when the same function is called at different timings, a local variable is stored in the stack memory area for each of the called functions.

  When memory access is performed on the data in the stack memory area in the main memory 16, the memory accessed data is also stored in the cache memory 130. In the example of FIG. 26, local variable data of the functions B, C, and D is stored in the cache memory 130.

  FIG. 27 is a diagram showing a local variable of a function and variable data in the stack memory area. In the example of FIG. 27, the function A uses arguments in_in1, in_in2 and variables int_va1, String_Va2. In this case, these arguments and variables are collectively stored in the stack memory area corresponding to the function A as local variable data of the function A.

  FIG. 28 is a diagram showing functions in a program and a stack memory area. In the program illustrated in FIG. 28, the function A is called, the function B is called in the function A, the function C is called in the function B, the function D is called in the function C, and the function D ends. In this example, the function E is read after being called back.

  In this case, in the stack memory area, as shown in the figure, the local variable data area of function A (local variables in1, in2, va1, va2 in FIG. 27), the local variable data area of function B, and the function The local variable data area for C and the local variable data area for function D are secured in a stack structure in the stack memory. When the function D is finished and called back, the local variable data area of the function D is released from the stack memory. When the function E is called after that, the local variable data area of the function E is newly added to the stack memory. Secured.

  FIG. 29 and FIG. 30 are diagrams for explaining problems of the cache memory for the stack memory area. In these examples, the cache memory 130 is shared by a plurality of functions.

  FIG. 29 shows an example of the stack memory area ST and an example of changes in the cache memory 130 corresponding to the stack memory area ST. (1) In an example in which the function C is executed for a long time, the functions A, B, and C are read out hierarchically in order, and the local variable data areas of the functions A, B, and C are stored in the stack memory area ST. Secured in order. Along with this, local variable data areas of the functions A, B, and C are written in the cache memory 130-1 immediately after the function C is called. However, when the function C is executed for a long time, the data of the process of the function C and the data in the memory area other than the stack memory area are once written into the cache memory 130-1 but then accessed. The local variable data of the functions A and B that did not exist are expelled and deleted.

  In such a case, when the function C being executed is terminated and memory access is performed on the local variable data of the function B immediately after that, the local variable data of the function B is deleted in the cache memory 130-2. As a result, repeated cache misses occur.

  (2) In the example in which the function D is called, the functions A, B, and C are read out hierarchically in order, and the local variable data of the functions A, B, and C are stored in the stack memory area ST in order. In this state, a new function D is called. In this case, if the local variable data of the function X that has already been executed is stored in the cache memory 130-3 in the cache memory 130, the local variable data of the function X is transferred to the main memory 16 and saved. Therefore, it is necessary to overwrite the local variable data of the function D read from the main memory 16 in the area where the local variable data of the function X is stored. Therefore, the process by reading the function D includes the process of saving the local variable data of the function X in the main memory, which increases the overhead.

  FIG. 30 shows (3) a change from the cache memory 130-5 to 130-6 in an example in which a large number of functions are called in a short time. In this example, when the function A is called, the local variable data of the function A is stored in the cache memory 130-5, and further, the functions B to Z are called hierarchically in a short time, thereby The local variable data of these functions are stored one after another in a wide area in the memory 130-6. As a result, data of other processes in the cache memory 130-6 may be erased and the cache memory 130-6 may be disturbed. As a result, the cache miss hit rate of other processes may decrease.

[Outline of Second Embodiment]
Therefore, in the second embodiment, the problems as pointed out in FIGS. 29 and 30 are solved by the cache memory control program. According to the cache memory control program of the second embodiment, in order to prevent local variable data of a function called in the past once stored in the cache memory from being erased by a memory access by another process. Allocate a dedicated cache area for each function to be called.

  However, when a large number of functions are called continuously, a large number of dedicated cache areas are allocated in the cache memory, and the use efficiency of the cache memory having a certain capacity is reduced for other processes. That is, the size of the cache area allocated to other processes is reduced and the cache hit rate is reduced.

  Therefore, the cache memory control program reserves a limited number of cache areas as a stack memory cache area group for a stack memory area for a function called in the program. Furthermore, in the stack memory cache area group, a first dedicated cache area allocated to the first function being executed, and one or a plurality of second calls called immediately before the first function being executed. In order to maintain the second dedicated cache area allocated to each function and a plurality of free cache areas, the allocation control of the dedicated cache area is performed for the called function and the called back function.

  The above free cache area is a cache area in which valid data that needs to be saved in the main memory is not stored, and is a cache area in which new data can be immediately overwritten. In addition, this free cache area is a kind of dedicated cache area in which data due to memory access of other functions and processes is not written.

  The plurality of cache areas in the stack memory cache area group have, for example, a certain size. Normally, the capacity of the stack memory area for storing function local variables is as small as 1MB or less, so even if you maintain the cache area allocated to each of multiple functions in the stack memory cache area group, it occupies that much memory capacity. Never do.

  FIG. 31 shows the stack memory area ST 130 in the cache memory 130 and the stack memory area ST in the cache memory 130 and the stack memory area ST at the time T1 when the function E is executed and the time T2 when the function E ends and is called back. It is a figure which shows -ST. In the stack memory area ST, local variable data of functions A, B, C, D, and E are stored in order. On the other hand, the cache memory control program allocates, for example, five cache areas (sector ID = 0-4) in the cache memory 130 for the stack memory areas for a plurality of functions. Secured as ST.

  Further, the cache memory control program executes the first dedicated cache area (sector ID) assigned to the function E being executed in the stack memory cache area group 130-ST (1) at the time T1 when the function E is being executed. = 4), the second dedicated cache area (sector ID = 2, 3) allocated to the two functions C and D read out immediately before the function E, and the function to be called next An empty cache area (sector ID = 0) and an empty cache area for the second called function (sector ID = 1) are maintained.

  That is, as shown on the stack memory area ST side, the cache areas corresponding to the functions C and D called immediately before the function E being executed and the two free cache areas for the function called after that are as follows. It is maintained in the stack memory cache area group 130-ST (1).

  The reason why the dedicated cache area of sector ID = 4 is allocated to the function E is that the functions A to E called hierarchically are assigned to the dedicated cache area of sector ID = 0 in the stack memory cache area group 130-ST. This is because they are assigned in order. As a result, if the stack memory depth starts from 0, a dedicated cache area of sector ID = 4 is allocated to the function E having the fifth stack depth.

  Next, at the time T2 when the function E ends and is called back, the cache memory control program allocates the free cache area (sector ID = 1) for the second function to the function B as the dedicated cache area at the time T1. , The local variable data of the function B is memory-accessed (prefetched) to the main memory and expanded in a dedicated cache area (sector ID = 1) assigned to the function B. Further, the cache memory control program allocates the dedicated cache area (sector ID = 4) allocated to the function E at the time T1 to the free cache area for the next function, and at the time T1 the free cache area for the next function ( Sector ID = 0) is allocated to the free cache area for the second function. The sector ID = 4, 0 is allocated to the next function free cache area and the second function free cache area, respectively, if the OS cache allocation management unit 204 performs the cache sector information setting unit 132 as described later. Often there is no need to write or save data in the cache memory.

  As a result, the cache memory control program executes the function being executed in the stack memory area ST in the stack memory cache area group 130-ST (2) at the time T2 when the function E ends and the function D starts executing. A second dedicated cache area (ID = 2, 1) assigned to the two functions C and B called immediately before the first dedicated cache area (ID = 3) assigned to D; An empty cache area (ID = 4, 0) for two functions to be called immediately after that is maintained. Therefore, the size of the stack memory cache area group 130-ST is limited to five from time T1 to time T2.

  Here, the number 2 of the second dedicated cache area allocated to the immediately preceding function and the number 2 of the subsequent function free cache areas are examples, and the number 5 of the cache areas in the stack memory cache area group is also an example. . The setting of these numbers will be described later. However, these numbers are set to a fixed limited number, and the size of the stack memory cache area group 13-ST is limited to a fixed range.

  FIG. 32 shows the stack memory area ST 130 and the stack memory cache area group 130 in the cache memory 130 at the time T1 when the function E is executed and the time T3 when the function E ends and is called back in the second embodiment. It is a figure which shows -ST. The stack memory cache area group 130-ST (1) at the time T1 during which the function E is being executed is the same as FIG.

  Next, at the time T3 when the next function F of the function E is called, the cache memory control program is called with the free cache area (sector ID = 0) for the next function at the time T1 as a dedicated cache area. Assigned to the function F, the local variable data of the function F is accessed (prefetched) in the main memory and written into the dedicated cache area (sector ID = 0) assigned to the function F. Further, the cache memory control program saves the local variable data of the function C in the dedicated cache area (sector ID = 2) assigned to the function C at time T1 to the main memory, and the cache area after the save (sector ID = 2) is allocated to the free cache area for the second function.

  As a result, the cache memory control program is allocated to the function F being executed in the stack memory area ST in the stack memory cache area group 130-ST (3) at the time T3 when the function F is called and started to execute. The second dedicated cache area (ID = 4, 3) assigned to the two functions E and D called immediately before the first dedicated cache area (ID = 0) and immediately after The free cache areas (ID1, 2) for the two functions to be called are maintained. Therefore, the size of the stack memory cache area group 130-ST is limited to five from time T1 to time T3.

  As described above, the cache memory control program is called back after the function is completed or when a new function is called, the stack memory cache area group 130-ST is being executed in the stack memory area ST. N second dedicated cache areas assigned to N functions that are called consecutively immediately before the function being executed centered on the first dedicated cache area assigned to the function, and execution It is maintained in the M dedicated free cache areas allocated to the M functions that are successively called immediately after the middle function. Therefore, if necessary, the local variable data in the dedicated cache area of the function evicted from the stack memory cache area group is saved to the main memory, and the local variable of the function newly added to the stack memory cache area group is saved. Data is prefetched and written from the main memory to the dedicated cache area.

  By controlling as described above, local variable data of a function that is likely to be executed in the future is stored in a separate dedicated cache area in the limited-size stack memory cache area group 130-ST. A dedicated free cache area is maintained in which local variable data of the called function can be written immediately without saving other data. Therefore, the problems described with reference to FIGS. 29 and 30 are avoided.

  Next, the setting of N for the second dedicated cache area and M for the free cache area will be described.

  FIG. 33 is a diagram for explaining the number N of N second dedicated cache areas allocated to N functions that are called continuously immediately before the function being executed. As described with reference to FIG. 31, when the function E ends and is called back, the cache memory control program starts prefetching local variable data in the stack memory area of the function B, and stores it in the free cache area allocated to the function B. Start writing the local variable data. That is, it is a cache restore process for local variable data of function B. This prefetch to the stack memory area generally involves a long time because it involves memory access to the main memory outside the CPU unit.

  Assuming that the functions D and C are continuously terminated following the termination of the function E, memory access to the local variable data of the function B is started after the termination processing of the functions D and C. At this time, if the local variable data of the function B is written in the free cache area allocated to the function B after completing the cache restoration, no cache hit miss occurs.

  Further, necessary processing is performed at the end of the functions E, D, and C, that is, at the time of recall. For example, software processing such as saving and restoring processing of registers and tables in the CPU of the function being executed.

  Therefore, after the end processing of the function E, the cache restoration by the memory access to the local variable data of the function B needs to be completed during the end processing (call back processing) of the functions D and C.

Therefore, the number N of the second dedicated cache areas needs to be greater than or equal to the number obtained by the following formula.
N = CEIL {memory access time of function local variable data in stack memory / time required for function call back processing} (17)
Here, CEIL means rounding up.

  That is, the number N of the second dedicated cache areas is set to at least the number of Expression (17), so that the number of cache areas in the stack memory cache area group is kept to a minimum and immediately before the execution of the function is completed. The memory hit to the local variable data of the function called in (1) can be surely made a cache hit. In the example of FIG. 31, N in Expression 17 is an example where N = 2.

  The number N of the second dedicated cache areas indicates the time required for performing cache restoration of the local variable data in the stack memory of the function B in the cache area in advance by the number of functions up to the prefetch target function. Therefore, this number N is referred to as prefetch size 2 (Prefetch_Size2).

  FIG. 34 is a diagram illustrating the number M of M dedicated free cache areas allocated to the M functions scheduled to be called continuously immediately after the function being executed. As described with reference to FIG. 32, when the function F next to the function E is called, the cache memory control program starts saving the local variable data of the function C in the stack memory area in the main memory. Since this save process is a write process to the stack memory area, it generally takes a long time.

  If the functions G and H are continuously called following the reading of the function F, the memory access to the local variable data of the function H is started after the calling processing of the functions G and H. By this time, if the local variable data save processing in the dedicated cache area assigned to the function C has been completed, the existing data is saved in the free cache area (ID = 2) for the second function. The local variable data of the called function H can be written without performing processing.

  Furthermore, after the function F is called, it is necessary to complete the save processing of the local variable data of the function C in the free cache area (ID = 0) during the calls of the functions G and H.

Therefore, the number M of dedicated free cache areas needs to be greater than or equal to the number obtained by the following equation.
M = CEIL {memory access time (data transfer time) of function local variable data into stack memory / time required for function call processing} (18)
That is, by setting the number M of dedicated free cache areas to at least the number of Expression (18), the number of cache areas in the stack memory cache area group is minimized, and the function locals when the function is called. Memory access to variable data can be started immediately without saving existing data. In the example of FIG. 32, M in Expression 18 is an example where M = 2.

  The number M of dedicated free cache areas is referred to as prefetch size 1 (Prefetch_Size1) as is the case with the number N.

  FIG. 35 is a diagram illustrating control of the sector ID conversion table by the cache memory control program according to the second embodiment. In the examples of FIGS. 31 and 32, five cache areas in the stack memory cache area group 130-ST are divided into one first dedicated cache area, two second dedicated cache areas, and two cache areas. It is cyclically changed to the dedicated free cache area.

  That is, when the function E of FIG. 31 is called and called back, the correspondence with the five cache areas is changed by decrementing the cache sector ID of the stack memory cache area group 130-ST by -1. However, ID = 0 is set to −1 by setting −1 to ID = 4. As a result, the cache sector ID of the dedicated cache area allocated to the function being executed is changed from the cache sector ID = 4 of the function E to the cache sector ID = 3 of the function D.

  Conversely, when the function F in FIG. 32 is read, the correspondence with the five cache areas is changed by incrementing the cache sector ID of the stack memory cache area group 130-ST by one. However, ID = 0 is incremented by 1 to set ID = 0. As a result, the cache sector ID of the dedicated cache area assigned to the function being executed has been changed from the function E cache sector ID = 4 to the function F cache sector ID = 0.

  In this way, the sector ID conversion table can be easily rewritten by changing the correspondence relationship cyclically. FIG. 35 shows a sector ID conversion table 131. In this example, the local sector ID = 0 in the sector ID conversion table 131 is assigned to the shared cache memory area, and the local sector ID = 1 is assigned to the dedicated cache memory area assigned to the function being executed. ID = 2 to N are assigned to a dedicated cache memory area different from the stack memory cache area group. Therefore, each time a function is called back or called, the cache allocation management unit 204 in the OS allocates a cache sector ID corresponding to the local sector ID = 1 in the sector ID conversion table 131 to the function being executed. The sector ID of the first dedicated cache area is rewritten.

  On the other hand, a memory access instruction to a local variable in a function is compiled and converted into a machine language instruction having a local sector ID = 1. For example, the machine language instruction 32 in FIG. 4 is converted so that the local sector ID is ID = 1 and the instruction sentence is a memory access instruction to a local variable. As a result, when a memory access instruction to a local variable in the function being executed is executed, as shown in FIG. 22, the local sector ID = 1 in the sector ID conversion table 131 is executed in the memory access instruction execution process by the CPU. The cache sector ID corresponding to is referenced, and memory access is executed using the first dedicated cache area assigned to the function being executed.

  By cyclically changing the correspondence as described above, it is possible to easily detect which cache sector ID is assigned to the function being executed. That is, the remainder obtained by dividing the stack depth of the target function by the total number of cache areas in the stack memory cache area group (5 in the examples of FIGS. 31 and 32) becomes the cache sector ID assigned to the target function. . However, the top of the stack memory area is counted as stack depth 0. Accordingly, since the depth of the stack of the function E is 4, the remainder (4/5) = 4, and a dedicated cache area with a cache sector ID = 4 is allocated. This is as shown in FIGS.

  Therefore, when the function is called back, the cache allocation management unit 204 obtains the cache sector ID of the allocated dedicated cache memory from the depth of the stack of the original function by the above calculation, and the local sector ID of the sector ID conversion table. Rewrite the cache sector ID corresponding to = 1. Thereby, the memory access of the function being executed is performed using the dedicated cache area allocated to the function.

[Details of Second Embodiment]
Next, the second embodiment will be described in detail. The configuration shown in FIGS. 1 and 2 is the same in the second embodiment. The relationship between the stack memory and the cache memory is as shown in FIG.

  FIG. 36 is a flowchart showing the compiling step and the target process starting step. First, when the source program activated by the input unit 17 is received (S611), the compiler 21 compiles the source program and converts it into a machine language program (S612). By this compilation, the access instruction to the local variable of each function is converted into a machine language instruction with a local sector ID = 1. Further, the compiled program is executed in the development environment, and the OS cache allocation management unit 204 performs test measurement of the time required for the function call back, the time required for the function call, and the memory access time. The number of cache areas in the cache area group and the aforementioned N (prefetch size 2) and M (prefetch size 1) are calculated (S613).

  Next, when the input unit 17 receives a compiled program start command in the production environment (S614), the OS process management unit 202 starts the target process (S615). At the same time, the cache allocation management unit 204 instructs to secure the number of cache areas for the stack memory by the number of cache areas calculated in advance (S616). In response to this instruction, a stack memory cache area group 130-ST is secured in the cache memory 130 and set in the cache sector information setting unit 132 (S617). Then, the process management unit 202 executes each process of the program (S618). If a function is called or called back during the execution of each process, the process management unit 202 executes function call processing and function call back processing (S618).

  FIG. 37 is a flowchart of the function call back process. FIG. 37 shows a caller function 22-1 and a callee function 22-2. The caller function 22-1 is a function that calls a certain function, and the callee function 22-2 is the called function. The function call back process has been outlined in FIG. 31, but a specific process by the OS will be described below.

  First, in the function call back process, the callee function 22-2 ends the process of the function (S621). In response to this, the function control management unit 201 of the OS executes termination processing of the callee function (S622). Termination processing of the callee function includes saving of registers and tables in the CPU for the function to be terminated. After the callee function termination processing, the cache allocation management unit 204 assigns the free cache area in the stack memory cache area group 130-ST to the dedicated cache area to the function that is one prefetch size 1 (N) before the caller function. The local variable data of the function is prefetched from the stack memory area in the main memory (memory access), and the data is written into the allocated free cache area and expanded (S623). The cache sector ID of this empty cache area is prefetch size 1 (N) before the cache sector ID of the dedicated cache area assigned to the caller function.

  Along with this, in the cache memory 130, local variable data of the function before the prefetch size 1 (N) is written and expanded in the allocated free cache area by the prefetch memory access processing corresponding thereto. However, since this memory access is a process for the main memory, the processing time becomes long. Therefore, the next process is executed without waiting for the completion of the memory access process.

  The cache allocation management unit 204 of the OS updates the sector ID conversion table and changes the cache sector ID corresponding to the local sector ID = 1 to the cache sector ID corresponding to the caller function (S625). That is, as shown at time T2 in FIG.

  Then, the function control management unit 201 of the OS executes a caller function resume process (S626). This restart processing includes setting of registers and tables in the CPU for the function to be restarted. Thereafter, the caller function 22-1 resumes processing (S627). When this caller function resumes processing and executes the local variable access instruction, the local function is already stored in the dedicated cache area in the stack memory cache area group 130-ST already allocated to the caller function in the cache memory 130. Since the variable data is still written, there is no cache miss hit.

  FIG. 38 is a flowchart of the function call process. The function call processing has been outlined with reference to FIG. 32, but the specific processing by the OS will be described below.

  First, in the function call process, the caller function 17 generates a function call (S631). As a result, the callee function is called. In response to this, the function control management unit 201 of the OS temporarily stops the current function and executes a delivery process to the callee function (S632). At this time, the function control management unit 201 allocates the next function free cache area in the stack memory cache area group to the call destination function, and starts memory access to the local variable of the call destination function. Since valid data is not stored in the next function free cache area, the memory access of the local variable of the callee function can be started without saving the original data to the stack memory.

  Then, the cache allocation management unit 204 of the OS starts saving the data of the function in the dedicated cache area 2 (M) before the prefetch size from the call destination function in the stack memory area in the main memory, and for the second function A free cache area is secured (S633). As a result, in the cache memory 130, the local variable data of the function in the dedicated cache area whose prefetch size is 2 (M) before the callee function is saved in the stack memory area, and becomes the second function free cache area. (S634). However, since this save process involves access to the main memory, the processing time becomes long. Therefore, the next process is executed without waiting for the completion of the memory access process.

  The cache allocation management unit 204 of the OS updates the sector ID conversion table and changes the cache sector ID corresponding to the local sector ID = 1 to the cache sector ID corresponding to the call destination function (S635). That is, as shown at time T3 in FIG.

  Then, the function control management unit 201 of the OS executes a call destination function start process (S636). This start processing includes setting of registers and tables in the CPU for the function to be started. Thereafter, the callee function 22-2 starts processing (S637). When this call destination function resumes processing and executes a local variable access instruction, memory access can be started using an empty cache area in which data has already been saved.

  Of the functions called immediately before the caller function, the local variable data of the function prior to the prefetch size 1 (N) before the callee function is saved from the dedicated cache area and the second function free cache Since it is maintained as an area, even if a function call occurs thereafter, memory access of the local variable for that function can be started without saving processing.

  In the second embodiment described above, the cache memory control program stores the first dedicated cache area assigned to the function being executed in the stack memory cache area group 130-ST and the first cache area called immediately before that. The second dedicated cache area assigned to the number 2 (N) functions and the third number (M) dedicated free cache area are maintained.

  However, the cache memory control program stores the first dedicated cache area assigned to the function being executed in the stack memory cache area group 130-ST and the second number (N) of functions called immediately before it. It is also possible to maintain the second dedicated cache area allocated to and not to maintain the dedicated free cache area. However, in this case, when a new function is called, the data in the dedicated cache area of the previously called function must be temporarily saved and then the local variable data of the new function must be accessed in memory. , The time until memory access is delayed.

  As described above, according to the second embodiment, a dedicated cache area is allocated to each subroutine for the stack memory area for storing local variables of subroutines such as functions and modules, and the cache area for the stack memory is allocated. Since the size of the group is maintained at a minimum size, the cache hit rate of memory access to the subroutine local variable is improved while efficiently using the area of the cache memory. Memory access can be started efficiently.

  The above embodiment is summarized as follows.

(Appendix 1)
A processor-readable cache memory control program for causing a processor to execute a cache memory control process,
The cache memory control process includes:
A stack memory cache area group allocating step for allocating a stack memory cache area group having a plurality of cache areas to a stack memory area for a subroutine called in the program;
A plurality of cache areas in the stack memory cache area group are divided into a first dedicated cache area allocated to the first subroutine being executed, and a second number called immediately before the first subroutine. A cache memory control program comprising a cache area allocation step for maintaining a second dedicated cache area allocated to the second subroutine and a third number of free cache areas.

(Appendix 2)
In Appendix 1,
The cache area allocation step includes:
When the first subroutine is finished and a subroutine called immediately before the first subroutine of the second subroutine is started to be executed, the third subroutine called before the second subroutine is started. A cache memory control program for prefetching data in a stack memory area of the third subroutine by allocating the free cache area as a dedicated cache area to a subroutine.

(Appendix 3)
In Appendix 2,
The cache area allocation step includes:
A cache memory control program for maintaining the second number equal to or more than a number obtained by dividing the time required for memory access of data in the stack memory area by the time required for the call-back processing of the subroutine.

(Appendix 4)
In Appendix 1,
The cache area allocation step includes:
When a new fourth subroutine is called while the first subroutine is being executed, the data in the dedicated cache area of the subroutine called the earliest among the second subroutines is saved in the stack memory area. A cache memory control program for allocating a dedicated cache area of the subroutine called earliest to the free cache area.

(Appendix 5)
In Appendix 4,
The cache area allocation step includes:
A cache memory control program that maintains the third number equal to or greater than the number of times required to save the data in the dedicated cache area in the stack memory area divided by the time required for calling the subroutine.

(Appendix 6)
A processor-readable cache memory control program for causing a processor to execute a cache memory control process,
The cache memory control process includes:
A stack memory cache area group allocating step for allocating a stack memory cache area group having a first number of cache areas to a stack memory area for a subroutine called in the program;
A cache area in the stack memory cache area group is allocated as a dedicated cache area to a subroutine called in the program, and the allocated dedicated cache area is assigned to a first subroutine being executed. A cache memory control program having a cache area allocation step for maintaining one dedicated cache area and a second dedicated cache area allocated to one or more second subroutines called immediately before the first subroutine .

(Appendix 7)
In Appendix 6,
The cache area allocation step includes:
A cache memory control program for maintaining cache areas other than the first and second dedicated cache areas in the stack memory cache area group as free cache areas in which valid cache data is not recorded.

(Appendix 8)
A cache memory control method,
A stack memory cache area group allocating step for allocating a stack memory cache area group having a plurality of cache areas to a stack memory area for a subroutine called in the program;
A plurality of cache areas in the stack memory cache area group are divided into a first dedicated cache area allocated to the first subroutine being executed, and a second number called immediately before the first subroutine. A cache memory control method comprising: a cache area allocation step of maintaining a second dedicated cache area allocated to the second subroutine and a third number of free cache areas.

(Appendix 9)
A cache memory control method,
A stack memory cache area group allocating step for allocating a stack memory cache area group having a plurality of cache areas to a stack memory area for a subroutine called in the program;
A cache area in the stack memory cache area group is allocated as a dedicated cache area to a subroutine called in the program, and the allocated dedicated cache area is assigned to a first subroutine being executed. A cache memory control method comprising: a cache area allocating step for maintaining one dedicated cache area and a second dedicated cache area allocated to one or a plurality of second subroutines called immediately before the first subroutine .

(Appendix 10)
A processor with a cache memory,
A stack memory cache area group allocating means for allocating a stack memory cache area group having a plurality of cache areas to a stack memory area for a subroutine called in the program;
A plurality of cache areas in the stack memory cache area group are divided into a first dedicated cache area allocated to the first subroutine being executed, and a second number called immediately before the first subroutine. A processor having cache area allocating means for maintaining in a second dedicated cache area allocated to the second subroutine and a third number of free cache areas.

(Appendix 11)
A processor with a cache memory,
A stack memory cache area group allocating means for allocating a stack memory cache area group having a plurality of cache areas to a stack memory area for a subroutine called in the program;
A cache area in the stack memory cache area group is allocated as a dedicated cache area to a subroutine called in the program, and the allocated dedicated cache area is assigned to a first subroutine being executed. A processor having a cache area allocation means for maintaining one dedicated cache area and a second dedicated cache area allocated to one or more second subroutines called immediately before the first subroutine.

10: Processor unit 12: CPU
13: Cache unit 16: Main memory 20: OS
21: Compiler 22: Application program 130: Cache memory 130_1: Shared cache area 130_2: Dedicated cache area

Claims (10)

A processor-readable cache memory control program for causing a processor to execute a cache memory control process,
The cache memory control process includes:
A stack memory cache area group allocating step for allocating a stack memory cache area group having a plurality of cache areas to a stack memory area for a subroutine called in the program;
A plurality of cache areas in the stack memory cache area group are divided into a first dedicated cache area allocated to the first subroutine being executed, and a second number called immediately before the first subroutine. A cache memory control program comprising a cache area allocation step for maintaining a second dedicated cache area allocated to the second subroutine and a third number of free cache areas. In claim 1,
The cache area allocation step includes:
When the first subroutine is finished and a subroutine called immediately before the first subroutine of the second subroutine is started to be executed, the third subroutine called before the second subroutine is started. A cache memory control program for prefetching data in a stack memory area of the third subroutine by allocating the free cache area as a dedicated cache area to a subroutine. In claim 2,
The cache area allocation step includes:
A cache memory control program for maintaining the second number equal to or more than a number obtained by dividing the time required for memory access of data in the stack memory area by the time required for the call-back processing of the subroutine. In claim 1,
The cache area allocation step includes:
When a new fourth subroutine is called while the first subroutine is being executed, the data in the dedicated cache area of the subroutine called the earliest among the second subroutines is saved in the stack memory area. A cache memory control program for allocating a dedicated cache area of the subroutine called earliest to the free cache area. In claim 4,
The cache area allocation step includes:
A cache memory control program that maintains the third number equal to or greater than the number of times required to save the data in the dedicated cache area in the stack memory area divided by the time required for calling the subroutine. A processor-readable cache memory control program for causing a processor to execute a cache memory control process,
The cache memory control process includes:
A stack memory cache area group allocating step for allocating a stack memory cache area group having a first number of cache areas to a stack memory area for a subroutine called in the program;
A cache area in the stack memory cache area group is allocated as a dedicated cache area to a subroutine called in the program, and the allocated dedicated cache area is assigned to a first subroutine being executed. A cache memory control program having a cache area allocation step for maintaining one dedicated cache area and a second dedicated cache area allocated to one or more second subroutines called immediately before the first subroutine . A cache memory control method,
A stack memory cache area group allocating step for allocating a stack memory cache area group having a plurality of cache areas to a stack memory area for a subroutine called in the program;
A plurality of cache areas in the stack memory cache area group are divided into a first dedicated cache area allocated to the first subroutine being executed, and a second number called immediately before the first subroutine. A cache memory control method comprising: a cache area allocation step of maintaining a second dedicated cache area allocated to the second subroutine and a third number of free cache areas. A cache memory control method,
A stack memory cache area group allocating step for allocating a stack memory cache area group having a plurality of cache areas to a stack memory area for a subroutine called in the program;
A cache area in the stack memory cache area group is allocated as a dedicated cache area to a subroutine called in the program, and the allocated dedicated cache area is assigned to a first subroutine being executed. A cache memory control method comprising: a cache area allocating step for maintaining one dedicated cache area and a second dedicated cache area allocated to one or a plurality of second subroutines called immediately before the first subroutine . A processor with a cache memory,
A stack memory cache area group allocating means for allocating a stack memory cache area group having a plurality of cache areas to a stack memory area for a subroutine called in the program;
A plurality of cache areas in the stack memory cache area group are divided into a first dedicated cache area allocated to the first subroutine being executed, and a second number called immediately before the first subroutine. A processor having cache area allocating means for maintaining in a second dedicated cache area allocated to the second subroutine and a third number of free cache areas. A processor with a cache memory,
A stack memory cache area group allocating means for allocating a stack memory cache area group having a plurality of cache areas to a stack memory area for a subroutine called in the program;
A cache area in the stack memory cache area group is allocated as a dedicated cache area to a subroutine called in the program, and the allocated dedicated cache area is assigned to a first subroutine being executed. A processor having a cache area allocation means for maintaining one dedicated cache area and a second dedicated cache area allocated to one or more second subroutines called immediately before the first subroutine.

Images