JPH05120140A - Cache memory device - Google Patents

Abstract

PURPOSE:To improve the cache hit rate by eliminating such a defective case where the pest useful cache date are driven out of a cache memory as a program runs. CONSTITUTION:The cache memories CM0, CM1 and CM2 are provided with the gates 15, 25 and 35 which the input of the control signals to the directory parts 12, 22 end 32 and the valid bit parts 13, 23 and 33 from the cache control parts 11, 21 and 31 respectively. A stack level control part 16 controls the stack level in response to the subroutine call/return instructions of a program and then outputs the signals 151, 251 and 351 to the gates 15, 25 and 35 corresponding to the controlled stack levels. Thus the part 16 selects the memories CM0, CM1 and CM2 to attain the read mishit processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory device used in an information processing device.

[0002]

2. Description of the Related Art Conventionally, cache memory has been effectively used for the purpose of greatly improving the performance in computer architecture such as shortening the average memory access time. FIG. 4 is a block diagram showing the basic configuration of the cache memory. In the figure, 1 is a cache control unit, 2 is a RAM (directory unit) that holds the upper (MAU) of the main memory address as tag data, and 3 is a RAM (valid bit unit) that holds valid bits,
Reference numeral 4 denotes a RAM (data section) that holds memory data. Further, 101 is lower data (C
A) and 102 are upper data (MA) of the main memory address.
U), 103 are valid bits transferred between the cache control unit 1 and the valid bit unit 3, and 104 is tag data transferred between the cache control unit 1 and the directory unit 2. Further, 105 is a control signal sent from the cache control unit 1 to the directory unit 2 and the valid bit unit 3, which becomes active when writing to the directory unit 2 and the valid bit unit 3. 106
Is a control signal sent from the cache control unit 1 to the data unit 4, and becomes active when writing to the data unit 4. 107 is bus data.

Here, the directory portion 2 is arranged such that when the signal 105 is inactive, the lower data 10 of the main memory address
The tag data 104 designated by 1 is output to the cache control unit 1, and when the signal 105 is active, the high-order data 102 of the main memory address given by the cache control unit 1 is input and written in the CA address, and at the same time, in the CA address. Set the valid bit. Further, the data section 4 writes the bus data 107 in the CA address when the signal 106 is active.

FIG. 5 is a diagram showing the relationship between the main memory address and the cache row address. As shown in the figure,
Bits 0 to m in the main memory address MA are the cache row address CA, and bits m + 1 to n are treated as tag data. In addition,
m is determined by the cachet capacity.

Next, the operation of this cache memory will be described.

First, the memory read operation will be described with reference to FIG. In the figure, (1) is the data flow at the time of a read miss, and (2) is the data flow at the time of a read hit. When the central processing unit CP starts a memory read at the main memory address MA of the main memory MM, the cache control unit 1 of the cache memory CM causes the main memory address M to be read.
Based on the cache row address CA of A, the tag data and the valid bit are read from the directory section 2 and the valid bit section 3, and this tag data is compared with the high order (MAU) of the main memory address MA. As a result, if the read mishit, that is, the mismatch or the valid bit read from the directory unit 2 is in the reset state even if the data match, the data "AAAA" at the address MA in the main memory MM is set to 1 by the read request from the central processing unit CP.
The word is read and the read buffer R in the central processing unit CP is read.
B is set to the CA address of the data portion 4 of the cache memory CM. At the same time, the higher address (MAU) of the main memory address is set as the tag data in the CA address of the directory unit 2 and the valid bit is set in the CA address of the valid bit unit 3.

If the read hit, that is, the tag data read from the cache memory CM and the upper (MAU) of the main memory address match and the valid bit is set, the cache control unit 1 starts from the CA address of the data unit 4. The data "AAAAA" is read and set in the read buffer RB in the central processing unit CP.

Next, the memory write operation will be described with reference to FIG. In the figure, (1) is the data flow at the time of a write miss hit, and (2) is the data flow at the time of a write hit. When the central processing unit CP starts the memory write at the main memory address MA of the main memory MM, the cache control unit 1 of the cache memory CM causes the tag data read from the directory unit 2 and the higher order of the main memory address MA as described above. Compare with (MAU). As a result, in the case of a write miss hit, the data "BBBB" in the write buffer WB is written to the address MA of the main memory MM in response to a write request from the central processing unit CP.

In the case of a write hit, the data "CCCC" of the write buffer WB in the central processing unit CP is written in the CA address of the data section 4 of the cache memory CM, and the high order of the main memory address is set in the CA address of the directory section 2. Write (MAU). Also, for the main memory MM, the data "CCC" of the write buffer WR is placed at the address MA
C ″ is written.

In this example, one level is taken as an example for the sake of simplicity, but it seems that the two level / 4 level system is actually common. Further, if the multi-level system is used, each cache memory can be assumed to be the multi-level system.

However, in such a cache memory, if, for example, the A module calls the B module in a program and the B module uses a large amount of memory data, some or all of the cache data loaded by the A module is cached. There is a problem that the cache hit rate drops significantly when the process is returned to the A module because it has been evicted from the memory.

[0012]

SUMMARY OF THE INVENTION The present invention is intended to solve such a problem and prevents the useful cached data of the past from being expelled from the cache memory each time the program progresses, thus improving the cache hit rate. It is an object of the present invention to provide a cache memory device capable of achieving the above.

[0013]

In order to achieve the above object, the cache memory device of the present invention increases or decreases the stack level according to a plurality of cache memories corresponding to the stack level and a subroutine call / return instruction of the program. A stack level control means for managing and controlling so that only the cache memory corresponding to this stack level is in a read mishit processable state.

[0014]

In the cache memory device of the present invention, the stack level control means is a subroutine call / program
The stack level is increased or decreased according to the return instruction, and the cache data corresponding to the current stack level is controlled to be in the read mishit processable state, so that the cache data of each stack level is written in a separate cache memory. .. This prevents the cache data of another stack level from being expelled from the cache memory by the memory access of the program of a certain stack level, and the cache hit rate can be improved.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a cache memory device according to an embodiment of the present invention.

In the figure, 11, 21, and 31 are cache control units, 12, 22, and 32 are RAMs (directory units) that hold upper (MAU) of main memory addresses as tag data, and 13, 23, and 33 are valid. RAM for holding bits (valid bit part), 14, 24, 34
Is a RAM (data section) that holds memory data.
Further, reference numerals 15, 25, and 35 are cache control units 11 and 21,
A gate for switching the input of the control signal from 31 to the directory units 12, 22, 32 and the valid bit units 13, 23, 33, 16 increases and decreases the stack level according to the subroutine call / return instruction of the program,
The stack level control unit outputs signals 151, 251, 351 to the gates 15, 25, 35 corresponding to the stack level. As described above, the cache memory device of this embodiment includes a plurality of cache memory sets (in this example, the first to third cache memories CM0, CM1, and CM2).
Is configured.

Further, 111 is the lower data (CA) of the main memory address, 112 is the upper data (MAU) of the main memory address, and 113 is the cache control units 11, 21, and 3.
1 is a valid bit transferred between 1 and the valid bit units 13, 23 and 33, 114 is the cache control unit 11,
It is the tag data transferred between 21, 31 and the directory sections 12, 22, 32. Further, 115 is from the cache control units 11, 21, 31 to the directory units 12, 2
2 and 32 and the above-mentioned control signals sent to the valid bit units 13, 23 and 33, which are active when writing to the directory units 12, 22, 32 and the valid bit units 13, 23 and 33 during read mishit processing. Become. Further, 116 is the cache control units 11, 21, and 3.
1 is a control signal output to the data units 14, 24 and 34, and becomes active when writing to the data units 14, 24 and 34. And 117 is bus data.

Next, the operation of the cache memory device will be described with reference to FIGS. 2 is a diagram showing the relationship between the flow of the program and the stack level. As shown in the figure, the stack level is controlled by the stack level control unit 16 to be “0” when the main module is executed, “1” when the sub module 1 called from the main module is executed, and the sub module 1 from the sub module 1. When the called sub-module 2 is executed, it is set to "2" respectively. FIG. 3 shows changes in the states of the cache memories CM0, CM1, and CM2 along the program flow shown in FIG.

First, when the central processing unit (not shown) processes the main module shown in FIG. 2, the stack level control unit 16 sets the stack level to "0". Then, the signal 151 from the stack level control unit 16 to the gate 15 of the first cache memory CM0 becomes active, the gate 15 is closed, and the cache control unit 11
Control signal 115 is input to the directory unit 12 and the valid bit unit 13. As a result, the read mishit processing in the first cache memory CM0 becomes possible. During this period, another cache memory CM
The gates 25 and 35 of 1 and CM2 are still in the open state, and the read mishit processing is not performed in these cache memories CM1 and CM2. Thereafter, the read mishit processing is performed in the first cache memory CM0, so that the data in the area A of the main memory (not shown) is loaded into the first cache memory CM0 (FIG. 3-a).

Next, when the sub module 1 is called by the subroutine call instruction from the main module, the stack level control unit 16 counts up the stack level to "1". Then, from the stack level control unit 16 to the gate 2 of the second cache memory CM1.
The signal 251 to 5 becomes active, the gate 25 is closed, and the read mishit process of the second cache memory CM1 becomes possible. After that, when the read mishit processing is performed in the same manner, the second cache memory CM1
The data in area B of the main memory is loaded into (Fig. 3
-B).

Next, when the submodule 1 is called from the submodule 1, the stack level is counted up to "2", the signal 351 is similarly activated, and the third cache memory CM2 becomes in the read mishit processable state. .. Then, by performing the read mishit processing, the data in the area C of the main memory is loaded into the third cache memory CM2 (FIG. 3C).

After that, when returning to the sub-module 1 by the return instruction, the stack level is counted down to "1", and the second cache memory CM1 becomes ready for read mishit processing again. However, FIG.
As shown in, B used in submodule 1 at this time
Since the data in the area remains in the second cache memory CM1, it is possible to avoid the situation where the same data must be loaded again from the main memory.

Similarly, when returning to the main module by a subsequent return instruction, as shown in FIG. 3-e, the A used in the main module for the first cache memory CM0 is also used.
It is not necessary to load the same data because the area data remains.

Although the operation at the time of read miss hit has been described above, other control at the time of read hit and write is not related to the stack level control unit 16, and all the cache memories CM0, CM1 and CM2 function and perform processing. Is done.

Thus, according to the cache memory device of this embodiment, the stack level is increased / decreased in accordance with the subroutine call / return instruction of the program, and only the cache memory corresponding to the stack level is set to the read mishit processable state, and each stack is processed. Level cache data is stored in separate cache memories CM0, CM1, CM
By writing to 2, it is possible to avoid the situation where the memory access of the program of a certain stack level causes the cache data of another stack level to be expelled, and the cache hit rate can be improved.

Although the cache memory level (different from the stack level) is set to "1" in this embodiment, each cache memory has a multi-level (FIFO / L) level.
Control by a replacement algorithm such as the RU method). That is, the present invention does not need to limit the method of each cache memory, and has an advantage that the degree of freedom of the circuit configuration is high.

Further, in the level control by the LRU method or the like, there is a problem that the control logic greatly increases as the number of levels increases, but since the control is simple in the present invention, the number of levels can be increased without increasing the control logic. It also has the effect of saying. Therefore, as a means of increasing the cache hit rate, rather than increasing the number of levels only with the multi-level method,
The method of increasing the number of levels by combining the cache memory of the multi-level method with the method according to the present invention is more effective in terms of cost performance. Further, in this embodiment, the stack level is increased / decreased according to the subroutine call / return instruction of the program, but the stack level is increased / decreased at a specific break (for example, task or module) in the program. Good.

[0029]

As described above, according to the cache memory device of the present invention, only the cache memory corresponding to the stack level is set in the read mishit processable state, so that a memory access of a program at a certain stack level causes another stack to be processed. It is possible to avoid the situation where the cache data of the level is evicted from the cache memory, and as a result, the cache hit rate can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a cache memory device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between a program flow and a stack level.

3 is a diagram showing changes in the state of each cache memory along the flow of the program shown in FIG.

FIG. 4 is a block diagram showing a basic configuration of a cache memory.

FIG. 5 is a diagram showing a relationship between a main memory address and a cache row address.

FIG. 6 is a diagram for explaining a memory read operation in a conventional cache memory.

FIG. 7 is a diagram for explaining a memory write operation in a conventional cache memory.

[Explanation of symbols]

11, 21, 31 ... Cache control unit, 12, 22, 3
2 ... Directory part, 13, 23, 33 ... Valid bit part, 14, 24, 34 ... Data part, 15, 25, 35
... gate, 16 ... stack level control unit, CM0, CM
1, CM2 ... Cache memory.

Claims (1)

[Claims] 1. A plurality of cache memories corresponding to a stack level, and a stack level is increased / decreased and managed according to a subroutine call / return instruction of a program, and only the cache memory corresponding to the stack level becomes a read mishit processable state. And a stack level control means for performing such control.