JP3360902B2 - Semiconductor storage device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device. In particular, when this semiconductor memory device is built in a semiconductor device such as a microcomputer, its advantages are greatly utilized. Of course, this semiconductor memory device can be used as an external memory device without being built in a semiconductor device such as a microcomputer.

[0002]

2. Description of the Related Art FIG. 7 shows a conventional S having a data width of 8 bits, 256 bytes or 2048 bits, which is one of semiconductor memory devices built in a microcomputer or the like.
1 shows a schematic configuration of a RAM (static random access memory). In this figure, the memory cell array 1 has 8-bit memory cells in one array and is composed of 8 × 32 arrays. Address signals A7 to A3 of higher 5 bits from the address bus are supplied to the row address decoder 3. The output of the row address decoder 3 is supplied via the gate means 4 to eight arrays of rows of the memory cell array 1 (for example, A7 to A3 = 00).
When 001, the arrays C7-1, C6-1, ...
, C2-1, C1-1). In addition, address signals A2 to A0 of lower 3 bits from the address bus
Are supplied to the column address decoder 21, and the column address decoder 21 selects a column of the memory cell array 1, that is, a 1-bit memory cell of 8 bits in each array.

When data is read from the memory cell array 1, a read data signal from the array selected by the row address decoder 3 passes through the input / output circuit 22, is further selected by the column address decoder 21, and passes through the data input / output buffer 8. Are transmitted to the data buses D7 to D0.

When writing data to the memory cell array 1,
Write data signals from the data buses D7 to D0 are supplied to the input / output circuit 22 via the data input / output buffer 8.
Row address decoder 3 and column address decoder 21
It is written in the memory cell selected by and.

A data input / output buffer 8, an input / output circuit 22, and a gate means 4 are controlled by the control circuit 9 from three signals of read permission OE, write permission WE and chip selection CS.
A signal is generated to control the.

When the chip selection signal CS is logic "1", the memory cell can be read / written, and when it is logic "0", the read permission OE and the write permission WE are ignored and the read / write cannot be performed. .

When the read enable signal OE is logic "1",
For the input / output circuit 22 and the data input / output buffer 8, the control signals RD1, RD2 and WLE for reading are set to logic "1". When the logic is "0", the control signals RD1 and R
D2 remains logical "0".

When the write enable signal WE is logic "1",
The control signals WR1, WR2 and WLE for writing to the input / output circuit 22 and the data input / output buffer 8 are set to logic "1". When the logic is "0", the control signals WR1 and W
R2 remains logical "0".

Read enable signal OE and write enable signal W
When E is logic "0", the control signal WLE remains logic "0".

The control signal WLE is a word line enable signal and is input to the gate means 4 inserted between the row address decoder 3 and the memory cell array 1 to control the output of the row address decoder 3.

The control signals RD1 and WR1 are applied to the input / output circuit 2
2 and controls the transfer of read / write data between the memory cell array 1 and the input / output circuit 22. Control signal R
D2 and WR2 are input to the data input / output buffer 8,
This controls the transfer of read / write data between the data bus and the input / output circuit 22.

When data is read from the memory cell array 1 in the above structure, the address signals A7 to A0 are first set to the addresses of the memory cells to be read. Next, the chip selection signal CS and the read enable signal O
E is set to logic "1" (write enable signal WE is set to logic "0"). As a result, the address signal A
The read data signal from the memory cell selected by 7 to A0 is sent to the data buses D7 to D0 via the input / output circuit 22 and the data input / output buffer 8. When writing data to the memory cell array 1, first, the address signals A7 to A0 are set to the addresses of the memory cells to be written. Next, the chip selection signal CS and the write enable signal W
E is set to logic "1" (read enable signal OE is set to logic "0"). As a result, the data bus D7
A write data signal is supplied to the bit line from D0 to D0 via the data input / output buffer 8 and the input / output circuit 22, and is written in the memory cell selected by the address signals A7 to A0.

A conventional semiconductor memory device built in a microcomputer or the like has a method of performing access (read / write) with a fixed data width (8 bits in the RAM of the conventional example).

By the way, in such a semiconductor memory device, it is sometimes desired to access data in a specific range (hereinafter referred to as a bit field). However, as described above, in the conventional semiconductor memory device, since the data width of access is fixed, the bit field access is artificially performed by a special instruction or a combination of a plurality of instructions.

In the case of a low-level microcomputer, access to a bit field is realized by a read / modify / write by a special instruction or a combination of a plurality of instructions. However, this read modify
Write is a process that temporarily reads (reads) all bits of data including the bit field that is the target of rewriting, modifies the read data only in the target bit field (modify), and modifies the processed data. All bits are written (write), which requires 3 steps even in a schematic manner, and there is a problem in processing speed.

Therefore, a high-order microcomputer having a bit field operation instruction in which the speed of the read / modify / write instruction is improved was also made, but in order to realize this bit field operation instruction, a barrel shifter (a bit field to be operated) A huge circuit such as a high-speed shift circuit used for extracting a signal is required in the central processing unit (hereinafter abbreviated as CPU) section, which is very expensive.

[0017]

As described above, the conventional semiconductor memory device built in the microcomputer or the like is
When accessing a bit field, there are problems such as a decrease in processing speed or an increase in circuit scale in the CPU section.

The present invention has been made in view of the above problems of the prior art. An object of the present invention is to provide a semiconductor memory device capable of accessing a bit field by a mode signal such as an address. is there.

[0019]

A semiconductor memory device according to the present invention is divided into N bit fields, and a row address signal from an address bus and a memory cell array which is accessible for this bit field are decoded. , A row address decoding means for outputting the row decode signal, a column address signal for decoding the column address signal from the address bus, and a column address decoding means for outputting the column decode signal, and a mode address signal from the address bus A mode address decoding means for outputting the mode decode signal, and an access terminal inserted in a row decode signal transmission line from the row address decode means and selected at least one of the bit fields of the memory cell array by the mode decode signal. A row decode gate means being opened and closed controlled according to the target bit field, wherein the bit positions and the data width of the accessed bit field by the mode address signal is variable.

Further, the semiconductor memory device of the present invention is divided into 1-bit units, and is accessible from a memory cell array accessible from a bit field having a minimum 1-bit width and a maximum M-bit width, and an address bus. Row address decoding means for decoding the row address signal and outputting the row decode signal, column address decoding means for decoding the column address signal from the address bus and outputting the column decode signal, and the address bus A mode address decoding means for decoding the mode address signal and outputting the mode decoding signal, and a row decoding signal transmission line from the row address decoding means, which is inserted into a bit field of the memory cell array by the mode decoding signal. at least One and a row decode gate means being opened and closed controlled in accordance with the selected access target bit field, wherein the bit positions and the data width of the accessed bit field by the mode address signal is variable.

The read data selecting means is inserted into the read data signal transmission line from the memory cell array to the data bus for every one or more bits in the data bus, and one bit of the memory cell array is in accordance with the mode address signal. It can be constituted by a selection circuit which selectively outputs a read data signal from a field and a read data signal from a bit field of the memory cell array or a specific data signal.

The write data selecting means is inserted into the write data signal transmission path from the data bus to the memory cell array for every one or more bits in the data bus, and one bit of the data bus is in accordance with the mode address signal. It can be constituted by a selection circuit which selectively outputs the write data signal from the field and the write data signal from the other bit field of the data bus.

[0023]

According to the present invention, the mode decode signal indicating the bit position and the data width of the bit field to be accessed is applied to the row decode gate means for gated the row decode signal to access the bit field to be accessed in the memory cell array. By activating (selecting), it is possible to access in a bit field unit by the mode address signal. As a result, when accessing the bit field, it is not necessary to sacrifice the speed side and increase the circuit scale of the CPU section unlike the conventional read-modify-write and bit-field operation instructions. It becomes possible to perform high-speed bit field access even with a microcomputer or the like. Even in the semiconductor memory device according to the present invention, if the entire data width of the memory cell array is set to the mode to be accessed by the mode address signal, the conventional read / modify / write or bit field operation instruction is executed. It is possible to do that.

[0024]

1 shows the structure of a semiconductor memory device according to a first embodiment of the present invention. This drawing shows a case where the memory cell array 1 is divided into an upper memory cell array 1M that stores upper 4-bit data and a lower memory cell array 1L that stores lower 4-bit data. The input / output circuit 22 is also divided into two, an upper input / output circuit 22M connected to the upper memory cell array 1M and a lower input / output circuit 22L connected to the lower memory cell array 1L. The lower 3 bits A2 to A0 (column address signal) of the address bus are input to the column address decoder 21, and the middle 5 bits A7 to A3 (row address signal) of the address bus are input to the row address decoder 3. .

Gate circuits 4M and 4M are provided between the row address decoder 3 and the memory cell arrays 1M and 1L, respectively.
L is inserted, and the gate circuits 4M and 4L control the enable / disable of the row decode signal from the row address decoder 3 by the word line enable signal WLE and the mode decode signals m2 and m1 described later.

Next, the read / write circuit of the data input / output buffer will be described. As shown in FIGS. 3 and 4, the data read circuit includes read data selection means (hereinafter referred to as selectors) 5M and 5L and a tri-state buffer 10.
It is composed of M and 10L. The selector 5M is a selector for reading the upper 4 bits of the data bus,
According to the input signal to the selection signal input terminal S, the signals of the 4-bit data input terminals A and B are output from the data output terminal Y.
Which is selectively output (when the S input is logic "0", the A input signal is output to Y, and when the S input is logic "1", the B input signal is output. )
Then, the data input terminal A is grounded and fixed to "0000" data (it is not always required to be "0000").
The output data of the input / output circuit 22M is connected to the data input terminal B, and the mode control signal m3 is input to the selection signal input terminal S. The input of the tri-state buffer 10M is connected to the data output terminal Y of the selector 5M, and the output of the tri-state buffer 10M is connected to the upper 4 bits D7 to D4 of the data bus. The tri-state buffer 10M is on / off controlled by a read control signal RD2.

The selector 5L is used for the upper memory cell array 1
It is for switching read data signals from M and the lower memory cell array 1L and outputting them to the lower 4 bits D3 to D0 of the data bus, and inputs the data signals to the 4-bit data input terminals A and B, respectively. It is selectively output to the data output terminal Y according to the input signal to the terminal S. The output data signal of the input / output circuit 22M connected to the upper memory cell array 1M is input to the data input terminal A, and the data input terminal B is input. The output data signal of the input / output circuit 22L connected to the lower memory cell array 1L is input, and the mode decode signal m1 is input to the selection signal input terminal S. The input to the tristate buffer 10L is connected to the data output terminal Y of the selector 5L, and the output of the tristate buffer 10L is the lower 4 bits of the data bus.
It is connected to bits D3 to D0. The tri-state buffer 10L is turned on / off by the read control signal RD2.
It will be controlled off.

The data write circuit comprises write data selection means (hereinafter referred to as selector) 6 and tristate buffer 1.
It is composed of 1M and 11L. The selector 6 is for switching write data to the upper 4-bit memory cell array 1M, and outputs the data signals of the 4-bit data input terminals A and B according to the input signal to the selection signal input terminal S. Output to the data input terminal A, the lower 4 bits D of the data bus
The write data signal from 3 to D0 is input, the write data signal from the upper 4 bits D7 to D4 of the data bus is input to the data input terminal B, and the mode decode signal m1 is input to the selection signal input terminal S. ing. The data output terminal Y of this selector 6 is the tri-state buffer 1
Tri-state buffer 11M connected to 1M input
Is connected to the input / output circuit 22M. The tristate buffer 11M is ON / OFF controlled by the write control signal WR2.

The tristate buffer 11L is for writing to the memory cell array 1L of lower 4 bits, its input is connected to the lower 4 bits D3 to D0 of the data bus, and the output of the tristate buffer 11L is input / output. It is connected to the circuit 22L. The tristate buffer 11L is on / off controlled by a write control signal WR2.

In this embodiment, three types of bit fields at the time of reading / writing can be used: 8 bits, upper 4 bits and lower 4 bits. In the circuit having the above structure, access control of the bit field at the time of reading and writing is performed by the mode decode signals m3, m2 and m1, and a circuit for generating these mode decode signals, that is, a mode address decoding means. The upper 2 bits A9 and A8 (mode address signal) of the address bus are input to a (hereinafter referred to as mode address decoder) 7 and read / write respectively depending on a combination of logical levels of the address signals in these upper 2 bits A9 and A8. The access control of three types of bit fields is performed for. The tables are summarized in Tables 1 and 2 below.
Here, the read / write bit field is the upper 4
Memory cell array 1 with 4 bits or lower 4 bits
When accessing M and 1L, the read / write data signal is input and output through the lower 4 bits D3 to D0 of the data bus, and the mode decode signals m3, m2 and m1 perform such operation. Selectors 5M, 5L, 6 and tri-state buffers 10M, 1
Control of 0L, 11M, 11L is performed. The mode address decoder 7 is configured as shown in FIG. 2, for example. That is, the inverter gates 71 and 72 and the AND gate 7
3 and the bit A9 is provided to the inverter gate 71.
Address, and the address signal of bit A8 is input to the inverter gate 72, and both inverter gates 7
The outputs of 1, 72 are input to the AND gate 73. As a result, the output of the inverter gate 71 is used as the mode decode signal m1, the output of the inverter gate 72 is used as the mode decode signal m2, and the output of the AND gate 73 is used as the mode decode signal m3.

[0031]

[Table 1]

[0032]

[Table 2] That is, in the case of the 8-bit mode of Table 1, all the control signals to the gate circuits 4M and 4L, the selectors 5M and 5L and the tri-state buffers 10M and 10L are logic "1", and in the case of the lower 4-bit mode. When the control signals to the gate circuit 4M and the selector 5M are logic "0", the gate circuit 4L, the selector 5L and the tri-state buffer 10
When the control signal to M and 10L becomes logic "1", and in the higher 4-bit mode, the gate circuit 4L and the selector 5
The control signal to M and 5L is logic "0", and the gate circuit 4M
Also, the control signals to the tri-state buffers 10M and 10L are controlled to be logic "1".

In the case of the 8-bit mode shown in Table 2, all the control signals to the gate circuits 4M and 4L, the selector 6 and the tri-state buffers 11H and 11L are logic "1",
In the lower 4-bit mode, the control signal to the gate circuit 4H is logic "0" and the control signals to the gate circuit 4L, the selector 6 and the tri-state buffers 11H and 11L are logic "1", and the higher 4-bit mode is used. In the case of, the control signal to the gate circuit 4L and the selector 6 becomes logic "0", and the gate circuit 4M and the tri-state buffer 11
The control signals to M and 11L are all controlled to be logic "1".

The operation of each mode shown in the table will be described below. [1] Operation at the time of reading shown in Table 1 (8-bit mode) Since the mode address signals A9 and A8 of the address bus are both logic "0", the input signal m1 to the gate circuit 4L and the input to the gate circuit 4M are input. The signal m2 becomes logic "1" and the word line selection enable signal W
The gate circuits 4L and 4M are in the open state while LE is logic "1". Therefore, the output signal of the row address decoder 3 is valid for both the upper 4-bit side and the lower 4-bit side of the memory cell array 1.

Next, since the address signals A9 and A8 are both logic "0", the mode decode signal m3 becomes logic "1", and the selector 5M selectively outputs the read data signal di from the input / output circuit 22M. Become. Further, the selector 5L is in a state of selectively outputting the read data signal dj from the input / output circuit 22L connected to the side of the memory cell array 1L because the signal m1 described above has the logic "1".

Then, the tri-state buffer 10M,
The read control signal RD2 of 10L is turned on by the logic "1".

Therefore, the read data signal from the memory cell at the address designated by the row address decoder 3 and the column address decoder 21 of the memory cell array 1 is transmitted through the input / output circuits 22M and 22L and the selectors 5M and 5L to the tristate buffer 10M. , 10L to the data bus. (Lower 4 bit mode) Since the mode address signal A9 of the address bus is logic "0", the mode decode signal m1 to the gate circuit 4L is logic "1" and the word line enable signal WLE is logic "1". , Gate circuit 4
L is in an open state. On the other hand, since the address signal A8 is logic "1", the mode decode signal m2 to the gate circuit 4M is logic "0", and the gate circuit 4M is closed. Therefore, the output signal of the row address decoder 3 is valid only for the memory cell array 1L.

Next, the logical "0" output from the inverter gate 71 causes the output m3 of the AND gate 73 to become a logical "0", and the selector 5M outputs the data signal "0000".
Is selected and output.

The selector 5L is an inverter gate 7
Input / output circuit 22L according to logic "1" output from 2
The data signal from is output.

Then, the tri-state buffer 10M,
The read control signal RD2 of 10L is turned on by the logic "1".

Therefore, the data signal of the memory cell array 1L at the address designated by the row address decoder 3 and the column address decoder 21 is transmitted from the tri-state buffer 8L via the input / output circuit 22L and the selector 5L to the lower bits D3 to D0 of the data bus. Will be output to. At this time, the data signal "0000" is sent from the selector 5M to the upper 4 bits D7 to D4 of the data bus via the tri-state buffer 8M. Therefore, in the lower 4-bit mode, only the data signal from the lower 4-bit memory cell array 1L is read. (Higher 4-bit mode) Since the mode address signal A9 of the address bus is logic "1", the inverter gate 7
The output m1 of 2 becomes logic "0", and the gate circuit 4L is closed. Since the address signal A8 is logic "0", the output m2 of the inverter gate 71 is logic "1" and the gate circuit 4M is in an open state. Therefore, the output address signal of the row address decoder 3 is valid only on the upper side with respect to the memory cell array 1M.

Next, the output "m3" of the AND gate 73 becomes logic "0" by the logic "0" output from the inverter gate 72, and the selector 5L outputs the data signal "000".
The state is such that "0" is selectively output.

The selector 5L is an inverter gate 7
According to the logic "0" output from 2, the data signal from the input / output circuit 22M is selectively output.

Then, the tri-state buffer 10M,
The read control signal RD2 of 10L is turned on by the logic "1".

Therefore, the data signal of the memory cell array 1M at the address designated by the row address decoder 3 and the column address decoder 21 is passed through the input / output circuit 22M and the selector 5M and the tri-state buffer 10L.
To the lower 4 bits D3 to D0 of the data bus. At this time, the data signal “000” is output from the selector 5M via the tri-state buffer 10M.
0 "is sent to the upper 4 bits D7 to D4 of the data bus. Therefore, in this mode, only the data from the upper 4 bits of the memory cell array 1M is read. [2] Write shown in Table 2 Operation (8-bit mode) Since the mode address signals A9 and A8 of the address bus are both logic "0", the input signal m1 to the gate circuit 4L and the input signal m2 to the gate circuit 4M are logic "1". , Word line enable signal WLF
However, the "logic" gate circuits 4M and 4L are open. AND gate 4L because the gate A8 is also a logical "0"
Will also be open. Therefore, the row address decoder 3
Output signal is valid for both the upper 4 bits and lower 4 bits of the memory cell array 1.

Next, the mode address signal A9 of the address bus becomes the selection control signal m1 logic "1" of the selector 6 by the logic "0", and the selector 6 writes from the upper 4 bits D7 to D4 of the data bus. Outputs data. The tristate buffers 11M and 11L are turned on because the control signal WR2 has a logic "1". Therefore, the data bus D7 is connected to the upper memory cell array 1M.
The data of the data buses D3 to D0 are written in the lower memory cell array 1L. (Lower 4 bit mode) Since the mode address signal A8 of the address bus is logic "1", the mode decode signal m2 is logic "0" and the gate circuit 4M is in a closed state. Since the address signal A9 is a logical "0", the mode decode signal m1 is a logical "1", and the gate circuit 4L is in the period in which the word line enable signal WLE is a logical "1".
Is open. Therefore, the row device decoder 3
Output signal is valid only on the lower side of the memory cell array 1L.

Further, the tri-state buffer 11L is turned on because the write control signal WR2 becomes logic "1". Therefore, the data bus D3 is included in the memory cell array 1L.
The data of ~ D0 will be written. On the other hand, since the gate circuit 4M is closed, the data in the memory cell array 1M is retained. (Upper 4-bit mode) Since the mode address signal A8 of the address bus is logic "0", the mode decode signal m2 becomes logic "1", and the word line enable signal WLE
The gate circuit 4M is in the open state during the period of logic "1". Since the address signal A9 is logic "1", the input signal m1 to the gate circuit 4L becomes logic "0", and the gate circuit 4L is in a closed state. Therefore, the output signal of the row address decoder 3 is valid only on the upper side of the memory cell array 1M.

As described above, since the mode decode signal m1 has a logic "0", the selector 6 is in a state of selectively outputting the write data signal from the lower 4 bits D3 to D0 of the data bus. Since the write control signal WR2 becomes the logic "1", the tri-state buffer 11M is turned on, and the data of the lower bit lines D3 to D0 of the data bus is written in the upper memory cell array 1M. On the other hand, since the gate circuit 4L is closed, the data in the memory cell array 1L is retained.

As described above, according to this embodiment, the row address gate circuit which gates the row address decode signal by the mode decode signal obtained by decoding the mode address signal indicating the bit position and the data width of the bit field to be accessed. And activates only the bit field to be accessed in the memory cell array, and controls the connection between the data bus and the memory cell array by the read data selecting means and the write data selecting means which are selectively controlled by the mode decode signal. Therefore, the bit field variable operation can be performed by the mode address signal. As a result, when accessing the bit field, it is not necessary to sacrifice the speed side as in the conventional read modify write instruction or the bit field operation instruction, and it is not necessary to increase the circuit scale of the CPU section. It is also possible to easily realize the conventional high-speed bit field access function.

FIG. 5 shows the structure of a semiconductor memory device according to the second embodiment of the present invention. As shown in this figure, the memory cell array 1 is divided into a set of three bit fields, and a set 1M of the upper 3 bit arrays C7 to C5 is formed.
M, set of medium 3-bit arrays C4 to C2 1LM, lower 2
Gate 4 circuits MM, 4LM, and 4LL are provided for the set 1LL of the bit arrays C1 and C0, respectively. Further, a column address decoder 2 is commonly used for each group 1MM, 1LM, 1LL.
1 is provided, and input / output circuits 22MM, 22LM, 22LL are provided opposite to each set 1MM, 1LM, 1LL. The input / output circuits 22MM, 22LM, 22LL are input / output controlled by the read control signal RD1 and the write control signal WR1 from the control circuit 9, and are connected to the bits D7-D0 of the data bus via the input / output buffer 8. . The read control signal R from the control circuit 9 is applied to the input / output buffer 8.
Input / output is controlled by D2 and the write control signal WR2 and the mode control signals m1, m2, ... From the mode address decoder 7.

According to the present embodiment, unlike the first embodiment in that the memory cell array 1 is divided into three parts, the control circuit system also operates in accordance therewith, but an operation equivalent to that of the first embodiment. It goes without saying that the effect is exhibited.

FIG. 6 shows the structure of an 8-bit data width 256-byte RAM according to the third embodiment of the present invention. In this figure, first, the memory cell array 1
Is divided into 1-bit array, minimum 1 bit, maximum 8
It is possible to access a bit field of bits. Accordingly, the address signal on the address bus includes a mode address indicating a bit field to be accessed in addition to the row address and the column address.

Gate circuits 47 to 40 are provided for the array of each bit field in the memory cell array 1, and the row decode signal from the row address decoder 3 is supplied to the memory cell array via the gate circuits 47 to 40. It has become so. The column address decoder 21 is provided commonly to all the arrays, and the input / output circuits 227 to 220 are divided and arranged corresponding to the arrays of each bit field.

The mode decode signal of the mode address decoder 7 is a signal of at least 8 bits corresponding to the number of divisions of the memory cell array 1. That is, at least 8 bits are required to control the opening / closing of each of the gate circuits 47 to 40, and the selective output control in the input / output buffers 87 to 80 described later is performed by the number of combinations of each array and each data bus line. If it is done, the number is not limited to eight types, that is, it may be more, so
The mode control signal has at least 8 bits.
Each bit m8 to m1 of this mode decode signal corresponds to each array C7 to C0 of the memory cell array 1 and is supplied to the gate circuits 47 to 40 of each array C7 to C0.
It is designed to open and close them.

Reference numerals 87 to 80 are data input / output buffers including selectors for read data signals and write data signals as many as the number of combinations of each array and each data bus bit as described above. Therefore, all arrays C7
Read data signals from C0 to C0 are input to the respective data input / output buffers 87 to 80, and the corresponding data buses D
Since it is designed to input to 7 to D0, each array C
The read data signal from 7-C0 can be sent to any bit D7-D0 on the data bus. Further, since the data signals of all the bits D7 to D0 of the data bus are input to the data input / output buffers 87 to 80, the write data signals to the respective arrays C7 to C0 are input to the arbitrary arrays C7 to C0 in the memory cell array 1. Can be sent out.

The operation of the RAM of this embodiment will be described below. First, the outline will be described. The bit field to be accessed is changed by the control of the mode address signal. That is, the row address in which the memory cell to be accessed in the memory cell array 1 exists is set by the row address signal, and the column address is also set by the column address signal. However, only those address signals specify the entire 8 bits. Is the same as. The mode address signal specifies which bit of the entire 8 bits is to be accessed,
By opening the mode address signal corresponding to the bit to be accessed among the gate circuits 47 to 40, the bit to be accessed out of the entire 8 bits designated by the row address signal and the column address signal. Only the field is activated.

In the third or fourth aspect of the invention, the mode address signal also serves to specify the bit of the data buses D7 to D0 to which the read data signal is sent. Therefore, by controlling this mode address signal, the read data signal from the bit field of the same row column address of the memory cell array 1 can be output to any field bit of the data buses D7 to D0. Similarly, in writing, the mode address signal plays a role of designating the bit field to be the input destination of the write data signal in the bit field of the memory cell array 1, and the same bit of the data bus is controlled by controlling the mode address signal. The write data signal from the field can be supplied to any bit field of the memory cell array 1.

Here, for example, it is assumed that the read mode is set and the mode address signal portion is set so that all bit fields are read access targets, and naturally all bits of the data bus are output destinations. Then, the gate circuits 47 to 40 are all opened by the mode decode signal from the mode address decoder 7, and the row address decode signal from the row address decoder 3 is transmitted to all the arrays C7 to C.
The data is read from the memory cells which are supplied to 0 and activated by the column address decode signal from the column address decoder 21 in all the arrays C7 to C0.

Similarly, it is assumed that the mode is set to the write mode, and the mode address signal portion is set so that all bit fields are write access targets, and naturally all bits of the data bus are input destinations. All the gate circuits 47 to 40 are opened by the mode decode signal from the mode address decoder 7, and the row decode signal from the row address decoder 3 is supplied to all the arrays C7 to C0.
Data is written to the memory cells activated by the column decode signal from the column address decoder 21 in 7 to C0.

Next, the lower 4 in the memory cell array 1
A bit field of bits is to be accessed, and the lower 4 bit lines D3 to D of the data bus
It is assumed that the read mode is set so that the data is sent to 0. As a result, the mode control signal from the mode address decoder 7 opens the gate circuits 43 to 40 and closes the gate circuits 47 to 44, so that the row address decode signal from the row address decoder 3 is in the lower 4 order.
The data of the memory cells which are supplied to the bit arrays C3 to C0 and activated by the column decode signal from the column address decoder 21 in the lower four bit arrays C3 to C0 are read. At this time,
According to the mode decode signal, the input / output buffer 87 is bit D7, the input / output buffer 86 is bit D6, the input / output buffer 85 is bit D5, the input / output buffer 84 is bit D4, the input / output buffer 83 is bit D3, and the input / output buffer 82 is Bit D2, input / output buffer 81 is bit D
1. The input / output buffer 80 outputs each read data signal to the bit D0 from the corresponding array of the memory cell array 1. Data signals are output to all the bits of the data bus, but the upper 4-bit array in the memory cell array 1 is not activated, so the signals to the upper 4-bits D7 to D4 of the data bus have no substantial meaning. . Further, as described above, it is possible to set all the upper 4 bits to the logical "0" by the read data selecting means.

Similarly, when the write mode is set to the bit field of the lower 4 bits, the gate circuits 43 to 40 are opened by the mode decode signal from the mode address decoder 7, and the row decode signal from the row address decoder 3 is set to the lower 4 bits. Data is written into the memory cells activated by the column address decode signal from the column address decoder 21 in the arrays C3 to C0. At this time, the mode decode signal causes the input / output buffer 8 to
7 is bit D7 of the data bus, I / O buffer 86 is bit D6, I / O buffer 85 is bit line D5, I / O buffer 84 is bit D4, I / O buffer 83 is bit D3, I / O buffer 82 is bit D2, and I / O buffer 82 is bit D2. The output buffer 81 receives the write data signal from the bit D1 and the input / output buffer 80 receives the write data signal from the bit D0.
It is designed to be input to C0. However, since the upper 4-bit arrays C7 to C4 are inactive by the gate circuits 47 to 44, no data is written to these arrays C7 to C4.

[0062]

As described above, according to the present invention, the row decode signal is applied to the row address gate circuit which gates the row decode signal by the mode address signal indicating the bit position and the data width of the bit field to be accessed, and the memory cell array of the memory cell array is provided. Only the bit field to be accessed is activated, and the connection between the data bus and the memory cell array is controlled by the read data selection means and the write data selection means that are selectively controlled by the mode address signal. A bit field change operation can be performed by the mode address signal.
As a result, when accessing the bit field, the speed is sacrificed like the conventional read modify write instruction and the bit field operation instruction, and the CPU
It is possible to install the high-speed bit field access function, which was limited to high-end models, without having to increase the circuit scale of the unit.

Even in the semiconductor memory device according to the present invention, if the entire data width of the memory cell array is set to the mode to be accessed by the mode address signal,
It is possible to execute the read modify write instruction and the bit field operation instruction itself.

[Brief description of drawings]

FIG. 1 is a block diagram of an 8-bit / 256-byte data width RAM as a semiconductor memory device according to a first embodiment of the present invention.

2 is a block diagram showing an example of an internal logical configuration of a mode address decoder shown in FIG.

FIG. 3 is a block diagram showing a higher-side configuration example of the data input / output buffer shown in FIG.

FIG. 4 is a block diagram showing a lower-side configuration example of the data input / output buffer shown in FIG.

FIG. 5 is a block diagram of an 8-bit / 256-byte data width RAM as a semiconductor memory device according to a second embodiment of the present invention.

FIG. 6 is a block diagram of an 8-bit / 256-byte data width RAM as a semiconductor memory device according to a third embodiment of the present invention.

FIG. 7: Conventional data width 8 bits / 256 bytes RAM
Block diagram of.

8 is a block diagram showing a 1-bit configuration of the data input / output buffer shown in FIG. 7. FIG.

[Explanation of symbols]

1 memory cell array 21 column address decoder 22 input / output circuit 3 row address decoders 47-40, 4MM, 4LM, 4LL, 4M, 4L row decode signal gate circuit 7 mode address decoder 8 data input / output buffer 9 control circuits C7-C0 array D7 ~ D0 data bus m1, m2, ... Mode decode signal

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-2-177192 (JP, A) JP-A-5-234368 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G11C 11/413 G11C 11/401

Claims (4)

(57) [Claims] 1. A memory cell array which is divided into N (N is an integer of 2 or more) bit fields and which can be accessed for this bit field, and a row address signal from an address bus is decoded, and the row decoding is performed. A row address decoding unit for outputting a signal, a column address signal for decoding the column address signal from the address bus, and a column address decoding unit for outputting the column decode signal, and a mode address signal from the address bus for decoding the mode A mode address decoding means for outputting a signal, and an access target bit field inserted in a row decoding signal transmission line from the row address decoding means and selected at least one of the bit fields of the memory cell array by the mode decoding signal. A semiconductor memory device comprising: a row decode gate circuit which is controlled to open / close according to a mode, and a bit position and a data width of the access target bit field are variable according to the mode address signal. 2. A memory cell array which is divided for each bit and which can be accessed for a bit field having a minimum 1-bit width and a maximum M (M is an integer of 2 bits or more) bit width, and an address. A row address decoding means for decoding a row address signal from the bus and outputting the row decode signal; a column address decoding means for decoding a column address signal from the address bus and outputting the column decode signal; A mode address decoding means for decoding a mode address signal from the bus and outputting the mode decoding signal, and a mode decoding part of the bit field of the memory cell array inserted in the row decoding signal transmission line from the row address decoding means. At least one by signal Row decode gate means which is controlled to open / close in accordance with one selected access target bit field, and the bit position and data width of the access target bit field can be changed by the mode address signal. apparatus. 3. A bit field of one or more bits in a data bus, which is inserted into a read data signal transmission line from the memory cell array to the data bus, and which is one bit field of the memory cell array according to the mode address signal. 3. The semiconductor memory device according to claim 1, further comprising read data selection means for selectively outputting a read data signal from the device or a specific data signal. 4. A bit field of one or more bits in a data bus, which is inserted into a write data signal transmission line from the data bus to the memory cell array, and which is one bit field of the memory cell array according to the mode address signal. 4. The semiconductor memory according to claim 1, further comprising write data selection means for selectively outputting a write data signal to the memory cell array and a write data signal to another bit field of the memory cell array. apparatus.