JPH05173927A - Address extension control system - Google Patents

Abstract

PURPOSE:To extend the address without changing an address bus in the address extension control system where an address area larger than the bus width of the address bus is accessed. CONSTITUTION:Plural packages 1-1 to 1-n are mutually connected by a bus 5, and each of these packages is provided with an address register 6, and an upper address signal transferred through a data bus 2 is set to the address register 6 designated by the address signal on an address bus 3, and the address area is accessed with the address signal where this upper address signal and a lower address signal transferred through the address bus 3 are combined.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address extension control system for accessing an address area having a bus width larger than that of an address bus. In a system in which multiple packages with various functions are mounted and interconnected by a bus,
One of the plurality of registers in the package is designated by the address signal transferred via the address bus, and control is performed to set the data transferred via the data bus or to send the set data to the data bus. .. It is desirable to have a larger number of registers in the package in such systems.

[0002]

2. Description of the Related Art A system constructed by mounting a plurality of packages has, for example, a configuration as shown in FIG. 4 and carries out input / output processing of the packages 31-1 to 31-4.
If four of the two IO packages are provided, they are connected to the common control unit package (not shown) via the bus 35. The bus 35 includes a data bus 32, an address bus 33, and a control bus 34, and each package 31-1 to 31 is selected by a selection control line corresponding to the package in the control bus 34.
-4 is specified and 16 registers RG1 to RG16 are provided in each of the packages 31-1 to 31-4, the register RGi (i = 1 to 1) is generated by an address signal from the address bus 33 having a 4-bit width. 16) is designated and, for example, data transferred via the 8-bit wide data bus 32 is set by a write signal.
Alternatively, 8-bit data of the designated register RGi is sent to the data bus 32 by a read signal.

[0003]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention In a system constructed by mounting a plurality of packages, it is desired to provide a larger number of registers in order to enhance the function. In this case, for example, if the address bus 33 has a width of 4 bits, 16 registers can be designated per package. Therefore, by mounting a larger number of packages, the number of registers as a system can be increased. be able to. However, since the number of control lines of the control bus 34 is limited and the mounting space is also limited, there is a limit in increasing the number of packages to be mounted and the number of registers. Although it is conceivable to widen the bus width of the address bus 33, it is often difficult to realize because there are restrictions on the number of pins of the connector for connecting the package and the bus. The present invention aims to extend addresses without changing the address bus.

[0004]

The address extension control system of the present invention will be described with reference to FIG. 1. A plurality of packages 1-1 to 1-n are connected to a data bus 2, an address bus 3, and a control bus 4. And an address register 6 for setting a higher-order address signal in each of the packages 1-1 to 1-n, and the address register 6 designated by the address signal from the address bus 3 is provided.
A high-order address signal transferred via the data bus 2 is set, and the high-order address signal set in the address register 6 and the low-order address signal transferred via the address bus 3 To access.

[0005]

The address register 6 is designated by the address signal from the address bus 3, and the upper address signal transferred via the data bus 2 is set in the address register 6. Next, by transferring the lower-order address signal through the address bus 3 to form a pair with the higher-order address signal set in the address register 6, as compared with the case where only the address signal from the address bus 3 is used, A very large number of registers can be selected and specified.

[0006]

FIG. 2 is a block diagram of the essential parts of an embodiment of the present invention. 12 is a data bus, 13 is an address bus, 14 is a control bus, 15 is a bus, 16 is an address register, and 17 is an address register.
Is a decoder, 18 is a gate circuit, 19 is an inverter, 2
Reference numeral 0 is a random access memory that constitutes a register. Similar to the system shown in FIG. 4 above, the data bus 1
2 is 8 bits wide, address bus 13 is 4 bits wide,
The random access memory 20 shows a case where 128 register units which are accessed by a 7-bit address signal of A _{6 to} A ₃ upper address signals and A _{2 to} A ₀ lower address signals are configured. ..

Address signals A _{3 to} A ₀ = “000” for designating the address register 16 are supplied to the address bus 13.
1 ", and data D _{7 to} D ₀ =“ 00 ”on the data bus 12.
When you transfer "000000" to "00001111,"
Decoder 17 address signal A ₃ ~A ₀ = "0001"
Is decoded, an enable signal is added to the enable terminal EN of the address register 16, and the lower 4-bit data D ₃ to 8 of the 8-bit data on the data bus 12 are decoded.
By adding D ₀ = “0000” to “1111” to the input terminals IN _{1 to} IN ₄ of the address register 16 and adding a write signal by the read / write control line in the control bus 14 to the select terminal CS, in the address register 16, D ₃ in the data _{D 7 ~D 0 ~D 0 = "} 000
0 "~" 1111 "is set. 4 bits from the address register 16 becomes the high-order address signal A ₆ to A ₃ of the random access memory 20.

Next, the address signals A _{3 to} A ₀ = “1000” to “1111” are transferred to the address bus 13. The gate circuit 18 outputs the inputs of the input terminals IN _{3 to} IN ₁ as valid when “0” is input to the terminal G, and therefore, the upper bit A _{3 of the} address signals A _{3 to} A ₀ is “. 1 ", the remaining 3 bits A _{2 to} A
₀ indicates the gate circuit 18 to the random access memory 20.
To the lower address signals A _{2 to} A ₀ . At that time, when a read / write signal indicating the writing of “0” is applied to the read / write terminal RW and 8-bit data D _{7 to} D ₀ are transferred to the data bus 12, the data D ₇ to
D ₀ is written in the register section designated by the address signal composed of the upper address signals A _{6 to} A ₃ and the lower address signals A _{2 to} A ₀ . When a read / write signal indicating "1" read is applied to the read / write terminal RW, the data in the register section designated by the address signal is sent to the data bus 12. That is, in the case of the address bus 12 having a 4-bit width, only 16 registers could be designated, but in the case of the above-mentioned embodiment,
It is possible to specify 128 register units configured in the random access memory 20 without changing the address bus 12.

When the upper address signals A _{6 to} A ₃ are not changed and only the lower address signals A _{2 to} A ₀ are changed to access the other register units, the address register 1 is used.
The process of setting the upper address signal to 6 can be omitted. That is, even if the address signal is divided into the upper address signal and the lower address signal, in the case where the register portion is continuously selected, the access can be performed at high speed as in the case where the address signal is not divided.

FIG. 3 is an explanatory diagram of the extended address. The address is shown in hexadecimal notation, the bank is based on the upper address signal, and the output buffer register OB is based on the lower address signal.
Corresponding to R, the lower address signals A _{2 to} A ₀ have a 3-bit structure, so that eight output buffer registers OBR indicated by 0 to 7 are designated, and the upper address signals A _{6 to} A ₃ are designated. Has a 4-bit structure, 16 banks represented by 0 to F can be designated. Therefore, as consecutive addresses, 0 to 12 indicated by 000 to 07F
It will be number 8.

As described above, 128 per package
If the number of registers can be provided, the present function is sufficient. However, if a larger number of registers are provided, since the data bus 12 has an 8-bit width, the upper address signal can be 5 bits or more. It would be good. Also, the case where 3 bits A _{2 to} A ₀ of the 4-bit address signals A _{3 to} A ₀ by the address bus 13 are used as lower address signals is shown. Since 0001 "is used, the control is simplified by not using the address signal whose upper bit A ₃ is" 0 "as the lower address signal. If necessary, the upper bit A ₃ is An address signal of "0" can also be used.

[0012]

As described above, according to the present invention, the upper address signal is set to the address register 6 provided in the plurality of packages 1-1 to 1-n via the data bus 2 and the upper address is set. Since a register in a package is designated by an address signal that is a combination of a signal and a lower address signal via the address bus 3, a large number of registers are provided in the package without changing the address bus 3. It becomes possible. Therefore, since it is not necessary to increase the number of packages mounted, there is an advantage that the function of the system can be economically enhanced without increasing the size.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram of an essential part of an embodiment of the present invention.

FIG. 3 is an explanatory diagram of extended addresses.

FIG. 4 is an explanatory diagram of a system.

[Explanation of symbols]

 1-1 to 1-n package 2 data bus 3 address bus 4 control bus 5 bus 6 address register

Claims (1)

[Claims] 1. A plurality of packages (1-1 to 1-n)
In a system in which a bus (5) composed of a data bus (2), an address bus (3) and a control bus (4) is connected to the plurality of packages (1-1 to 1-n), An address register (6) for setting an address signal is provided, and an upper address transferred via the data bus (2) to the address register (5) specified by the address signal from the address bus (3). An address characterized by setting a signal and accessing by an address signal consisting of an upper address signal set in the address register (6) and a lower address signal transferred through the address bus (3). Extended control method.