JPH03223950A - Bus conversion circuit - Google Patents

Abstract

PURPOSE:To secure the connection between the data bus of an external input/ output device and an entire system data bus by providing a means which secures the connection with switching between the data bus of the external input/output device having a half-bit constitution compared with the system data bus and a higher or lower rank system data bus based on a data bus selection signal. CONSTITUTION:The lower rank bits of a system data bus are corresponding to the even addresses with the higher rank bits corresponding to the odd addresses respectively. Thus a data bus selection signal showing a lower rank bit is outputted concurrently with output of an even address of a CPU 1 with a data bus selection signal showing a higher rank bit outputted concurrently with output of an odd address of the CPU 1 respectively when data are read or written. Then a bus conversion circuit 31 connects the data bus of an external input/output device to a lower rank bit of the system bus when the data bus selection signal shows a lower rank bit and then connects the data bus to a higher rank bit of the system bus when the data bus selection signal shows a higher rank bit respectively. Thus a higher or lower rank bit of the data bus can be used.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a computer system in which a data bus is divided into two systems, upper bits and lower bits, and more specifically, a computer system in which a data bus is divided into two systems, upper bits and lower bits. The present invention relates to a bus conversion circuit applied to a computer system in which either the upper bit or the lower bit of the bus is used.

[Conventional technology]

For example, in a computer system using an Intel 8086 series 16-bit central processing unit (CP IJ),
Either the upper 8 bits or the lower 8 bits of the 16-bit data bus are selected depending on whether the address value is even or odd. Therefore, when accessing an external input/output device with a 16-bit data structure, addressing is performed twice, one for an even number and one for an odd number. For example, lower 8 bits of data are read or written at even addresses, and upper 8 bits of data are read or written at odd addresses.

Incidentally, it often happens that it is desired to apply an 8-bit external input/output device to a computer system using such a 16-bit CPU, and in that case, the devices are generally connected as shown in FIG. In the figure, 1 is a 16-bit CPU, 2 is a main memory, 3 is an 8-bit external input/output device, 4 is a 16-bit system data bus, 5 is an address bus, and 9 is a control bus. The main memory 2 is connected to the system data bus 4 via two 8-bit memory data buses 6.7. That is, the memory data bus 6 corresponds to the upper bits of the system data bus 4, and the memory data bus 7 corresponds to the lower bits. Then, when an even address is specified, the memory data bus 6
The lower 8 bits of data are written or read through the 8 bits, and when an odd address is specified, the upper 8 bits of data are written or read.

A data bus 8 of the external input/output device 3 is connected to the upper eight bits of the system data bus 4.

[Problem to be Solved by the Invention] As described above, in this computer system, the data bus 8 of the external input/output device 3 is connected to the upper 8 of the system data bus 4.
Since it is connected only to bits, the external input/output device 3 can only be accessed using odd addresses. Therefore, the memory areas corresponding to even-numbered addresses in the main memory 2 are completely wasted. This problem occurs even if the data bus 8 of the external input/output device 3 is connected to the lower 8 bits of the system data bus 4. It happens even if you change it.

An object of the present invention is to solve these problems.

[Means to solve the problem]

The bus conversion circuit of the present invention has been made to solve the above-mentioned problems, and is a data bus selection circuit that indicates whether the upper or lower system data bus output from the central processing unit of a computer system is to be used. The device is equipped with a switching means for connecting a data bus of an external input/output device having a bit configuration half that of the system data bus to either an upper or lower data bus of the system data bus, based on a signal.

[Effect]

To simplify the explanation, it is assumed that the lower bits of the system data bus correspond to even addresses and the upper bits correspond to odd addresses. When reading or writing data, when an even address is output from the central processing unit, a data bus selection signal indicating the lower bit is simultaneously generated, and when an odd address is output, a data bus selection signal indicating the upper bit is generated. is output. The switching means connects the data bus of the external input/output device to the lower bits of the system bus if the data bus selection signal indicates the lower bits, and connects the data bus of the external input/output device to the upper bits of the system bus if the data bus selection signal indicates the upper bits.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of the present invention,
FIG. 2 is a block diagram showing an example of application of the circuit of this embodiment. The terminal 11 is a terminal connected to the upper 8-bit data bus 5DA8-15 of the 16-bit system data bus 4, and is a set of eight terminals, although not shown. Similarly, the terminal 12 is a terminal connected to the lower 8 bit data bus 5DAO-7 of the system data bus 4.

On the other hand, the terminal 24 is a terminal connected to the 8-bit data bus DAO-7 (numeral 33 in FIG. 3) of the external input/output device 3.

The multiplexer circuits 18 and 19 are circuits that switchably connect the Y terminal to either the A terminal or the S terminal, and switching of the connection is controlled by a signal applied to the S terminal. Here, the S terminal is selected when the signal applied to the S terminal is at high level, and the A terminal is selected when the signal is at low level.

Reference numbers 14.16 and 23 are 3-tristate buffer circuits, 15.17 and 22 are buffer circuits,
20 and 21 are negative logic AND circuits. Further, the terminals 25 to 28 are connected to the control bus 9,
Terminal 25 has CPU read permission signal RD, terminal 26 has C.
The upper data bus selection signal BHE is applied to the PU write permission signal WR1 terminal 27 and the external access signal TE11 terminal 28, respectively.

Next, the operation of this embodiment will be explained with reference to the waveform diagrams of FIGS. 3 and 4.

First, the CPU reading operation will be explained using the waveform diagram in FIG. In interval T1, the 8-bit data "2A" read from the external input/output device 3 via the data bus DAO-7 is sent to the A terminal of the multiplexer circuit 18 and the 3-tristate buffer via the terminal 24 and the buffer circuit 22. It is applied to the input terminal of circuit 16. At this time, the upper data bus selection signal BHE applied to the S terminal of the multiplexer circuit 18 is at a high level indicating the selection of the lower data bus corresponding to an even number address, so the multiplexer circuit 18 inputs the S terminal to the Y connected to the terminal. Therefore, the 8-bit data "2A" applied to the A terminal cannot pass through the muffler multiplexer circuit 18. On the other hand, the control terminal of the 3-tri-state buffer circuit 16 is given an AND signal of the read permission signal RD and the external access signal C8 from the negative logic AND circuit 20, and the 3-tri-state buffer circuit 16 is activated. ing. Therefore, 8
The bit data "2A" passes through the 3-try state buffer 7 circuit 16 and is further applied to the lower 8 bit data bus 5DAO-7 of the system data bus 4 via the terminal 12. That is, the CPUI reads the 8-bit data "2A" from the external input/output device 3 as the lower 8-bit data corresponding to the even address.

In section T2, data bus D is connected from external input/output device 3.
8-bit data “2A” read via AO-7
The signal is also applied to the A terminal of the multiplexer circuit 18 and the input terminal of the 3-tristate buffer circuit 16 via the terminal 24 and the balancer circuit 22. However, this time, the upper data bus selection signal BHE is at a low level, which means selection of the upper data bus corresponding to the odd address.
In the multiplexer circuit 18, the A terminal is connected to the Y terminal, and the 8-bit data "2A" passes through the multiplexer circuit 18. Then, an AND signal of the read permission signal RD and the external access signal C8 is applied from the negative logic AND circuit 20 to each control terminal of the 3-tristate buffer circuits 14 and 1.6.

Therefore, 8-bit data "2A" is applied to both upper data bus 5DA8-15 and lower data bus 5DAO-7. At this time, upper data bus selection signal B
As you can see that HE is at low level, the CPU
For I, only the data on the upper data bus is valid. That is, the CPU has read the 8-bit data "2A" from the external input/output device 3 in the interval T2 as the upper 8 bits corresponding to the odd address of the 16-bit data.

In this way, the 8-bit data from the external input/output device 3 can be read both as upper 8 bits corresponding to odd addresses and as lower 8 bits corresponding to even addresses.

Next, the CPU write operation will be explained using the waveform diagram shown in FIG. In interval T3, the lower 8-bit data "2A" given from the CPU via the lower data bus 5DAO-7 is sent to the S terminal of the multiplexer circuit 19 via the terminal 12 and the buffer circuit 17, and also to the upper data bus 5DAO-7. The upper 8 bits of data "3B" given through -15 are given to the A terminal of the multiplexer circuit 19 via the terminal 11 and the buffer circuit 15, respectively. At this time, the upper data bus selection signal BHE is
Since this is a high level indicating selection of the lower data bus corresponding to an even address, the multiplexer circuit 19 selects S
The terminal is connected to the Y terminal. Therefore, from the Y terminal of the multiplexer circuit 19, the lower 8-bit data “2
A" is output. Then, the logical product signal of the write permission signal WR and the external access signal C8 is applied from the negative logic AND circuit 21 to the control terminal of the 3-tristate buffer circuit 23, and the lower 8-bit data "2A" is transferred to the data bus D.
Given to AO-7. That is, writing of the lower 8 bits of data corresponding to the even address to the external input/output device 3 is achieved.

In section T4, the upper data bus selection signal BHE becomes low level indicating selection of the upper data bus, and the A terminal of the multiplexer circuit 19 is connected to the Y terminal. Therefore, this time, the upper 8 bit data from terminal 11 “3B
'' is applied to the data bus DAO-7 via the multiplexer circuit 19 and the 3-tristate buffer circuit 23.

That is, writing of the upper 8 bits of data corresponding to the odd address to the external input/output device 3 is achieved.

Note that although this embodiment is based on a 16-bit computer system, the number of bits is not limited to this. In other words, it is applicable regardless of the number of bits, as long as all the bits of the system data bus are divided into two systems, upper and lower, and one system corresponds to odd addresses and the other system corresponds to even addresses. can do.

〔Effect of the invention〕

As explained above, if the bus conversion circuit of the present invention is used,
Add an external input/output device with half the bit configuration of the system data bus to a computer system in which the system data bus is divided into two systems, upper bits and lower bits, and the bus system used differs depending on whether the address is even or odd. In doing so, the data bus of the external input/output device can be connected to substantially the entire system data bus.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram showing an application example of this embodiment, FIGS. 3 and 4 are timing charts showing the operation of this embodiment, and FIG. FIG. 5 is a block diagram showing the prior art. 1... Central processing unit (CPU), 2... Main memory, 3... External input/output device, 13... System data 2 Bus side terminal, 14.16.23... 3 tri-state buffer circuit, 15.17.22...buffer circuit,
18.19...Multiplexer circuit, 20.21...
- Negative logic AND circuit, 24... External input/output device data bus side terminal, 25-28... Control signal input terminal, 31
...Bus conversion circuit.

Claims (1)

[Claims] A bus converter connected to the system data bus of a computer system in which all bits of the system data bus are divided into two data buses, upper and lower, and one system corresponds to odd addresses and the other system corresponds to even addresses. a bit configuration of half of the system data bus based on a data bus selection signal output from the central processing unit of the computer system and indicating which system, upper or lower, is to be used; A bus converting circuit comprising means for switching and connecting a data bus of an external input/output device having a data bus to either an upper or lower data bus of the system data bus.