JPH04256053A - Computer device - Google Patents

Abstract

PURPOSE:To make the change of software unnecessary in the case that a central control device selects a peripheral input/output device necessitating recovery time by providing a circuit to renounce the bus control right of the central control device for a definite period. CONSTITUTION:At the time when a CPU 1 accesses the peripheral input/output device 4, an address signal 5 and signals 8,9 are outputted. A decoder 3 decodes the address signal 5, and in the case of coincidence, it outputs the signal 13, and a control circuit 2 receives the signals 8, 9, 13, and outputs a hold signal 6 to the CPU 1, and counts a clock 15 by a counter in it. The hold signal is held until the counter counts a definite number. Since the control circuit 2 to hold the CPU 1 for a definite period so as to secure the peripheral input/ output device 4 in this way is provided, the recovery time need not be considered in the software.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a computer device having a central processing unit and peripheral input/output devices, and particularly when the central processing unit accesses peripheral input/output devices that require a pause period (hereinafter referred to as recovery time). The present invention relates to a computer device equipped with a control means.

0002

2. Description of the Related Art A conventional computer device will be described with reference to FIGS. 7 to 9.

FIG. 7 is a block diagram of a conventional computer device. As shown in FIG. 7, a conventional computer device includes a central processing unit (CPU) 1, a decoder 3 that decodes an ADDR signal from an address bus 5 connected to the central processing unit 1, and a decoder 3 connected to the central processing unit 1. It has a peripheral input/output device 4 that exchanges DATA signals with a data bus 12. This central processing unit 1
has a bus hold function that relinquishes control of the bus, and has an input terminal for the HLDRQ inverted signal 6 that enables the hold function, and an HL signal that indicates that the hold function is in operation.
It has an output terminal for a DAK inversion signal 7, an output terminal for a BCYST inversion signal 8 indicating the start of a bus cycle, and an output terminal for an ADDR signal 5 which is the address of the central processing unit 1. The bus cycle of the central processing unit 1 is two clock cycles, the T1 cycle and the T2 cycle. The output terminal of signal 9 and the output terminal of R/W inversion signal 10, which distinguishes whether the activated bus cycle is a read cycle or a write cycle, and the data to be input/output have become valid. The output terminal of the DA inverted signal 11 indicating that the
It has an input/output terminal for an ATA signal 12 and an input terminal for a reference clock CLK signal 15 for operating the central processing unit 1. On the other hand, the peripheral input/output device 4 receives an input terminal of an IOSEL inverted signal 13 that recognizes that it has been selected, and an R/W inverted signal that recognizes whether the operation requested of the peripheral input/output device 4 is a read operation or a write operation. 10 input terminals,
It has an input terminal for the DA inverted signal 11 that recognizes that the data bus 12 is active, and has a recovery terminal.
Time is needed. Furthermore, the decoder 3 uses the ADDR signal 5 output from the central processing unit 1 to
It has a function of outputting an IOSEL inverted signal 13 for selecting the MRQ inverted signal 9, and has an input terminal for a DECEN inverted signal 14 that controls permission/disapproval of the decoding operation from the MRQ inverted signal 9 via an inverter 31.

FIG. 8 is a timing diagram of each part of the apparatus in FIG. As shown in FIG. 8, the ADDR signal 5 is output from the central processing unit 1 during the T1 cycle and the T2 cycle, so the BCYST inversion signal 8 becomes active during the T1 cycle. Further, the MRQ inversion signal 9 becomes inactive when the central processing unit 1 accesses the peripheral input/output device 4, becomes active when accessing the memory device, and is output during the T1 cycle and the T2 cycle. Furthermore, the R/W inversion signal 10 becomes "H" when the central processing unit 1 performs a read operation, becomes "L" when the central processing unit 1 performs a write operation, and is output during the T1 cycle and the T2 cycle. Further, the DA inversion signal 11 becomes active when the data signal 13 becomes valid, and is output during the T2 cycle. On the other hand, D.A.
The TA signal 12 is sampled at the rising edge of the cycle following the T2 cycle when the central processing unit 1 performs a read operation, and is output in synchronization with the falling edge of the clock in the T1 cycle when the central processing unit 1 performs a write operation.

FIG. 9 is an operational flow diagram for explaining the operation of the CPU shown in FIG. As shown in FIG. 9, the central processing unit 1 uses peripheral input/output devices 4 that require recovery time.
When accessing , the central processing unit 1 first makes the MRQ inversion signal 9 inactive by executing the IN command, and outputs the address of the peripheral input/output device 4 from the ADDR signal 5 terminal, then the IOSEL of the decoder 3 is inverted. The signal 13 selects the peripheral input/output device 4, and the central processing unit 1 accesses the peripheral input/output device 4. Next, the central processing unit 1 immediately executes the NOP instruction, occupies the bus for fetching the NOP instruction, controls the MRQ inversion signal 9 to active, and inputs the IOSEL inversion signal 13 output by the decoder 3. Activate. In short, the conventional computer system secures the period during which the IOSEL inversion signal 13 is inactive as the recovery time of the peripheral input/output device 4.

[0006]

The conventional computer system described above secures the recovery time of peripheral input/output devices by software instructions of the central processing unit. Therefore, when trying to improve the performance of the entire computer system by increasing the performance of the central processing unit, particularly by increasing the operating clock frequency of the central processing unit, the time for one instruction cycle becomes shorter. Therefore, with the conventional number of instruction steps, sufficient recovery time for peripheral input/output devices cannot be ensured, and software assets cannot be reused.

For example, if the central processing unit operates with a 10 MHz clock signal and the recovery time required for the peripheral input device is 400 nS, when the program with the flow shown in FIG. Two bus cycles are activated to ensure recovery time. However, the operating clock of the central processing unit is
When increasing the frequency to 0 MHz, the time required for a bus cycle for two NOP instructions using the conventional control method would be 200 nS, and as a result, recovery time for peripheral input/output devices could not be secured, so the software had to be changed to replace the NOP instructions. 2
I have to add one thing.

An object of the present invention is to provide a computer device that can reuse past software assets without changing the software.

[0009]

[Means for Solving the Problems] A computer device of the present invention has a bus hold function for relinquishing control of a bus and an address signal output function, and has a hold request signal output function for enabling the hold function. Requires a central processing unit equipped with an input terminal and an output terminal for a hold acknowledge signal indicating that the hold function is operating, and a recovery time as a pause period in which access is not possible for a certain period of time once accessed. A peripheral input/output device having a peripheral input/output device, and a control device such that once the central processing unit accesses the peripheral input/output device, the central processing unit relinquishes the bus control right to reduce the recovery time necessary for the peripheral input/output device. and a control circuit that automatically secures and continuously prevents the central processing unit from accessing the peripheral input/output devices.

0010

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a computer device showing a first embodiment of the present invention, FIG. 2 is a block diagram of a control circuit shown in FIG. 1, and FIG. 3 is a timing diagram of signals of various parts of the device in FIG. It is. As shown in FIGS. 1 to 3, in this embodiment, a central processing unit (CPU) 1, a decoder 3 connected to an address bus 5, and a data bus 12 based on signals from the CPU 1 and the decoder 3 are connected. It has a peripheral input/output device 4 that exchanges data, and a control circuit 2 that is connected to the CPU 1 and controls the decoder 3. Of these, the central processing unit 1 and the peripheral input/output device 4 are the same as those described in the prior art example. The control circuit 2 in this embodiment differs from the conventional example in that the HLDAK inverted signal 7 and
BCYST inversion signal 8, MRQ inversion signal 9, IOS
By inputting the EL inverted signal 13, the HLDRQ
Creates an inverted signal 6 and a DECEN inverted signal 14 and sends it to the CPU.
1 and decoder 3 to ensure recovery time for peripheral input/output device 4. This HLDRQ inverted signal 6 is CP
It is sampled by U1 at the rising edge of the clock in the T2 cycle, the hold function is activated, and the TH cycle is executed. Further, the HLDAK inversion signal 7 becomes active at the falling edge of the clock of the first TH cycle. Further, the HLDRQ inverted signal 6 is sampled at the rising edge of the clock in the TH cycle, and if it is inactive, the LDAK inverted signal 7 becomes inactive at the falling edge of the clock in the TH cycle.

Next, when the CPU 1 accesses the peripheral input/output device 4, the ADDR signal 5, the BCYST inverted signal 8, and the MRQ inverted signal 9 are first output. As a result, the control circuit 2 outputs the MRQ to the internal NAND gate 22.
The inverted signal 9 is input and the DECEN inverted signal 14 for enabling the decoder 3 is activated. In addition, since the hold function is not operating at this time, HLDAK
The inverted signal 7 is "H". On the other hand, decoder 3 is a CPU
The ADDR signal 5 outputted by the circuit 1 is decoded, and if the decoding conditions are met, the IOSEL inversion signal 13 is activated and transmitted to the peripheral input/output device 4, and the control circuit 2
I will also tell you. The control circuit 2 receives this IOSEL inverted signal 1.
3 to the NOR gate 21, and the BCYST inverted signal 8
The RS flip-flop (F/F
) Create a signal to reset 17. HL requests the CPU1 to perform a hold operation using this reset signal.
DRQ inversion signal 6 is output from RSF/F17. The CPU 1 samples this HLDRQ inverted signal 6 at the rising edge of the T2 cycle, operates the bus hold function if it is active, and relinquishes control of the bus in synchronization with the rising edge of the next TH cycle clock. The HLDAK inverted signal 7 is output in synchronization with the falling edge of the clock.

Furthermore, when the HLDRQ inversion signal 6 becomes active, the Q inversion output 24 of the RSF/F 17 is connected to an AND gate that controls the clock input of the counter 16, which has the function of activating the OVF signal 23 when the count overflows. 18 and enables the count clock input to counter 16. When the counter 16 finishes counting for the recovery time required for the peripheral input/output device 4, it activates the OVF signal 23. This OVF signal 23 and HLDAK inversion signal 7
is inverted by the inverter 20 and the AND gate 1
9, creates a signal to set RSF/F17, and makes the HLDRQ inversion signal 6 inactive. As described above, by holding the central processing unit (CPU) 1 for a certain period of time, a period is established in which the IOSEL inversion signal 13 is always inactive, thereby reducing the recovery time of the peripheral input/output device 4. It is secured.

FIG. 4 is a block diagram of a computer device showing a second embodiment of the present invention, FIG. 5 is a block diagram of the control circuit shown in FIG. 4, and FIG. 6 is a signal timing diagram of each part of the device in FIG. be. As shown in FIGS. 4 to 6, the present embodiment differs from the first embodiment in that the control circuit 2 is changed and a control circuit 25 having an encoder 28 and a presettable counter 27 is provided. . First, the control circuit 25 has input terminals for S0 to Sn signals 26 that can programmably set the recovery time for the control circuit 2 of FIG. The encoder 28 encodes these S0 to Sn
This is a circuit in which when a signal 26 is input, a constant value is determined for the input value. On the other hand, the presettable counter 27 has an input terminal for a LOAD signal 29 for loading preset data, and a terminal for inputting an encode signal 30 from the encoder 28. Further, S in the control circuit 25
When a count value corresponding to the recovery time required for the peripheral input/output device 4 is set by the input terminal of the 0 to Sn signal 26, it is encoded by the encoder 28 to obtain a count value to be preset in the presettable counter 27. The count value obtained by the encoder 28 is OV
The F signal 23 and the output obtained by inverting the HLDAK inverted signal 7 by the inverter 20 are input to the AND gate 19, and the RSF
/F17 is set. Also, this set signal is LOA
It is transferred to the presettable counter 27 as a D signal 29. This preset value is secured as the recovery time of the peripheral input/output device 4. In this embodiment, since the recovery time can be set using an external terminal, it is possible to flexibly respond to peripheral input/output devices 4 having different recovery times, and also to change the frequency of the CLK15 signal. It has the advantage of being able to respond to

[0015]

[Effects of the Invention] As explained above, the computer device of the present invention has a control circuit for ensuring the recovery time of the peripheral input/output device, so that the recovery time of the peripheral input/output device can be taken into account in software. The effect is that there is no need to do so. Furthermore, even when trying to improve the performance of the central processing unit, especially the operating clock frequency of the central processing unit to improve the performance of the entire device, the present invention can reuse past assets (software) without changing the software. This has the effect of making it possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a computer device showing a first embodiment of the present invention.

FIG. 2 is a configuration diagram of the control circuit shown in FIG. 1.

FIG. 3 is a timing diagram of signals of various parts of the device in FIG. 1;

FIG. 4 is a block diagram of a computer device showing a second embodiment of the present invention.

FIG. 5 is a configuration diagram of the control circuit shown in FIG. 4;

FIG. 6 is a timing diagram of signals of various parts of the device in FIG. 4;

FIG. 7 is a block diagram of a computer device showing a conventional example.

FIG. 8 is a timing diagram of signals of various parts of the device in FIG. 7;

9 is an operation flow diagram for explaining the operation of the CPU shown in FIG. 7. FIG.

[Explanation of symbols]

1 Central processing unit (CPU) 2, 25 Control circuit 3 Decoder 4 Peripheral input/output device 5 ADDR signal (address bus) 6 H
LDRQ inverted signal 7 HLDAK inverted signal 8 BCYST inverted signal 9 MRQ inverted signal 10 R/W inverted signal 11 DA inverted signal 12 DATA signal (data bus) 13
IOSEL inverted signal 14 DECEN inverted signal 15 CLK signal 16 Counter 17 RS flip-flop (RS F/F)
18, 19 AND gate 20 Inverter 21 NOR gate 22 NAND gate 23 OVF signal 24 Q inverted output 26 S0 to Sn signal 27 Presettable counter 28 Encoder 29 LOAD signal 30 Encode signal

Claims (1)

[Claims] [Claim 1] Bus control for relinquishing control of the bus.
A central processing unit that has a hold function and an address signal output function, and includes an input terminal for a hold request signal that enables the hold function, and an output terminal for a hold acknowledge signal that indicates that the hold function is operating. a peripheral input/output device that cannot be accessed for a certain period of time once accessed and requires a recovery time as a pause period; and once the central processing unit accesses the peripheral input/output device, the central processing unit A control circuit that automatically secures a necessary recovery time for the peripheral input/output device by controlling the bus control right to be relinquished, and prevents the central processing unit from continuously accessing the peripheral input/output device. A computer device comprising: