JPH047739A - Controlling system for instruction executing time - Google Patents

Abstract

PURPOSE:To secure the least executing time of an instruction which is used as a software timer by executing a read instruction that reads an area of a fixed wait time which is not fetched by a cache memory and obtaining a software timer. CONSTITUTION:A fixed wait time that is not fetched by a cache memory 40 is set before an answer signal 22 is turned on to a microprocessor 1. Thus the least executing time is assured for the read instruction of a dip switch 4. As a result, a software timer is obtained when the read instruction of the switch 4 is repeated by several times by a program which is carried out by the microprocessor 1. Then a fixed wait time set by the software timer is surely assured.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an instruction execution time control method for controlling the instruction execution time of a microprocessor in a computer system and obtaining a fixed delay time by a program.

(Prior Art) FIG. 2 is a block diagram showing the configuration of a device that implements the instruction execution time control method of the present invention.

The illustrated device includes a microprocessor 1, a ROM 2,
It consists of a main memory 3, a dip switch 4, a disk interface 5, a magnetic disk 6, a timer 7, an address decode wait control section 8, an interrupt controller 9, and the like.

The microprocessor 1 performs various data processing and control.

The ROM2 is a read-only memory and stores a system startup program and the like.

The main memory 3 is comprised of a random access memory, and stores programs executed by the microprocessor 1, processing results, and the like.

The dip switch 4 stores the initial setting values of the system. The initial setting values stored in the dip switch 4 are read by the microprocessor in the initial state.

Disk interface 5 connects the magnetic disk to data bus 11 and address bus 12 via bus 13 .

The magnetic disk 6 stores programs and data.

The timer 7 generates an interrupt signal 29 after a certain period of time has elapsed or at certain time intervals.

This interrupt signal 29 and an interrupt signal 28 generated from the disk interface 5 are input to the interrupt controller 9.

The interrupt controller 9 outputs an interrupt request signal 30 to the microprocessor 1 when any of the interrupt signals 28 and 29 is input.

The register 33 converts the voltage value output from the power supply voltage sensor 35 into a digital value via the A/D converter 34 and stores the digital value.

The address decode wait control section 8 decodes the address bus 12 and the address strobe signal 21, and outputs select signals 23 to 27 . Outputs 32.

Further, the wait time of the microprocessor 1 is controlled by controlling the response signal 22 to the microprocessor 1 according to the data response signal of each unit.

Now, considering the operation of the microprocessor 1, there are cases where an interval longer than a certain period of time is required between performing one process and performing the next process. for example,
General-purpose SC3I used for disk interface 5
In the bus controller LSI, at least 7
It is specified that microseconds are required.

One possible way to obtain a wait time of 7 μsec or more is to use timer 7, but in this system, this timer is used as a watchdog timer that monitors the program execution time, so it cannot be used for other purposes. cannot be used.

Providing another timer in addition to timer 7 is not possible because it would increase the amount of hardware and cost, so conventionally a method called a software timer has been used. This is a method in which a microprocessor obtains the necessary time by performing a simple loop in a program or executing a NOP (no operation) instruction multiple times. Since the instruction execution time of a microprocessor is determined for each instruction, the wait time of the software timer can be determined by calculating the sum of the execution times of each instruction.

(Problems to be Solved by the Invention) However, the above-described conventional technology has the following problems.

That is, in a microprocessor that has a built-in cache memory or performs vibe line processing, the instruction execution time varies depending on the cache memory and vibe line. For this reason, it was not possible to guarantee a constant wait time using a software timer.

The present invention has been made with attention to the above points, and the instruction execution time is such that even in a microprocessor that has a built-in cache memory or performs vibe line control, it is possible to reliably guarantee a certain wait time using a software timer. The purpose is to provide a control method.

(Means for Solving the Problems) The instruction execution time control method of the present invention defines a register with a constant wait time that is not related to the operating clock of the microprocessor in an area that is not taken into the cache memory,
The present invention is characterized in that the instruction execution time is controlled by executing a read instruction for reading the register by a program executed by a microprocessor to generate a wait time.

(Function) In the instruction execution time control method of the present invention, when a read instruction to read a predetermined area is executed by a program executed by a microprocessor, this area is not taken into the cache memory and the microprocessor operates. Since it is not related to the clock, a certain period of time specific to the read command can be secured as the wait time.

(Embodiment) FIG. 1 is a block diagram showing the configuration of a device that implements the instruction execution time control method of the present invention.

The illustrated device includes a microprocessor 1, a ROM 2,
It consists of a main memory 3, a dip switch 4, a disk interface 5, a magnetic disk 6, a timer 7, an address decode wait control section 8, an interrupt controller 9, and the like.

The microprocessor 1 performs various data processing and control.

The ROM2 is a read-only memory and stores a system startup program and the like.

The main memory 3 is comprised of a random access memory, and stores programs executed by the microprocessor 1, processing results, and the like.

The dip switch 4 stores the initial setting values of the system. The initial setting values stored in the dip switch 4 are read by the microprocessor in the initial state.

Disk interface 5 connects the magnetic disk to data bus 11 and address bus 12 via bus 13 .

The magnetic disk 6 stores programs and data.

The timer 7 generates an interrupt signal 29 after a certain period of time has elapsed or at certain time intervals.

This interrupt signal 29 and an interrupt signal 28 generated from the disk interface 5 are input to the interrupt controller 9.

The interrupt controller 9 outputs an interrupt request signal 30 to the microprocessor l when receiving either of the interrupt signals 28 or 29.

The register 33 converts the voltage value output from the power supply voltage sensor 35 into a digital value via the A/D converter 34 and stores the digital value.

Address decode wait control section 8 decodes address bus 12 and address strobe signal 21, and outputs select signals 23 to 27.32 for each unit of ROM 2, main memory 3, disk interface 5, timer 7, and register 33. Furthermore, the microprocessor 1
control the wait time. On the other hand, when accessing the dip switch 4, the address decode wait control unit 8 controls the wait time so that it is longer than the data response time and the instruction execution time is an appropriate value as a reference for the software timer. .

A select signal 23 to the ROM 2 and a select signal 24 to the main memory 3 are input to the NOR gate 10 . The output signal 31 of the NOR gate 10 indicates that the microprocessor 1 has accessed a memory other than the ROM 2 or the main memory 3. The microprocessor 1 receives this output signal 3
When 1 is input, data is not taken into the internal cache memory 40. As a result, dip switch 4, disk interface 5, timer 7,
The value output from register 33 is
This prevents the data from being taken into the internal cache memory 40 of the device.

Next, the operation when the dip switch 4 is read in the above-described device will be explained.

FIG. 3 is a time chart illustrating the operation of the apparatus shown in FIG.

Microprocessor 1 outputs an address indicating dip switch 4 to address bus 12, and turns on address strobe signal 21. Then, the dip switch 4 outputs data to the data bus 11 after a certain data response time.

The address decode wait control section 8 turns on the response signal 22 after a certain wait time when the select signal 25 is turned on.

Microprocessor 1 reads data on data bus 11 when response signal 22 is turned on. At this time, R
Since the select signal 23 of OM2 and the select signal 24 of the main memory 3 are both off, the NOR gate 1o
The output signal 31 of is off, and no data is taken into the cache memory 40 inside the microprocessor 1.

Thereafter, the microprocessor 1 turns off the address strobe signal 21 and the address bus 12. As a result, the address decode wait control section 8 turns off the select signal 25 and the response signal 22. Then, the dip switch 4 turns off the data on the data bus 11.

In this way, by providing a certain wait time between when the microprocessor 1 turns on the address strobe signal 21 and when the microprocessor 1 turns on the response signal 22, the dip switch 4 is read. Guarantees the minimum instruction execution time -0 Therefore, a software timer can be realized by repeating the read instruction for the dip switch 4 multiple times using a program executed by the microprocessor I.

Incidentally, in the above-mentioned embodiment, the wait time is gained by leading the dip switch 4.
Not limited to this, by reading the register 33,
You may also try to earn weight time. That is, although the register 33 monitors the power supply voltage using the power supply voltage sensor 35, the data in this register 33 is not taken into the cache memory 40 like the dip switch 4. Therefore, a software timer can be realized by repeating the read command of the register 33 multiple times using a program executed by the microprocessor 1.

(Effects of the Invention) As explained above, according to the instruction execution time control method of the present invention, a software timer is realized by executing a read instruction that reads an area with a certain amount of wait time before it is loaded into the cache memory. Therefore, it has the following effects.

That is, it is possible to guarantee the minimum execution time of an instruction used as a software timer.

Therefore, a software timer can also be used in a computer system that has a cache memory inside a microprocessor and performs pipeline control. ,

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a device that implements the instruction execution time control method of the present invention, FIG. 2 is a block diagram showing the configuration of a device that implements the conventional instruction execution time control method, and FIG.
The figure is a time chart explaining the operation of the apparatus shown in FIG. 1...Microprocessor, 2...ROM. 3... Main memory, 4... Datebusui Sochi,
5... Disk interface, 6... Magnetic disk, 7... Timer, 8... Address decode wait control section, 9... Interrupt controller, 10... Noah gate. u”e+o-leap=

Claims (1)

[Scope of Claims] A register with a fixed wait time that is not related to the operating clock of the microprocessor is defined in an area that is not taken into the cache memory, and a program executed by the microprocessor executes a read instruction to read the register and waits. An instruction execution time control method characterized in that the instruction execution time is controlled by generating time.