JPH0635757A - Abnormality detector of cpu - Google Patents

Abstract

PURPOSE:To provide the abnormality detector of a CPU suitable for applying to the servo system of a VTR. CONSTITUTION:The output signal level 13 of an O port 2 is turned to an H level while the CPU 1 executes a prescribed processing program stored in a ROM 4 and is turned to an L level after completion based on the interruption signals 11 of an interruption signal generator 5. At the time of the L level before the next interruption signal arrives, the abnormality detector 3 latches the L level and detects that the CPU 1 is not abnormal. When the CPU 1 becomes abnormal while executing the program and an abnormal state continues even when the interruption signal 11 arrives, the output level of the O port 2 is the H level and the abnormality detector 3 latches the H level, detects that the CPU is abnormal, and turns off the power source of the motor of the servo system of the VTR. The abnormality detection of nonregular processing impossible by a watchdog timer is enabled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an abnormality detecting device which is applied to a VTR servo system or the like to monitor an abnormality of a CPU suitable for detecting the abnormality of the CPU.

[0002]

2. Description of the Related Art In a servo system used in a VTR, a CPU is used for servo control, and peripheral circuits such as a capstan servo circuit are controlled based on a command from the CPU. As a method of monitoring the operation of this CPU, there is a watched dog timer (hereinafter referred to as WDT). This WDT is a timer that operates as follows. 1. The CPU periodically accesses the WDT and resets the WDT. 2. If it is not accessed for a certain period of time, change the output level. This output level change indicates that the CPU is not operating normally. That is, if the CPU is normal, there should be access for a certain period of time, but if there is no access for a certain period of time, it is determined to be abnormal. As a method of using this WDT, the time of the interval at which the WDT is regularly accessed is known in advance, and the time obtained by adding a margin to the longest time is set in the WDT, and then the operation of the CPU is started.

A block diagram shown in FIG. 5 shows a conventional example of a CPU control circuit including a peripheral processing circuit such as a capstan servo circuit adopting the WDT. In FIG.
Reference numeral 1 denotes a CPU that controls various controls in the servo system. Various signals (address signal, control signal) from the CPU 1 are supplied to an address decoder 51, in which the address signal is decoded, and the decoded address data is obtained. Based on this, the control signal is supplied as a specific access signal to the peripheral processing circuit (drive circuit for capstan servo, etc.) 52.

Reference numeral 53 is the WDT, and this WDT 5
3 is supplied with the decoded output from the address decoder 51, and is reset because the WDT 53 is accessed by the decode output at regular intervals (periodically) during normal operation of the CPU 1, so that the WDT 53 does not always overflow. It is like this.

When the CPU 1 is in an abnormal state, WDT5
Since the WDT 53 is not normally accessed, the WDT 53 is not reset and the CPU 1 is forced to perform the highest interrupt (NMI) or reset based on the control signal obtained by the overflow.

However, the CP according to the WDT53
The abnormality monitoring of U1 has the following limitations. 1. Since the WDT detects an abnormality that regular processing is not performed regularly, it cannot be used for monitoring irregular processing. For example, when the tape speed measurement processing is performed four times for one rotation of the motor in the servo system of the VTR, there is no processing when the motor is stopped.
If you try to use DT, you have to spend infinite time to control the motor, and you cannot use WDT. CP with such a VTR servo system
If the operation of U becomes abnormal and the abnormality cannot be detected, the tape may be damaged.

2. Since the set value of the abnormal time of WDT must be a value obtained by adding a margin to the longest time to be accessed in the normal operation, the detection is delayed by the margin.

[0008]

SUMMARY OF THE INVENTION An object of the present invention is to provide a CPU monitoring device for monitoring the operation of a CPU, which is solved without using WDT, in order to avoid the above-mentioned problems caused by using WDT.

[0009]

According to the present invention, a CPU, a storage device storing a predetermined program to be executed by the CPU, an interrupt signal generator for requesting the CPU to start a predetermined process, and the predetermined signal are provided. A processing execution signal output device that outputs a processing execution signal by discriminating when processing is being executed and when processing is not being executed;
An abnormality detector that detects an abnormality of the CPU by looking at the execution signal immediately before the PU starts the predetermined processing, and when the interrupt signal comes to the CPU, whether the previous interrupt processing is completed or not. It is characterized by detecting whether or not the CPU is abnormal if it is not completed.

[0010]

1 is a block diagram of a first embodiment of a CPU abnormality detecting device according to the present invention. In FIG. 1, 1 is C
PU, 2 is an O (output) port that constitutes an output device during processing, 3 is an abnormality detector for detecting an abnormality of the CPU, and 4 is R
OM, 5 is an interrupt signal generator that automatically generates an interrupt signal periodically or irregularly, 12 is a CP
Signals (address bus, data bus, control bus) for U1 to communicate with O port 2 and ROM 4, 1
Reference numeral 3 is an output of the O port, and reference numeral 14 is an abnormality detection signal.

A program executed by the CPU 1 is stored in the ROM 4, and in particular, the interrupt signal 11 is stored.
Comes to the CPU 1, the CPU 1 executes the following steps 1 to 4
The program is stored such that the processing is performed in the order of 1) and the processing of 1 to 4 is always completed before the next interrupt signal comes. That is, <Step 1> The output level of O port 2 is set to H level. <Step 2> A predetermined processing program is executed. <Step 3> The output of O port 2 is set to L level. <Step 4> end

That is, the output signal 13 of the O port 2 is programmed to be at the H level during the execution of the predetermined program and at the L level after the completion of the predetermined program. Anomaly detector 3
Performs the operation of latching the level of the output signal 13 of the O port 2 with the interrupt signal 11 and outputting the abnormality detection signal 14.

When the CPU 1 is operating normally and the interrupt signal 11 is received from the interrupt signal generator 5, the previous processing is always completed according to the program stored in the ROM, so that the abnormality detector 3 latches the L level of the output level of the O port 2 and indicates that the abnormality detection signal is normal.

On the other hand, when the CPU 1 becomes abnormal during the execution of the processing program, and the abnormal state continues even when the CPU runs away and the interrupt signal 11 comes, the output level of the O port 2 is H level. Therefore, the abnormality detector 3 latches the H level, and the abnormality detection signal 14 indicates that the CPU is abnormal. This abnormality detection signal is, for example, VT
In the case of the R servo system, it is sent to the power supply block to turn off the power supply to the motor.

As described above, the abnormality of the CPU 1 can be detected. According to this embodiment, when the predetermined process is requested, it is checked whether the previous process is completed, so that the abnormality of the CPU 1 can be detected even when the process is not a regular process. When used for regular processing, since there is no time delay of the time margin that is always provided in the WDT, it is possible to detect the abnormality earlier than the CPU abnormality is detected using the WDT.

In the case of the above embodiment, the interrupt signal 1
1, the predetermined processing program is started, but not the interrupt signal but a certain signal level is monitored by the I port constituting the processing request signal input device, and the predetermined processing is started by the change of the signal level. Alternatively, the processing program may be started with a different interrupt signal. FIG. 2 shows a block diagram in this case. This embodiment is different from the embodiment of FIG. 1 in that the interrupt request signal is not input to the CPU 1 but the process request signal generator 20 generates a substantial interrupt signal.
Is being input to the I port 21, and the CPU 1 is monitoring the processing start signal 31.

Next, depending on the setting method of the interrupt processing of the CPU, when the next interrupt comes during the execution of the previous interrupt processing, the next interrupt can be accepted and executed without waiting. An example of such a setting is shown in the block diagram of FIG. Here, 22 is an I port that constitutes a processing execution signal input device, 23 is an O port that outputs an abnormality detection signal, and 24 is a ROM that stores the interrupt processing program. In this case, ROM2
A program to be executed by the CPU as follows when the interrupt signal 11 from the interrupt signal generator 5 arrives at the CPU 1 may be stored in the memory 4.

<Step 1> The output 13 of the O port 2 is observed from the I port 22. <Step 2> As a result, if the H level is abnormal, the abnormality detection signal 14 is output from the O port 23. If it is at the L level, it is normal and the process proceeds to the next. <Step 3> The output level 13 of the O port 2 is set to the H level. <Step 4> A predetermined program is executed. <Step 5> The output of O port 2 is set to L level. <Step 6> ends.

In the case of this embodiment, the I port 22, O
A memory device such as a memory or a register may be used instead of the port 2. This embodiment is shown in the block diagram of FIG. In FIG. 4, the following processing program to be executed by the CPU 1 is stored in the ROM 26.

<Step 1> Look at the contents of the memory 25. <Step 2> As a result, if the content is in the process of executing the predetermined processing, it is abnormal, and therefore the abnormality detection signal 14 from the O port 23.
Is output. If the predetermined processing is completed, it is normal and the process proceeds to the next. <Step 3> The contents of the memory 23 are set to a predetermined process being executed. <Step 4> A predetermined processing program is executed. <Step 5> The contents of the memory 25 are terminated by a predetermined process. <Step 6> ends.

In each of the above-described embodiments, the end of all the processes is monitored. However, only some important processes in the process are monitored, and only some of the important processes are completed by the next time. It is also possible to store the program that needs to be executed in the ROM and execute the program.

[0022]

According to the present invention, when an interrupt signal comes to the CPU, it is checked whether or not the previous interrupt processing is completed, and if it is not completed, it is detected that the CPU is abnormal. As a result, it becomes possible to detect anomalies for irregular processing that was not possible with WDT. Further, abnormality detection for regular processing can be detected earlier than WDT.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of a second embodiment of the present invention.

FIG. 3 is a block diagram of a third embodiment of the present invention.

FIG. 4 is a block diagram of a fourth embodiment of the present invention.

FIG. 5 is a block diagram of a conventional example.

[Explanation of symbols]

 1 CPU 2 O port 3 CPU abnormality detector 4 ROM 5 Interrupt signal generator 20 Processing request signal generator 21 I port 53 WDT

Claims (5)

[Claims] 1. A CPU, a storage device storing a predetermined program to be executed by the CPU, a processing request signal generator requesting the CPU to start a predetermined processing, and the predetermined processing is being executed. A process-in-progress signal output device that outputs an in-execution signal by discriminating between a time and a non-occurrence time, and a signal during execution of the process when the process request signal comes or immediately before the CPU starts the predetermined process. An abnormality detector for detecting abnormality of the CPU, the abnormality detecting device for CPU. 2. The CP according to claim 1, wherein the processing request signal generator is an interrupt signal generator.
U abnormality detection device. 3. The CPU abnormality detection device according to claim 1, further comprising an I port for inputting the processing request signal. 4. A CPU, an interrupt signal generator for generating a signal for interrupting the CPU, and an interrupt signal from the interrupt signal generator for the CPU.
C, the interrupt processing by the subsequent interrupt signal is given priority over the interrupt processing by the previous interrupt signal.
A storage device storing a program executed by the PU and a CP
U A processing-in-progress signal output device that outputs a processing-in-progress signal, a processing-in-progress signal input device that receives a signal from the processing-in-progress signal output device, and an abnormal signal based on the signal input level of the processing-in-progress signal input device And an abnormality signal output device for detecting an abnormality and outputting an abnormality detection signal.
Anomaly detection device. 5. The CPU abnormality detection device according to claim 4, wherein the processing execution signal output device and the processing execution signal input device are configured by a storage device.