JPH0844593A - Runaway detector - Google Patents

Abstract

PURPOSE:To provide a runaway detector which detects runaway only by a CPU without using a reset IC and informs the occurrence of the runaway to the outside. CONSTITUTION:The CPU 1 is an ordinary central processing unit which incorporates a ROM or RAM 2, etc., in addition to a clock mechanism to clock a time. A LED 5 is connected to the CPU 1 via a resistor 4 between an output port 3 and a power source. The CPU 1 clears the clock interruptive timer of the clock mechanism at a fixed period earlier than timer time set on the timer. When the runaway of the CPU occurs, the clock interruptive timer is completed. An instruction to write a constant on the RAM 2 is prepared in a vector interruption destination by such time completion, and it is set so as to be reset after the instruction is executed. The CPU 1 refers to the RAM 2 at the beginning stage of processing after the application of the power source or reset, and makes the LED 5 put on continuously when no constant is stored, and makes it flicker when the constant is stored.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a runaway detecting device capable of detecting runaway only by a CPU without using a reset IC.

[0002]

2. Description of the Related Art Conventionally, there is a reset IC as a dedicated integrated circuit for detecting runaway of a CPU. This reset I
C is connected to the CPU, and when the CPU runs out of control, it detects the runaway and resets the CPU, thereby preventing the runaway of the CPU from continuing.

[0003]

However, the above reset IC simply resets the CPU when it detects a runaway of the CPU. Therefore, when a certain time has elapsed after the reset and the CPU automatically restarts the execution of the program from the head address, there is a problem that the runaway of the CPU cannot be known to the outside. Further, the reset IC has a problem that it is expensive as compared with a circuit that merely detects a runaway of the CPU.

In view of the above conventional circumstances, an object of the present invention is to
It is an object of the present invention to provide a runaway detection device which detects a runaway only by the CPU without using a reset IC and notifies the occurrence of the runaway to the outside.

[0005]

First, a runaway detecting apparatus according to the first aspect of the present invention is provided with a clock interrupt timer of a clock mechanism incorporated in a CPU and before a vector interrupt is performed by the clock interrupt timer. Means for clearing the clock interrupt timer at a constant cycle, and when the clock interrupt timer performs a vector interrupt because the clear means does not clear the clock interrupt timer at a constant cycle, A notification means is provided to notify the outside of the occurrence of an interrupt as the occurrence of a runaway.

Next, in the runaway detecting apparatus according to the second aspect of the present invention, a predetermined constant is stored in the clock interrupt timer, the clearing means, and the notifying means when the clock interrupt timer makes a vector interrupt. The notification means is configured to notify the outside of the occurrence of an interrupt by the clock interrupt timer when a constant is read from the storage means.

The notifying means comprises, for example, an LED connected between the CPU and a power source as described in claim 3.

[0008]

According to the first aspect of the invention, the clearing means clears the clock interrupt timer of the clock mechanism incorporated in the CPU at a constant cycle before the vector interrupt is performed by the clock interrupt timer. The clock interrupt timer performs vector interrupt when the clearing means does not clear in a fixed cycle. The notification means notifies the interrupt to the outside that a runaway has occurred.

In addition to the operation of each of the above means, the storage means stores a predetermined constant when the clock interrupt timer makes a vector interrupt, and the constant is read from the storage means. When notified, the notification means notifies the outside that a runaway has occurred.

Thus, the runaway can be detected only by the CPU and the occurrence of the runaway can be notified to the outside without using the reset IC.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a configuration diagram of an embodiment. In the figure, the CPU 1 is not particularly shown,
In addition to the system clock, it also has a clock mechanism for measuring time, and a ROM (R
It is an ordinary central processing unit having an ead only memory), an adder, a subtractor, a comparator, various registers, and the like. This CPU 1 is an RA
An M (Random Access Memory) 2 is built in, and an LED 5 is connected between an output port 3 and a power supply via a resistor 4.

A system program is stored in the built-in ROM, and the CPU 1 controls an application program stored in an external memory (not shown) by a user while controlling each of the above-mentioned components based on the system program. Execute programs etc.

The output of the output port 3 is maintained at the "L" level when the CPU 1 is operating normally.
Therefore, since a voltage is applied to the LED 5 in the forward direction, the LED 5 is constantly turned on.

The clock mechanism causes the clock interrupt timer to generate vector interrupts at regular intervals in order to generate time data. Of the various interrupts, originally, at the vector address where the interrupt by the clock interrupt timer occurs, for example, the time interrupt timer is set to 1/10.
If it is seconds, the time data in the memory for storing time is sequentially updated every 1/10 seconds, or every 1/100 if the time interrupt timer is set to 1/100 seconds. However, in this embodiment, another instruction is incorporated in the address of the vector interrupt performed by the clock interrupt timer of the clock mechanism, and the runaway is detected by utilizing this clock mechanism.

Next, the processing operation of the runaway detection in the embodiment having the above-mentioned configuration will be described with reference to the flow chart shown in FIG. In this processing, for example, a case of executing an application program (sequence program) for performing sequence control will be described. In general,
In execution of this sequence control (execution of sequence program), reading of data such as sensors, switches, instruments, calculation results, etc. is performed in a fixed cycle, and various outputs of relays, motors, etc. are output based on this cycle. It is controlled in time. In the flow chart of FIG. 2, “repeated” is a loop of the main routine portion of the above sequence program, which is not shown. In this embodiment, a predetermined value is set in the clock interrupt timer at the beginning of the main routine, and the clock interrupt timer is cleared at a constant cycle that is the timing before vector interrupt is performed by the clock interrupt timer. I am trying to do it.

In the flowchart shown in the figure, first, the CPU 1 refers to a predetermined area of the RAM 2 and determines whether or not a predetermined constant is stored in the predetermined area (step S1). This process is a process of determining whether or not a reset due to a runaway described later is being performed.

If the constant is not stored in the above determination (No in S1), it is determined that no runaway has occurred and the output of the output port 3 is maintained at "L". This makes LE
D5 continues to light (step S2).

Then, the RAM 2 is cleared (step S4). This process is the initial setting of the RAM 5, and is used for the RA in order to be used in the process of the sequence control which follows.
This is a process of clearing the entire area of M5.

In the sequence processing, first, predetermined time data is set in the clock interrupt timer of the clock mechanism (step S5). The set time data is set to have an appropriate cycle in consideration of the processing cycle of the sequence program.

Next, a normal sequence program (not shown) is executed, and the value of the clock interrupt timer is set to "0" at a predetermined constant cycle which is shorter than the time data set in the clock interrupt timer. Clear (step S6).

Subsequently, the execution of the sequence program and the clearing of the clock interrupt timer at regular intervals are sequentially repeated (steps S7 ... S8). When the sequence program completes one cycle, the above step S5
~ S8 is performed.

As a result, during normal execution of the sequence program, the clock interrupt timer is cleared to "0" before counting up the set timer value, so that no clock interrupt occurs.

In the above process, if the CPU 1 runs out of control,
The CPU 1 executes processing in an address order different from that in the case of processing a normal sequence program.
Alternatively, the same plural addresses are looped to repeat the processing. Therefore, the clock interrupt timer is not cleared at regular intervals.
The clock interrupt timer counts up, and a vector interrupt is generated by this clock interrupt timer. When a vector interrupt occurs, the address value of the address pointer is forcibly rewritten to the vector address corresponding to the vector interrupt, so that the process of the CPU 1 that was in the runaway state is changed to the vector address indicated by the address pointer. Transition.

In this embodiment, with this vector address, first, a process of writing a predetermined constant, for example, "1" in a predetermined area of the RAM 2 is executed (step S9), and then a reset process is executed (step S10). ). In addition, CP
Although some U do not have a reset command, this embodiment has been described by taking the case of a CPU having a reset command as an example. With this reset instruction, flags, stack, program counter, etc. are initialized. Then, after a certain time required for these reset processes has elapsed, the process is automatically restarted from the beginning of the program. This restart of the process is exactly the same as the process started when the power is first input. Therefore, as it is,
It is not possible to know from the outside whether or not the above runaway occurred.

However, in this embodiment, due to the above-mentioned runaway,
The constant "1" is written in a predetermined area of the RAM 2 by the vector interruption by the clock interruption timer. In the determination of step S2, since the constant "1" of the RAM2 is determined (S1 is Yes), the CPU is determined based on this determination.
1 alternately outputs "L" and "H" from the output port 3 (step S3). As described above, when the output of the output port 3 is “L”, the LED 5 is turned on, but when the output of the output port 3 is “H”, the direction of the voltage applied to the LED 5 is reversed and the LED 5 is turned on. Turn off the light. Therefore,
The LED 5 blinks by alternately outputting "L" and "H" from the output port 3 as described above. This LE
The blinking of D5 continues thereafter while the CPU is operating normally. This allows the user to know that the CPU 1 has runaway.

In the above embodiment, the case where the CPU 1 has a reset command has been described, but in the case of a CPU that does not have a reset command, runaway can be similarly detected using the clock mechanism. This will be described below as another embodiment.

The hardware configuration of the other embodiments is the same as that shown in FIG. However, the other embodiment is different from the case of FIG. 1 only in that the CPU 1 has no reset command.

The processing operation of runaway detection in another embodiment will be described with reference to the flow chart shown in FIG.
Note that this processing will also be described by taking a case of executing a sequence program for performing sequence control as an example. Also in this case, "repeated" in the flowchart of FIG. 3 is a loop of the main routine portion of the sequence program, although not particularly shown. In this case as well, at the beginning of the main routine, a predetermined value is set in the clock interrupt timer, and the clock interrupt timer is cleared at a constant cycle that is the timing before vector interrupt is performed by the clock interrupt timer. I am trying.

In the flowchart of FIG.
First sets the output of the output port 3 to "L". This turns on the LED 5 (step S11). continue,
The RAM 2 is cleared (step S12). This process is also the initial setting of the RAM 5 as in the previous embodiment, and the R 5
This is a process of clearing the entire area of AM5.

In the sequence processing, step S13
The processing shown in to S16 is the same as the processing shown in steps S5 to S8 of FIG. That is, after setting the time data in the clock interrupt timer so as to have an appropriate cycle, while executing the normal sequence program, the clock interrupt timer is set at a predetermined constant cycle that is shorter than the set time data. The process of clearing the value "0" is repeated.
Therefore, also in this case, the clock interrupt by the clock interrupt timer does not occur while the sequence program is normally executed.

If the CPU 1 runs out of control, the above clock interrupt (vector interrupt) occurs. In this case, in the process at the vector address corresponding to the vector interrupt, the CPU 1 performs a process of alternately outputting "L" and "H" from the output port 3. This causes the LED 5 to blink (step S17). As described above, in this embodiment, when a vector interrupt is generated by the clock interrupt timer due to a runaway, the LED 5 is immediately blinked.

Then, after this, the process shifts to the step S12 and steps S12 to S16 are performed. However, since the LED 5 is blinking as described above, it is immediately known that the CPU 1 has runaway outside.

[0033]

As described above in detail, according to the present invention, since the runaway can be detected and reset by using the clock mechanism normally built in the CPU, an expensive reset IC becomes unnecessary, Therefore, the product cost is reduced.
Further, since the LED is made to blink by the runaway detection, it is possible to know from the outside that the runaway has occurred even if the CPU is operating again after the reset. Therefore,
Since it is possible to avoid the risk that the time passes without noticing the runaway and to take an early measure against the runaway, it contributes to the early improvement of the work environment such as sequence control.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment.

FIG. 2 is a flowchart illustrating a processing operation of runaway detection in one embodiment.

FIG. 3 is a flowchart illustrating a processing operation of runaway detection in another embodiment.

[Explanation of symbols]

 1 CPU 2 RAM 3 Output port 4 Resistor 5 LED

Claims (3)

[Claims] 1. A clock interrupt timer of a clock mechanism built in a CPU (Central Processing Unit), and the clock interrupt timer is cleared at a constant cycle before vector interrupt is performed by the clock interrupt timer. When the clock interrupt timer performs a vector interrupt by the clearing means and the clearing means does not clear the clock interrupt timer in a constant cycle, the occurrence of the interrupt is notified to the outside as occurrence of runaway. A runaway detection device comprising: 2. The clock interrupt timer further comprises a storage unit for storing a predetermined constant when the vector interrupt is performed, and the notification unit is configured to read the clock when the constant is read from the storage unit. 2. The runaway detection device according to claim 1, wherein the occurrence of an interrupt by the interrupt timer is notified to the outside. 3. The runaway detecting device according to claim 1, wherein the notifying unit is an LED (issuing diode) connected between the CPU and a power source.