JPH03246603A - Rapid counter - Google Patents

Abstract

PURPOSE:To make it possible to hold a count value even at the time of generating service interruption by storing the count value of a counter in a memory. CONSTITUTION:A backed-up RAM 3 and the counter 5 for outputting an interruption request signal to a CPU 1 in each counting an external clock are used for the rapid counter. The CPU 1 prepares interruption processing such as the saving of a register at the time of receiving an interruption request from the counter 5 and adds '1' to the count value stored in the RAM 3. When the count value reaches a set point, processing such as the output of prescribed data to a prescribed output address, the setting of the succeeding set point in the RAM 3 and the updating of a table pointer is executed. Since the count value of the counter 5 is successively stored in the RAM 3, the count value can be stored even at the time of generating power interruption.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to a high-speed counter that can set count values in multiple stages and is used in a sequence control device that controls the operation of a load according to a sequence control program.

[Prior Art] Some sequence control devices that control the operation of a load according to a sequence control program require a high-speed counter that can set count values in multiple stages. Therefore, a method has been proposed in which the above-mentioned high-speed counter is implemented as software in the arithmetic processing section of the sequence control device. In this method, the elapsed value of the counter that counts the clock,
A comparison command is used to compare a target value (set value) at which the output should be changed, and a load control signal is output based on the result. However, this method has a problem in that the output response varies within the scan speed range of the sequence control program.

Therefore, in addition to the CPU for normal program execution, there is a method of using a CPU dedicated to counter processing (or, if even higher-speed processing is required, the comparison processing is also made into hardware). However, in this case, there was a problem of increased costs due to the addition of an expensive CPU.

In order to solve these conventional problems, the present inventor proposed the following sequence control device in Japanese Patent Application No. 62-269573. This sequence control device
As shown in the figure, input signals are taken in through a RAM 3 that stores a sequence control program and an I10 interface 2, and a load control signal is created based on the sequence control program.
1, a preset counter 5 that counts an external clock and outputs an interrupt request signal when the count is up, and a ROM 4 that stores a system program.

Here, in addition to the above-mentioned sequence control program, the RAM 3 stores a data table shown in FIG. 7 that stores a plurality of sets of setting values to be preset in the counter 5, output addresses, and output data. is created by a counter setting instruction in the sequence control program. Furthermore, since the counter 5 can selectively count the internal clock, it performs down-counting and outputs a pulse as an interrupt request signal when the counter 5 counts down to zero.

If the counter 5 is to start a multi-stage count-up operation, the initial set value (set value 0 in FIG. 7) is preset after initialization. When the set value is counted up, the counter 5 issues an interrupt to CP and Ul, and the CPU performs the interrupt processing shown in FIG. After that, load the table pointer of the data table. In this case, the table pointer is "
1"), the contents of the data table indicated by this table pointer (output address "0", output data "0") are loaded, and the output data ("0") is loaded to the output address ("0"). '') and completes the first stage counting operation.Next, the second stage set value (1") is preset to counter 5, and the table pointer is updated to "4". ), restores the register, returns to the original program processing (the processing before branching to the insert processing), and repeats operations such as performing arithmetic processing based on the normal sequence control program until the next interrupt occurs. .

According to this method, the number of stages of the speed counter can be set arbitrarily (within the storage capacity of the data table set according to the storage capacity of RAM3), and the Multi-stage setting is possible without adding expensive hardware, and the external clock is counted by counter 5, and when the count is 771, the CPU
1 and outputs predetermined data to a predetermined output address, the counting operation at each stage does not depend on the scan speed of the sequence control program, and variations in output response can be eliminated.

[Problem to be solved by the invention 1 However, as mentioned above, the counter 5 which is an external counter
When using this, there was a problem that the count value of the counter 5 would be reset in the event of a power outage.

In other words, the multi-stage setting high-speed counter described above is of a type that does not hold count values.

The present invention has been made in view of the above-mentioned points, and its object is to provide a holding type multi-stage setting high-speed counter.

[Means for Solving the Problems] In order to achieve the above object, the present invention includes an arithmetic processing means that controls the operation of a load based on a sequence control program, and an arithmetic processing means that interrupts the arithmetic processing means every time one clock is counted. A data table that stores multiple sets of a preset counter that outputs a request signal, a set value to be set to this counter, data that is output when the counter counts up the set value, and an address to which the data is output. The count value of the counter is stored in the memory, and the count value stored in the memory is updated every time the arithmetic processing means is interrupted.

Note that in order to eliminate the need for backup, a non-volatile memory may be provided separately, and the count value stored in the memory may be transferred to the non-volatile memory when the power supply voltage drops.

[Operation 1] The present invention configures a high-speed counter as described above so that the count value of the counter can be stored in the memory, so that the count value is retained even in the event of a power outage. It is.

Note that if a non-volatile memory is provided separately and the count value stored in the memory is transferred to the non-volatile memory when the power supply voltage drops, memory backup becomes unnecessary.

[Example 1] An embodiment of the present invention is shown in FIGS. 1 and 2. FIG.

This embodiment is basically the same as the conventional example shown in FIG. 6, except for the fish described below.

The RAM 3 of this embodiment is backed up, and the counter 5 is one that issues an interrupt request signal to the CPU every time it counts one external clock. Then, each time the CPUI receives this interrupt request signal, it executes the processing shown in FIG. First, when an interrupt request is received from the counter 5, preparations for interrupt processing such as register saving are made, the count value in the RAM 3 is incremented by one, and it is determined whether the count value has reached a set value. Here, when the set value is reached, the predetermined data is output to the predetermined output address and the next set value is set in the RAM 3 (conventionally, the counter 5 8) and update the table pointer. and,
When the processing is completed or the count value does not reach the set value, the register is restored, the interrupt processing is finished, the original program processing (the processing before branching to interrupt processing) is resumed, and the next interrupt is executed. Until then, the operation of performing arithmetic processing based on the normal sequence control program is repeated. In other words, in this embodiment, the count value of the counter 5 is stored in the RAM 3, so even if there is a power outage, the counting will continue. The value is retained, and there is no need to back up the counter 5 itself.Moreover, storing the count value on the backed up RAMa in this way has seven advantages in that the current consumption can be lower than when backing up the counter 5 itself. .

[Example 2] Other embodiments of the present invention are shown in FIGS. 3 to 5.

This embodiment performs the processing operation for holding count values in the same manner as the first embodiment, but differs from the first embodiment in the following points. In other words, in the case of this embodiment, as shown in FIG. 3, E2FROM6, which is a nonvolatile memory,
A new voltage drop detection circuit 7 is installed to detect the voltage drop of the power supply (for example, 24■), and the output of the voltage drop detection circuit 7 is connected to the NMI (/n masked interrupt) of the CPU 1.
, interrupts CPU 1 during a power outage, stores the count value in RAM 3 as shown in Figure 4, and outputs the count value to E2.
The count value is transferred to the FROM 6, and when the power is restored, the count value is transferred from the E2 FROM 6 to the RAM 3 after initialization as shown in FIG.

Note that the transfer of the count value from RAM3 to E"PROM6 is performed by the CPU, RAM3, ROM4, and E"PROM.
This is performed while the ROM 6 is at an operable voltage (for example, while the output voltage Vcc of the power supply circuit 8 is maintained at 5V). Therefore, in the case of this embodiment, there is no need to back up the RAM 3 either, and therefore no battery or the like is required for backup, making maintenance easier. Furthermore, although the voltage drop detection circuit 7 is used in the above case, a voltage drop signal may be given to the CPU from a manual switch such as a power switch.

[Effect of the Invention 1] As described above, the present invention includes an arithmetic processing means that controls the operation of a load based on a sequence control program, and a preset type that sends an interrupt request signal to the arithmetic processing means every time one clock is counted. Stores a data table that stores a counter, a setting value to be set to this counter, data to be output when the counter outputs the setting value, and a plurality of sets based on the address to which the data is output. The count value of the counter is stored in the memory, and the count value stored in the memory is updated every time an interrupt occurs to the arithmetic processing means, so the count value of the counter is stored in the memory. The count value is stored, so even if there is a power outage, the count value is retained. Moreover, by storing the count value in the backed up memory in this way, current consumption can be reduced compared to backing up the counter itself.

In addition, if a non-volatile memory is provided separately and the count value stored in the memory is transferred to the non-volatile memory when the power supply voltage drops, there is no need to back up the memory. It never becomes a hassle.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. #12 is a 7rj-chart showing the same CPU f) interrupt processing, Fig. 3 is a circuit diagram of another embodiment, and Fig. 4 is a CP at a power outage. 70-chart showing U interrupt processing, wIJ5 diagram 70-chart showing CPU processing when power is restored, Fig. 6 is a circuit diagram of a conventional example, Fig. 7 is an explanatory diagram of a data table, and Fig. 8 is a 70-chart showing CPU processing when power is restored. 70 is a chart showing CPU interrupt processing; FIG. 1 is CPU, 3 is RAM, 4 is ROM, 5 is counter,
6 is an E2PROM, and 7 is a voltage drop detection circuit.

Claims (2)

[Claims] (1) A high-speed counter that is used in a sequence control device that controls the operation of a load based on a sequence control program and is capable of setting count values in multiple stages, and is an arithmetic processing means that controls the operation of the load based on the sequence control program. , a preset counter that issues an interrupt request signal to the arithmetic processing means every time it counts one clock, a set value to be set to this counter, data output when the counter counts up the set value, and the data. and a backed-up memory that stores a data table that stores a plurality of sets of addresses that are output. A high-speed counter characterized by updating a counted value. (2) The high-speed counter according to claim 1, wherein a non-backed-up memory is used as the memory, a non-volatile memory is provided separately, and the count value stored in the memory is transferred to the non-volatile memory when the power supply voltage drops. .