JPH05233851A - Microprocessor - Google Patents

Abstract

PURPOSE:To improve the privacy of a system provided with the microprocessor. CONSTITUTION:This microprocessor to be operated on any specified private condition is provided with a timer 1 to count the operating period of the microprocessor, register 2 to successively store data values showing the operating period, storage circuit 4 to store a data value showing operating limit specified in advance, comparator 3 to compare and collate the data value showing the operating period stored in the register 2 with the data value showing the operating limit stored in the storage circuit 4, at least, and when the data value showing the operating period exceeds the data value showing the operating limit, the function of a built-in CPU 5 is stopped through a control signal 102 outputted from the comparator 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, and more particularly to a microprocessor used for a security / crime prevention device.

[0002]

2. Description of the Related Art Conventionally, for measuring the operating time of a microprocessor, a predetermined software is used for processing. 2 shows the circuit configuration at the time of measuring the operating time, and FIG. 3 shows
It is a flow chart which shows a processing procedure in that case. In addition,
The block diagram shown in FIG. 2 is a partial block diagram showing only a portion of the microprocessor concerned with the present invention.

2 and 3, when a certain time value is set in the timer 6, counting is started in the timer 6 via the input clock 103, and when a predetermined count value is reached, the timer is stopped. The INT control signal 104 is output from 6 and is input to the INT terminal of the CPU 9. In response to the INT control signal 104, the CPU 9 enters the interrupt processing operation, and the program is started from the start shown in the flowchart of FIG. In the process of this interrupt processing, the operating period time data stored in the memory circuit (RAM) 7 is read out, the operating period value is added (step 31), the timer value is updated (step 32), and then the relevant period value is updated. Returning to the original processing from the interrupt processing (step 33), the interrupt processing ends,
The timer 6 starts counting again.

Further, even when it is determined whether the operating time exceeds the value of the predetermined operation time limit data and the processing is stopped, the processing is performed by the software.
In the flow chart showing the processing procedure of, the storage circuit (RAM)
The operation period data value (B) of the microprocessor itself is read from 7 and the operation time limit data value (A) is read from the memory circuit (ROM) 8 (step 41).
When the operation period data value (B) and the operation period data value (A) are compared and determined (step 42) and the operation period data value (B) is within the operation period data value (A), , Normal processing, that is, normal application processing is continuously performed, and the operation period data value (B) is
If the operation time limit data value (A) is exceeded, the execution function of the program is stopped and the processing ends.

In the conventional microprocessor described above, the operating period is updated via software, and the operating period data value and the like are read out. However, in this method, since this function can be easily deleted and changed by deleting / changing the software, it is suitable for a microprocessor operated under a specific security condition. It has the drawback that it cannot.

[0005]

A microprocessor according to the present invention is a microprocessor which is operated under a specific security condition, in which a first data storage for sequentially storing a data value indicating an operation operation period of the microprocessor. Means, a second data storage means for storing a data value indicating a predetermined operational operation time limit for the microprocessor, and data indicating the operational operation period stored in the first data storage means. At least an operation operation period comparison means for comparing and collating a value with a data value indicating the operation operation time limit stored in the second data storage means, wherein the data value indicating the operation operation period is At the time when the data value indicating the operational operation time limit is exceeded, the built-in CP is transmitted via the control signal output from the operational operation period comparison means It is characterized by stopping the function.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a partial block diagram showing an embodiment of the present invention, and only a portion related to the present invention is shown. As shown in FIG. 1, the partial circuit of this embodiment includes a timer 1, a register 2, a comparator 3, a memory circuit 4, and a CPU 5.

In FIG. 1, in the timer 1, counting is performed via the clock 101, and the value of the operation period data output as a result is input to and stored in the register 2. The value of the operating period data stored in the register 2 is compared with the value of the operating period data held in the memory circuit 4 via the comparator 3, and the value of the operating period data stored in the register 2 is determined. If it is larger than the value of the operation time limit data held in the memory circuit 4, the control signal 102 for controlling the operation of the CPU 5 is continuously output from the comparator 3 as an inactive signal and the READY of the CPU 5 is read. Input to the terminal,
In response to this control signal, CPU 5 enters a state in which wait cycles are repeatedly generated, and its functional operation is completely stopped. Further, in the comparator 3, when the value of the operation period data stored in the register 2 is within the value of the operation deadline data held in the memory circuit 4, the control signal 102 is output from the comparator 3.
Is not output, and the CPU 5 performs a normal processing operation.

The function of the CPU 5 can also be stopped by stopping the function of the program counter of the microprocessor by the control signal 102 output from the comparator 3.

[0010]

As described above, according to the present invention, the processing related to the operation period, which has been conventionally processed by software, is performed through the hardware in the microprocessor, so that the software can be rewritten. Therefore, there is an effect that the security measures are highly effective.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional example.

FIG. 3 is a flowchart showing a processing procedure in a conventional example.

FIG. 4 is a flowchart showing a processing procedure in a conventional example.

[Explanation of symbols]

 1, 6 timer 2 register 3 comparator 4 storage circuit 5, 9 CPU 7 storage circuit (RAM) 8 storage circuit (ROM)

Claims (1)

[Claims] 1. In a microprocessor operated under a specific security condition, first data storage means for sequentially storing a data value indicating an operation operation period of the microprocessor, and the microprocessor in advance. A second data storage means for storing a data value indicating a prescribed operational operation time limit; a data value indicating an operational operation period stored in the first data storage means; and a second data storage means An operation operation period comparison means for comparing and collating with a stored data value indicating the operation operation time limit, and at a time point when the data value indicating the operation operation time period exceeds the data value indicating the operation operation time limit. A micro controller characterized in that the function of a built-in CPU is stopped through a control signal output from the operational operation period comparison means. Processor.