JPH05216701A - Recovery time adjusting circuit for input/output instruction - Google Patents

Abstract

PURPOSE:To simplify the insurance of recovery time of an input/output instruction and to eliminate the reconsidering of software at every device. CONSTITUTION:A matrix circuit 1 outputs count preset values 111 set in accordance with a CPU specification signal 100, a CPU operating frequency signal 101, and a bus operating frequency signal 102 to a counter circuit 2. The counter circuit 2 subtracts the count preset value 111 from the matrix circuit 1 from a counter start-up signal 151 representing the detection of an I/O instruction provided with a specific I/O address from a CPU 4 by a decoder circuit 5 when it is inputted. A wait control circuit 3 requests waiting to the CPU 4 by activating a ready signal 131 when the counter startup signal 151 from the decoder circuit 5 is inputted, and cancels such wait request for the CPU 4 by activating the ready signal 131 when a count-out signal 121 is inputted from the counter circuit 2.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a recovery time adjusting circuit for an input / output instruction, and more particularly to a method for adjusting an execution time of an I / O (input / output) instruction.

[0002]

2. Description of the Related Art Conventionally, in an information processing device, a CPU
When the (central processing unit) continuously accesses the peripheral LSI, a malfunction occurs when the CPU makes the next access in a state where the operation on the peripheral LSI side is not completed with respect to the first access. Therefore, peripheral LSI
The time required to secure the recovery time for guaranteeing the normal operation of the CPU is converted into the number of clocks of the CPU, and the NOP (no operation) instruction with the number of clocks converted immediately after the execution of the first I / O instruction in the software is executed. Or JMP
(Jump) instructions are inserted. By this, CP
Peripheral L in U by NOP instruction or JMP instruction
It is kept waiting until the operation of SI is completed, and then the next I / O instruction is executed.

When the CPU continuously accesses the peripheral LSI, the number of clocks to be delayed depends on the type of the CPU, the operating frequency of the CPU, and the CPU and the peripheral LSI.
The basic cycle time differs depending on the three parameters of the operating frequency of the bus connecting the and. Therefore, the CPU
To wait until the operation of the peripheral LSI is completed N
The number of OP instructions or JMP instructions varies depending on each device. Therefore, when the software directly accesses the peripheral LSI, it is necessary to review or change the software each time a new device is developed.

In such a conventional information processing apparatus, in order to secure the recovery time of the I / O instruction to the peripheral LSI, the type of CPU used in the apparatus, the operating frequency of the CPU, and the operating frequency of the bus are used. It is necessary to determine the number of clocks to be delayed by discriminating the three parameters, and the number of NOP instructions or JMP instructions to be inserted in order to wait until the operation of the peripheral LSI is completed must be reviewed for each device. is there.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in order to eliminate the above-mentioned problems of the conventional one, and it is possible to simplify the recovery time of input / output instructions and eliminate the need to review the software for each device. It is an object of the present invention to provide a recovery time adjustment circuit for an input / output command that can be performed.

[0006]

The recovery time adjusting circuit according to the present invention is an input / output for ensuring a recovery time for guaranteeing the operation of the peripheral device when the input / output commands are continuously output from the central processing unit to the peripheral device. A recovery time adjusting circuit for an instruction, the detecting means for detecting that a preset specific instruction is output from the central processing unit, and the central processing of a set value for measuring a preset predetermined time. Setting means for setting according to the type and operating frequency of the device and operating frequency of the bus between the central processing unit and the peripheral device; and the setting means when the output of the specific command is detected by the detecting means. The present invention is characterized in that a suppression means is provided for suppressing the operation of the central processing unit while the set value set is counted.

[0007]

An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, the matrix circuit 1 has a CPU type signal 100, a CPU operating frequency signal 101, and a bus operating frequency signal 102 so that the time from when the counter circuit 2 is activated until the time-out signal 121 is output is always constant. The count set value 111 set accordingly is output to the counter circuit 2. Here, the CPU type signal 100 indicates the type of the CPU 4, and the CPU operating frequency signal 101 is C
The operating frequency of PU4 is shown, and the bus operating frequency signal 102 shows the operating frequency of a bus (not shown).

When the counter activation signal 151 is input from the decoding circuit 5, the counter circuit 2 receives the matrix circuit 1
The count set value 111 sent from is subtracted in synchronization with the bus clock signal 103. When the count value becomes 0, the counter circuit 2 outputs the count-out signal 121 to the wait control circuit 3.

When the counter activation signal 151 is input from the decoding circuit 5, the wait control circuit 3 inactivates the ready signal 131 to request the CPU 4 to wait. When the count-out signal 121 is input from the counter circuit 2, the wait control circuit 3 activates the ready signal 131 to cancel the wait request to the CPU 4.

When the CPU 4 continuously accesses a peripheral LSI (not shown), the I / O control signal 141 and the address signal 142 cause an I / O having a specific I / O address.
The / O instruction is output to the decoding circuit 5. Also, CPU4
Stops its operation when the ready signal 131 from the wait control circuit 3 becomes inactive, and starts the operation when the ready signal 131 from the wait control circuit 3 becomes active.

The decode circuit 5 receives a specific I / O signal according to the I / O control signal 141 and the address signal 142 from the CPU 4.
When the I / O instruction having the O address is detected, the counter activation signal 151 is sent to the counter circuit 2 and the wait control circuit 3.
Is output.

FIG. 2 is a flow chart showing the operation of one embodiment of the present invention. The operation of the embodiment of the present invention will be described with reference to FIGS.

Since the recovery time of the I / O instruction of the peripheral LSI is usually required to be about 0.5 to 10 μs, the count set value 111 set in the counter circuit 2 is the count out signal 121 and the counter start signal 151 is input. To about 0.
The value is set so that it will be output after 5 μs. Since the count setting value 111 is determined by the matrix circuit 1 in terms of hardware, the software operating in the CPU 4 is C
It is no longer necessary to be aware of the type and operating frequency of the PU 4, and the operating frequency of the bus. Software is each peripheral LSI
Required I / O instruction recovery time is 0.5 μs
The required recovery time can be increased by inserting I / O instructions with a specific I / O address as many times as necessary during continuous access of I / O instructions to the peripheral LSI, considering how many times Can be secured.

That is, when the CPU 4 continuously accesses the peripheral LSI (step 11 in FIG. 2), the CPU 4
From the I / O having a specific I / O address to the decoding circuit 5
The I / O control signal 141 and the address signal 142 of the O instruction are output (step 12 in FIG. 2).

The decode circuit 5 receives a specific I / O signal according to the I / O control signal 141 and the address signal 142 from the CPU 4.
When the I / O instruction having the O address is detected, the counter activation signal 151 is sent to the counter circuit 2 and the wait control circuit 3.
Is output.

When the counter activation signal 151 is input from the decoding circuit 5, the counter circuit 2 receives the matrix circuit 1
The count set value 111 sent from is subtracted in synchronization with the bus clock signal 103. In addition, the weight control circuit 3
When the counter activation signal 151 is input from the decoding circuit 5, the signal inactivates the ready signal 131 to the CPU 4. As a result, the CPU 4 stops operating.

The counter circuit 2 outputs a count-out signal 121 to the wait control circuit 3 when the count value becomes 0 by subtraction in synchronization with the bus clock signal 103. When the count-out signal 121 is input from the counter circuit 2, the wait control circuit 3 activates the ready signal 131 to cancel the wait request to the CPU 4. This causes the CPU 4 to start operating.

At this time, the CPU 4 has not recovered the recovery time of the I / O instruction (step 1 in FIG. 2).
3), the I / O control signal 141 and the address signal of the I / O instruction having the specific I / O address again in the decoding circuit 5
142 is output (step 12 in FIG. 2). On the other hand, CPU4
If the recovery time of the I / O instruction has passed (Fig. 2
Step 13), the next access to the peripheral LSI is executed.

In the processing operation described above, the matrix circuit 1
Although the count set value 111 is set by, the count set value 111 can also be set by software. In that case, the count setting value 111 may be set once by the program for initializing the hardware, and it is necessary to output the I / O instruction having the specific I / O address by the software as in the processing operation described above. It is enough to secure a good recovery time.

As described above, the CPU type signal is set so that the time from the activation of the counter circuit 2 in the matrix circuit 1 to the output of the time-out signal 121 is always constant.
100 and CPU operating frequency signal 101 and bus operating frequency signal 1
The count setting value 111 is set in accordance with 02 and the decoding circuit 5 has an I / O from the CPU 4 having a specific I / O address.
When the / O command is detected, the ready signal 131 from the wait control circuit 3 is made inactive until the counter circuit 2 subtracts the count set value 111 from the matrix circuit 1 and outputs the count-out signal 121. By outputting the request, it is possible to simplify the recovery time of the I / O instruction and eliminate the need to review the software for each device.

In the embodiment of the present invention, the counting circuit 2
Is subtracting the count set value 111 from the matrix circuit 1, but the count set value from the matrix circuit 1 is
You may make it add until it becomes 111, but it is not limited to this.

[0023]

As described above, according to the present invention, the type and operating frequency of the central processing unit and the operation of the bus between the central processing unit and the peripheral device are set to set values for measuring a preset predetermined time. Input / output by setting according to the frequency and suppressing the operation of the central processing unit until the set value is counted when it is detected that a predetermined specific command is output from the central processing unit. It is possible to simplify the recovery time of instructions and eliminate the need to review software for each device.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of the embodiment of the present invention.

[Explanation of symbols]

 1 matrix circuit 2 counter circuit 3 weight control circuit 4 CPU 5 decode circuit

Claims (1)

[Claims] 1. A recovery time adjusting circuit for an input / output instruction, which secures a recovery time for guaranteeing the operation of the peripheral device when the input / output command is continuously output from the central processing unit to the peripheral device. Detecting means for detecting output of a preset specific command from the central processing unit, and setting values for timing a preset predetermined time, the type and operating frequency of the central processing unit, and the center. Setting means for setting according to the operating frequency of the bus between the processing device and the peripheral device, and the set value set by the setting means when the output of the specific command is detected by the detecting means A recovery time adjusting circuit, characterized by further comprising a suppressing means for suppressing the operation of the central processing unit.