JPS5922145A - Interruption control system - Google Patents

Abstract

PURPOSE:To transfer program execution processing to a block of interruption processing in case of the occurrence of interruption and to realize high-speed response, by dividing a control program through a programmable controller. CONSTITUTION:For example, if an input port 3B generates an interruption signal while a CPU1 executes a periodic execution block SCAN-A, a corresponding bit B of an interruption register 2 is set immediately. After the CPU1 finishes the block SCAN-A being executed, an interruption check on bits A, B, and C of the register 2 is made. Then, the bit B of the register 2 is set and the occurrence of interruption from an input port B is known. Then, an interruption execution block INTRPT-B is read out of a program memory 4 according to the starting address of an area of an address table 5 corresponding to the block and executed. After the execution, the bits A, B, and C of the register 2 are checked again to know that there is no set bit, so the execution of the periodic execution block SCAN-B is started.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interrupt control method that enables high-speed response to interrupt signals in a programmable controller used for equipment control.

A programmable controller generally controls input/output ports by periodically repeating and executing its entire program.

Therefore, even if the state of an input port changes, the change can only be detected when a program that refers to the state of the input port is executed.

In other words, if the state of the input port changes immediately after the program is executed, this can be detected by:
This is when the program is executed in the next cycle, and a delay (response time) of up to the execution cycle (for example, about 50 ms) will occur.

One of the attempts to reduce such delays is a combination of divided long-period program and short-period program, as shown in the execution cycle diagram of an example of a conventional interrupt control system in FIG.

In this conventional method, as shown in FIG. 1(a), the long-period program L is divided into blocks Lt, L2, La VC, and as shown in FIG.
1+, TJ 21 L 3, the short cycle program S is repeated a plurality of times immediately after execution of TJ 21 L 3.

According to this conventional method, the maximum response time for the short-cycle program S is from (TL+Ts) to (TL1+TS).
, (TL2+T8), (TL3+T!), whichever is the maximum, will be reduced by about 1/3, but the time allocated to the short-cycle program S will increase, so
The maximum response time for long-term program L is (TL+T
S) to (TL +3 ・Ts) i.

Another attempt is to use an interrupt control method similar to that used in general computers to transmit an interrupt signal indicating that a high-speed response is required when an interrupt occurs to the central processing unit, and then process the interrupt. Conventional method In this conventional method, the generation timing of interrupt signals cannot be controlled (limited) by the program creator, so when creating a program, an abnormal situation will not occur even if processing is interrupted by an interrupt signal at any timing. Therefore, sufficient caution is necessary and essential.

This is a big burden for program creators,
For example, for programmable controllers that are used in conjunction with equipment, the engineers involved are generally the creators of the programs, but they were unable to bear the responsibility of creating programs with the above-mentioned precautions, and in the end, , which requires a programmer for interrogation, making it complicated and uneconomical.

An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art, and provide an interrupt control method that is capable of high-speed response to interrupt signals and that is easy to create programs in a programmable controller used for equipment control. Our goal is to provide the following.

The configuration of the interrupt control method according to the present invention is a programmable controller that has an input/output controller for equipment control, etc., and has a function of sequentially and periodically executing and processing the stored control program from the beginning. In this step, the interrupt signal from the input port can be held, the control program is divided into a predetermined number of blocks, and at the end of execution of each block, it is checked whether or not the interrupt signal is held. When the interrupt signal is held, the control is performed so that the program execution/processing is immediately transferred to the interrupt processing block corresponding to the interrupt signal.

In short, by using a control program memory, execution can be transferred between blocks when an interrupt occurs to enable a high-speed response, and by limiting control transfer due to interrupts between blocks, it is easier to create programs. This makes it possible to

Hereinafter, embodiments of the present invention will be described based on the drawings.

FIG. 2 is a system block diagram of one embodiment of the interrupt control method according to the present invention, FIG. 3 is a time chart thereof, and FIG. 4 is a block diagram of an example of the same control program.

Here, ■ is the central processing unit (hereinafter referred to as CPU).
, 2 are interrupt registers that hold (set) the presence or absence of interrupt signals from input ports 3A, 3B, and 3C in corresponding bits; 4 is, for example, a periodic execution block 5CAN-A, B and an interrupt execution block; A program memory stores a control program consisting of blocks such as INTRPT-A, B, and C, divided into blocks; 5, a block address table indicating the start address of each block;

Note that FIG. 4 shows an example of a control program, in which (a) and (b) are for the above-mentioned periodic execution blocks 5CAN-A and B, and (C) is for the above-mentioned interrupt execution block INTRPT. -A is shown as a representative example. These are all using normal relay circuit symbols, and X-, Y- are each input port,
Shown on the output boat.

First, as shown in FIG. 3, for example, when an interrupt signal is generated from the input port 3B while the CPU is executing the periodic execution block 5CAN-A' of the normal control program, the interrupt register The corresponding bit B of 2 is set.

The CPU does not immediately respond to this interrupt, but immediately interrupts each bit A, B of the interrupt register 2 after the completion of the currently executing cyclic execution block 5CAN-A.

Check the state of C and perform an interrupt check INTK to see if an interrupt has occurred.

This causes CPU1 to interrupt bit B of the interrupt L/register.
is set and that an interrupt is generated from input capo 3B, first reset the pit B't of the side register, and then reset the interrupt block of block address table 5. The second line of the correspondence (
According to the start address shown in IV), the corresponding interrupt execution block INTRPT-B' is transferred from the program memory 4.
e, and execute/process it.

After the execution of this block is completed, the state of each bit A, B, and C of interrupt register 2 is not set. to complete the execution of the entire control program.

In this way, in response to an interrupt from any of the input ports 3A to 3C, the response and execution (processing) to the interrupt can be performed immediately at the end of the corresponding block without waiting for the execution of the entire normal control program being executed to complete. can do.

Finally, a comparison using specific numerical values between the conventional method and this embodiment will be shown below.

First, for both methods, the execution speed of C1) U is 4 μS/instruction, and the normal response (periodic execution) program is 1
0000 steps, a program requiring high-speed response (for interrupt execution) has 500 steps, and the required response time is 4 ms at the maximum.

In the conventional method explained in Fig. 1, in order to satisfy the above conditions, a 500-step high-speed response program must be executed at a cycle of 4ms, but the execution time is 2m5.
(4 μ5 × 500), so the long period program L cannot be executed in 2 In S L in 4 ms,
80m5 (4, /Z 5X1
00OOX4111S/217TS). That is, when attempting to perform a high-speed response of 4 mS for some signals, the execution time (total period) for other signals ends up being twice the real time.

On the other hand, in the method of this embodiment, if a program of 10,000 steps is divided into 10 blocks, the execution time of each block is 4;ns, so the maximum response time to an interrupt is 4ms' (if z is satisfied) Yes, you can.
Since interrupts do not occur often, the entire program with normal response (periodic execution) takes approximately 40 ms.
There is no practical problem even if it is assumed that one mouth is executed.

Furthermore, compared to conventional general interrupt control methods,
Since the CPU immediately starts responding when an interrupt occurs, the response time is short, usually about 1 ms.

On the other hand, in the method of this embodiment, the response time is 4
rns is slower than the one above, but the input/output ports of programmable controllers usually use filters with a delay of several milliseconds, so the difference in CPU processing time of 2 to 3 milliseconds is not a big problem. Must not be. if,
If this becomes a problem, the number of blocks can be further increased to about 20.

In this way, the method of this embodiment not only makes it possible to keep the response speed to the same degree as iK, but also reduces the possibility of an interrupt occurring at any of the above 10,000 steps in the conventional general interrupt control method. In contrast to this, the program creator has to pay a lot of attention, whereas he only has to pay attention to 10 to 20 places, which are the breaks between blocks, making the program creation much easier.

As described in detail above, according to the present invention, it is possible to respond to interrupt signals that require a high-speed response in a time comparable to that of a normal computer, and programming can be done easily. Like the Progera and Pull Controller, it is extremely easy to perform, and is simple and economical without the need for a programmer for interrogation. Effects can be obtained.

[Brief explanation of drawings]

FIG. 1 is an execution cycle diagram of an example of a conventional interrupt control method, FIG. 2 is a system configuration diagram of an embodiment of an interrupt control method according to the present invention, and FIG. 3 is a time chart thereof. Figure 4 is
It is a block diagram of the example of the same control program. 1...CPU, 2...Interrupt register, 3A, 3B. 3C...Input board, 4...Program memory, 5
...Block address table. Agent Patent attorney Kosaku Fukuda (and 1 other person) Kaya 1st (a-2 (b)) 2nd $3 Kyo 4th (υ) (C)

Claims (1)

[Claims] 1. In a programmable controller that has an input/output controller for equipment control, etc., and has the function of sequentially executing and processing periodically from the beginning according to a stored control program, it holds interrupt signals from input ports. In addition, the control program is divided into a predetermined number of blocks, and at the end of execution of each block, it is checked whether or not the interrupt signal is held, and if it is held. An interrupt control method is characterized in that control is performed so that program execution and processing are immediately transferred to an interrupt processing block corresponding to the interrupt signal.