JPH05108384A - Microprocessor - Google Patents

Abstract

PURPOSE:To interrupt a microprocessor and to perform the proper processing such as resetting in the case the microprocessor starts to run away to process a non-program area or process a part not to be processed even in a program area. CONSTITUTION:A microprocessor 1 is provided with an execution part 5 having a program counter 3, an address register 7, and a comparator 9. The execution part 5 sets interruption start address data to the address register 7. The comparator 9 compares the address data held in the address register 7 with the value of a program counter 3 to judged the equality. In this case, the comparator 9 gives an interruption signal Sint to the execution part 5 when the value of the program counter 3 equals to the address data. Thus, the proper processing such as resetting can be performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor capable of recovering from a runaway at high speed.

[0002]

2. Description of the Related Art As is well known, a microprocessor of this type is defined as a processing mechanism in which its elements are integrated in one or several integrated circuits. This microprocessor does not have a mechanism for generating an interrupt depending on the contents of the program counter on hardware. Therefore, in the conventional microprocessor, means such as inserting a necessary instruction into a designated address is taken by software control.

[0003]

In such a conventional microprocessor, as described above, the software control causes a necessary instruction to be inserted into a designated address and the like, so that the processor is out of control. When it happened, software control could not be used as a recovery means. Therefore, conventionally, a method such as adding external hardware such as a watchdog timer and resetting the above-mentioned processor when the watchdog timer is overtime has been adopted.
Therefore, there is a problem that the processor cannot be reset until the watchdog timer is overtime, and it takes time to return to the normal state.

It is an object of the present invention to provide a microprocessor which solves the above-mentioned problems and shortens the time required to return to a normal state.

[0005]

In order to achieve the above object, a microprocessor according to the present invention according to claim 1 comprises:
An execution unit that has a program counter and executes various processes in accordance with software instructions, one address register that holds address data according to an instruction from the execution unit, and the address data and the program that are held in this address register A comparator for comparing the contents of the counter and generating an interrupt to the execution unit in response to a match signal of the comparison result is provided.

According to a second aspect of the present invention, there is provided a microprocessor having a program counter, which executes various processes in accordance with software instructions, and a plurality of address registers which hold address data according to instructions from the execution section. And compare the address data held in these address registers with the contents of the program counter,
And a comparator for generating an interrupt when the content of the program counter is within the range of the address data of both address registers.

According to a third aspect of the present invention, there is provided a microprocessor having a program counter, which executes various processes in accordance with software instructions, and a plurality of address registers which hold address data according to instructions from the execution section. And compare the address data held in these address registers with the contents of the program counter,
And a comparator for generating an interrupt when the contents of the program counter are out of the range of the address data of both address registers.

According to the present invention, the value of the program counter in the execution unit and the address data set in the address register by the execution unit can be compared with each other, and the address data is exchanged between the value of the program counter and the address data. Since the interrupt is generated in accordance with either of the above, and the relationship between the address data being within or outside the range, the time required to return to the normal state can be shortened.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a microprocessor according to the present invention.

The microprocessor 1 shown in FIG. 1 comprises an execution unit 5 having a program counter (PC) 3, one address register 7, and a comparator 9. The execution unit 5 executes various processes in accordance with software instructions. The execution unit 5 can set address data, which is an interrupt generation address, in the address register 7 according to a software instruction. The output of the program counter 3 incorporated in the execution unit 5 is input to the comparator 9. The address data set in the address register 7 is input to the comparator 9. The comparator 9 compares the address data held in the address register 7 with the contents of the program counter 3, and an interrupt signal Sin is sent to the execution unit 5 by a match signal of the comparison result.
It is designed to generate t.

The operation of the embodiment of such a microprocessor will be described.

In the microprocessor 1, the execution unit 5
Writes the interrupt generation address in the address register 7 according to the software instruction. The interrupt generation address written in the address register 7 is compared with the value from the program counter 3 in the comparator 9. The comparator 9 gives an interrupt signal Sint to the execution unit 5 when a match is detected. Therefore, even when the software runs out of control, the program counter 3 is set to the interrupt generation address set in the address register 7.
When the value of reaches, the reset is applied and the return to normal is speeded up.

FIG. 2 is a block diagram showing another embodiment of the microprocessor according to the present invention.

The microprocessor 11 shown in FIG. 2 includes an execution unit 15 having a program counter (PC) 13,
Two address registers 17A and 17B and a comparator 19
It has and. The execution unit 15 executes various processes according to software instructions. The execution unit 15 can set the interrupt generation address data in the address register 17A and the interrupt end address data in the address register 17B according to the software instruction. The output of the program counter 13 is connected to the comparator 19. The outputs of the address registers 17A and 17B are connected to the comparator 19. The comparator 19 includes an address register 17
If the contents of the program counter 13 are included between the address data held in A and 17B, the interrupt signal Sint can be generated for the execution unit 15.

The operation of the other embodiment described above will be described.

In the microprocessor 1, the execution unit 5
Address register 17A according to the software instruction
The interrupt generation address is written in and the interrupt end address is written in the address register 17B. The interrupt generation start address written in the address register 17A and the interrupt generation end address written in the address register 17B are given to the comparator 19. These addresses are compared with the value from the program counter 13 in the comparator 19, and when the value from the program counter 13 is within the range of the interrupt generation start address and the end address, the interrupt signal Sint is generated. Therefore, even if the software runs out of control,
If the value of the program counter 13 is entered between the addresses set in the address registers 17A and 17B, the program counter 13 is reset to speed up the return to normal.

In the other embodiment described above, the comparator 1
9 is an interrupt signal Sint if the value of the program counter 13 is between the interrupt generation address and the interrupt end address set in the address registers 17A and 17B.
Is generated, the address register 17A, 1
The interrupt signal Sint may be generated when the value of the program counter 13 reaches outside the range of the interrupt generation address and the interrupt end address set in 7B.
According to such an embodiment as well, even if the software runs out of control, if the value of the program counter 13 reaches outside the range of the addresses set in the address registers 17A and 17B, the program is reset and the speed of returning to normal is increased. To be done.

[0019]

As described above, according to the first aspect of the invention, when the value of the program counter in the microprocessor coincides with the value of the address designated by software, an interrupt is issued to the microprocessor. Therefore, when the microprocessor runs out of control and tries to execute the non-program area, the interrupt processing routine is executed, and for example, there is an effect that the reset can be immediately performed.

According to the second aspect of the invention, when the value of the program counter in the microprocessor indicates within the range of the address designated by software, the microprocessor can be interrupted. When an attempt is made to run out of the non-program area due to a runaway, an interrupt processing routine is executed, and for example, resetting allows immediate return.

According to the third aspect of the present invention, when the value of the program counter in the microprocessor indicates that the value is out of the range of the address designated by software, the microprocessor can be interrupted. When an attempt is made to run out of the non-program area due to a runaway, an interrupt processing routine is executed, and for example, resetting allows immediate return.

According to the first, second or third aspect of the present invention, since the instructed address value is controlled by software, the address value can be set individually for software in different program areas. Moreover, there is an effect that the set value of the address can be changed on the way.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a microprocessor of the present invention.

FIG. 2 is a block diagram showing another embodiment of the present invention.

[Explanation of symbols]

 1 Microprocessor 3 Program Counter 5 Execution Unit 7 Address Register 9 Comparator 11 Microprocessor 13 Program Counter 15 Execution Unit 17A Address Register 17B Address Register 19 Comparator

Claims (3)

[Claims] 1. An execution unit having a program counter, which executes various processes in accordance with software instructions, one address register which holds address data according to an instruction from the execution unit, and an address register which is held in this address register. And a comparator which compares the address data with the contents of the program counter and generates an interrupt to the execution unit in response to a match signal of the comparison result. 2. An execution unit having a program counter for executing various processes in accordance with software instructions, a plurality of address registers for holding address data according to instructions from the execution unit, and an address unit held by these address registers. And a comparator which compares address data with the contents of the program counter and generates an interrupt when the contents of the program counter are within the range of the address data of the both address registers. .. 3. An execution unit having a program counter, which executes various processes in accordance with software instructions, a plurality of address registers for holding address data according to instructions from the execution unit, and an address unit held by these address registers. And a comparator which compares address data with the contents of the program counter and generates an interrupt when the contents of the program counter are out of the range of the address data of the two address registers. ..