JPH0378832A - Data processor - Google Patents

Abstract

PURPOSE:To effectively carry out a numerical comparison operation of a language process system by detecting such an inconvenient comparison arithmetic process where the comparison is carried out between the complex numerical values at execution of a condition branch instruction based on the deciding result of the data type of the complex numerical value at execution of a comparison arithmetic instruction and interrupting the process based on the comparison arithmetic process. CONSTITUTION:The data type of the complex numerical value is provided, and the data type of an operand forming a comparison arithmetic instruction is decided at execution of this instruction. If it is decided based on the deciding result that the data type shows the complex numerical value, a flag P of a condition flag register 11 is set. Then the conditions are satisfied to secure the coincidence between the executing result of the comparison arithmetic instruction and a condition mask designat ed by a condition branch instruction at execution of this instruction. At the same tims, the flag P is set. Under such conditions, a trap is outputted from an AND circuit 13 to interrupt a process. Thus, the comparison arithmetic instruction and the condition branch instruction can be prepared in the same way as a language process system having no data type of the complex number. Then the processing speed of a numerical comparison operation an be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a data processing device such as a LISP language processing system.

(Prior Art) Conventionally, in language processing type data processing devices having a function of indicating complex values as data types, there is a method in which the data type is determined at the time of executing an instruction. In such a method, when performing a comparison operation to compare the magnitude of numerical data, since the comparison of the magnitude of complex numbers has no mathematical meaning, it is necessary to perform a comparison operation that does not perform a magnitude comparison operation for complex numbers or is performed incorrectly. If this occurs, it is necessary to detect it and take appropriate action.

Conventionally, as shown in the flowchart of FIG. 3, when the magnitude comparison operation (step S3) is made into an independent processing unit, the process of detecting whether the data type of the operand is a complex number (step S1).

S2) is being performed. However, in the above-mentioned method, optimization processing that is common in language processing systems that do not have complex number data types, that is, processing that uses the result of one comparison instruction when executing multiple comparison instructions, for example. It becomes difficult to carry out.

(Problems to be Solved by the Invention) Conventional language processing devices that have the function of indicating complex values as data types have to perform magnitude comparison operations on complex numbers when performing comparison operations to compare the magnitude of numerical data. Processing that will not be executed is required.

For this reason, optimization processing that uses the result of one comparison instruction when executing multiple comparison instructions, for example, becomes difficult, and for language processing systems that do not have complex number data types,
The disadvantage is that the processing speed of numerical comparison operations is reduced.

An object of the present invention is to provide a data processing device that can efficiently execute numerical comparison operations in a language processing system that has a function of indicating complex values as a data type.

Configuration of invention C (Means and effects for solving the problem) The present invention has a function of indicating a complex value as a data type,
For example, in a data processing device of a LISP language processing system, where the data type is determined at the time of instruction execution, the data type of the operand is determined at the time of execution of a comparison operation instruction, and if the data type of at least one operand is a complex value, a condition code is generated. flag setting means to set a specific flag in the condition code register, and control to generate an interrupt signal (trap) to interrupt processing if a specific flag is set in the condition code register when executing a conditional branch instruction. It is a device equipped with means.

With this configuration, comparison operation instructions and conditional branch instructions can be arranged in the same way as in a language processing system that does not have a complex number data type, and as a result, it is possible to improve the processing speed of numerical comparison operations.

(Example) The present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a conditional branch control circuit used in a data processing apparatus according to the same embodiment. As shown in FIG. 1, the circuit of the same embodiment includes a sequencer 10 for controlling instruction execution cycles including interrupt processing. A condition code register (condition flag register) for holding the execution result of the comparison operation instruction 11, an instruction decoder 12 and an AND circuit 13 for decoding the instruction. Each logic gate circuit of the OR circuit 14 is provided.

In the condition flag register 11 of the same embodiment, in addition to the normally used flag Z (zero), flag N (negative), flag V (overflow), and flag C (carry occurrence), the data type of the operand is a complex value. A flag P for indicating that this is the case is stored.

Here, in the same embodiment, as shown in FIG. 2, a one-word data representation includes a tag section 20 indicating the data type (integer, complex number, etc.) and a pointer (address) of a value or other data structure. It consists of a data section 21.

Next, the operation of this embodiment will be explained. First, the data processing device of the present invention has a complex value data type, and when executing a comparison operation instruction, determines the data type of an operand that constitutes the instruction. As a result of this determination, if the data type of the operand (at least one of the plurality of operands) indicates a complex value, flag P in the condition flag register 11 shown in FIG. 1 is set. If the data type of any operand does not indicate a complex value, the flag P of the condition flag register 11 is in a reset state.

Here, the flag P is set to the other flags (C, V, N) of the condition flag register 11 when executing an arithmetic operation or the like.

It is updated (reset) at the same timing as 2).

Next, the conditional branch control circuit moves to execution of a conditional branch instruction that determines the next instruction based on the execution result of the comparison operation instruction. In executing this conditional branch instruction, the branch condition flags (flags C, V, and N excluding flag 2) referenced from the instruction decoder 12 are output to the OR circuit 14. That is,
A condition mask consisting of flags other than flag Z for determining the branch condition is specified in the instruction code of the conditional branch instruction. The branch condition flag is output from this OR circuit 14 to one input terminal of the AND circuit 13.

On the other hand, in the condition flag register 11, flags (C, V, N, Z) representing the execution results of the comparison operation instructions and flags P representing the determination results of the data type of complex values are set. Flags other than 7 lag Z of condition flag register 11 are as follows:
It is output to the other input terminal of the AND circuit 13. As a result, if the condition mask from the instruction decoder 12 matches and the flag P is set, the AND circuit 13 outputs a trap (interrupt signal) to interrupt the processing to the sequencer IO.

In this way, when the conditional branch instruction is executed, the condition that the execution result of the comparison operation instruction and the condition mask (branch condition flag) specified by the conditional branch instruction match is satisfied, and the flag P (specific flag) is If set, the AND circuit 13 outputs a trap for interrupting processing. This trap makes it possible to detect an inconvenient comparison operation process such as comparing the magnitudes of complex values, and to interrupt the process based on this comparison operation process.

[Effects of the Invention] As detailed above, according to the present invention, in a language processing system having a function of indicating a complex value as a data type, based on the determination result of the data type of the complex value when executing a comparison operation instruction, It is possible to detect an inconvenient comparison operation such as comparing the magnitude of complex values when executing a conditional branch instruction, and to interrupt processing based on this comparison operation.

Therefore, it is possible to eliminate the need for the conventional process of detecting the data type of a complex value when performing a comparison operation.

This makes it possible to perform optimization processing, such as using the result of one comparison instruction when executing multiple comparison instructions, and as a result, the numerical value of a language processing system that has the function of representing complex values as a data type. This allows comparison operations to be executed efficiently.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the configuration of a conditional branch control circuit according to an embodiment of the present invention, Fig. 2 is a conceptual diagram for explaining data expression in the embodiment, and Fig. 3 explains a conventional system. This is a flowchart for lO...Sequencer, 11...Condition code register, ■2...Instruction decoder.

Claims (1)

[Scope of Claims] A data processing device having a function of indicating a complex value as a data type and determining the data type at the time of executing an instruction, the data type of the operand being determined at the time of executing a comparison operation instruction, and at least one of the operands being determined. flag setting means for setting a specific flag of a condition code in a condition code register when the data type of an operand is a complex value; 1. A data processing device comprising: a control means for generating an interrupt signal for interrupting processing.