JPH05334099A - Write circuit for state setting register - Google Patents

Abstract

PURPOSE:To eliminate complicated work and to reduce possibility to generate an error by employing such configuration that interrupt is prevented from occurring when write on a state setting register and a spare memory area are performed. CONSTITUTION:This circuit is a write circuit provided with the state setting register 13 which sets the internal state of a device and the spare memory area 14 on which the same content is written to read the content of the state setting register 13, and for the state setting register of the device which performs the write on the spare memory area 14 following when the write is performed on the state setting register 13, and it is constituted so that the write on the state setting register 13 and the spare memory area 14 can be performed simultaneously. In other words, the write on the state setting register 13 and the spare memory area 14 can be performed simultaneously by the write circuit 30. Thereby, since the write on the state setting register 13 and that on the spare memory area 14 are not sequentially performed, it is possible to prevent discrepancy in the contents of the state setting register 13 and the spare memory area 14 due to the intrusion of the interrupt between the write on the state setting register 13 and that on the spare memory area 14 from occurring.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a state setting register write circuit for setting an internal state of a device.

[0002]

2. Description of the Related Art Conventionally, a microprocessor (hereinafter referred to as MP
A device controlled by abbreviated as U) employs firmware control using several interrupt levels as the processing becomes complicated. Moreover, such a device has a state setting register for setting the state of the hardware,
It has a status read register for reading the status of the hardware, and each can be written and read by the firmware.

FIG. 3 is a block diagram of a conventional device. In the figure, 11 is an MPU for controlling the apparatus. An address decoder 12 decodes and outputs the address signal of the address bus output from the MPU 11. 13 is a status setting register,
It sets the hardware status. Reference numeral 14 denotes a preliminary storage area in which the same contents are written to read the contents of the state setting register 13. Reference numeral 15 is a status reading register, which holds the status signal of the hardware and is read by the MPU.

In the apparatus shown in the figure, when setting the setting value of the state setting register 13, the value of the spare storage area 14 is read and MP
After changing the bit whose value is to be changed in U11, the value is written in the state setting register 13 and the preliminary storage area 14. Status setting register 13
The status read register 15 has a storage area and a series of addresses, and the spare storage area 14 is a part of the storage area assigned as a spare storage area, and has different addresses. Therefore, writing to the auxiliary storage area 14 must be performed serially with writing to the state setting register 13.

Conventionally, these processes have been performed by firmware. FIG. 4 is a processing flowchart when an interrupt occurs in the conventional device. The original process is step 81 → step 82
→ It is set to proceed to step 83 → step 84.

That is, in step 81, a copy "00000000" of the contents of the state setting register 13 is read from the preliminary storage area 14. Then, when the value of bit 0 is changed in step 82, "
In step 83, the content "00000001" is written in the state setting register 13. Then, in step 84, the same content is written in the spare storage area 14.

This completes the setting of the state setting register 13. However, there is a case where an interrupt with a higher priority occurs during steps 83 to 84, and another bit of the same state setting register 13 is changed in the process. This is a case where an interrupt occurs after step 83 in the figure and the process proceeds to step 91. At this time, the state of the process of step 83 is all saved, but the contents of the state setting register 13 are not saved. Step 91 in the interrupt process
The "00000000" which is a copy of the contents of the status setting register 13 is read from the preliminary storage area 14. Then, when the value of bit 1 is changed in step 92, it becomes "00000010". Step 93
Write the contents "00000010" to the status setting register 13 with. Then, in step 94, the same contents are written in the preliminary storage area 14. Then, the interrupt process is terminated, all the saved information is restored, and the process returns to the original step 84.

In step 84, the original content "00000001" is written in the spare storage area 14. When an interrupt occurs in this way, when the value of the bit changed during the interrupt process is written to the auxiliary storage area 14 after the interrupt is released, there is a bit set in the status setting register 13 during the interrupt process. Because I do not know that, I will return to the state before the interrupt processing occurred. Therefore, the status setting register 13
And the contents of the spare storage area 14 differ from each other, which causes a failure.

Therefore, conventionally, processing for further prohibiting interrupts has been performed. FIG. 5 is a processing flowchart when an interrupt is prohibited in the conventional device. That is, when setting the status setting register 13, the interrupt mask is set in step 80 to disable the interrupt. After that, the conventional processing is performed to write to the status setting register 13 and the spare storage area 14.
(Step 81 → Step 82 → Step 83 → Step 84)
.. When the writing is completed, the interrupt mask is released in step 85.

[0010]

Therefore, conventionally, in order to prevent such a situation from occurring, an interrupt mask for preventing an interrupt is set and then written to the state setting register 13 and the spare storage area 14. And then released the interrupt mask.

However, it is complicated to consider such a process each time a program is created, and an error of forgetting this process may be made. In view of such a point, the present invention has an object to provide a means for preventing an interrupt when writing to the state setting register and the spare storage area.

[0012]

The above problem can be solved by a write circuit of a state setting register configured as follows.

FIG. 1 shows the principle of the present invention. It has a state setting register 13 for setting the internal state of the device, and a spare storage area 14 for writing the same contents to read the contents of the state setting register 13, and when writing to the state setting register 13, it continues. A writing circuit of a state setting register of a device for writing to the spare storage area 14, which is configured to simultaneously write to the state setting register 13 and the spare storage area 14.

[0014]

Operation: The writing circuit 30 simultaneously writes to the state setting register 13 and the preliminary storage area 14.

As a result, the writing to the state setting register 13 and the spare storage area 14 is no longer sequentially processed, so an interrupt occurs between the writing to the state setting register 13 and the spare storage area 14, and the state setting register It is possible to prevent a discrepancy between the contents of 13 and the preliminary storage area 14.

[0016]

2 is a block diagram of an embodiment of the present invention, showing the details of a write circuit of a state setting register.
In the figure, 16 is a decoder for generating a signal designating the state setting register 13 and the spare storage area 14 from an address signal. At this time, the signal designating the state setting register 13 is logically ANDed with the R / W signal at the same time.

Reference numeral 17 denotes a timing pulse generation circuit, which generates a timing pulse for reading and writing based on a timing signal from the MPU.
In addition, the same reference numerals as those in FIG. 3 are the same.

In the embodiment of the present invention, the addresses of the state setting register 13 and the spare storage area 14 are made the same. When reading the value of the preliminary storage area 14 in order to change the setting value of the state setting register 13, the MPU 11 outputs the address of the preliminary storage area 14 and puts the R / W signal R into the read state. The decoder 16 generates a signal for selecting the state setting register 13 and the spare storage area 14 from the address signal A and the R / W signal R of the address bus. In this case, the status setting register
The signal for selecting 13 is not output.

The timing pulse generation circuit 17 which receives the timing signal T and the selection signal SS of the spare memory area 14 sends a timing pulse to the spare memory area 14, and the spare memory area 14 receives the address signals A and R / W of the address bus. Upon receiving the signal R and the timing pulse from the timing pulse generation circuit 17, it operates and reads, and the read output is output to the data bus M
Sent to PU11.

When the MPU 11 changes the read contents of the preliminary storage area 14 and then writes them in the state setting register 13 and the preliminary storage area 14, the MPU 11 outputs the address of the preliminary storage area 14 and puts the R / W signal into the write state. Then, the information to be set is transmitted from the data bus, and the timing signal T is transmitted.

In the decoder 16, the address signal A and R / W
A selection signal for the state setting register 13 and the preliminary storage area 14 is generated from the signal R, and the timing pulse generation circuit 17 sends respective timing pulses to the state setting register 13 and the preliminary storage area 14. Therefore, the status setting register 13 uses the data signal D of the data bus and the timing pulse generation circuit 17
It operates by receiving the timing pulse from and writes.

The spare memory area 14 also receives the address signal A of the address bus, the R / W signal R, the data signal D of the data bus, and the timing pulse from the timing pulse generating circuit 17 and writes to the designated address.

As a result, the data is written into both the state setting register 13 and its spare storage area 14 at the same time. If the status setting register 13 and the spare storage area 14 are simultaneously written as described above, there is no possibility that an interrupt will occur in the middle and the contents of the two will not conflict with each other.

It is needless to say that the coincidence at this time does not have to be physical coincidence at all and is coincidence within a range where an interrupt does not enter. Here, the same configuration can be realized when there are a plurality of status setting registers and a plurality of status reading registers.

Further, in the present embodiment, the addresses of the state setting register and the spare storage area are the same, but it is not always necessary that they be the same, and it is needless to say that it is possible to write simultaneously.

[0026]

As is apparent from the above description, according to the present invention, by providing the state setting register and the means for preventing the interruption when writing to the spare storage area,
It has a remarkable industrial effect of eliminating the complicated work to be taken into consideration when creating a program and eliminating the possibility of causing errors.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a configuration diagram of a write circuit according to an embodiment of the present invention.

FIG. 3 is a block diagram of a conventional device

FIG. 4 is a processing flowchart when an interrupt occurs in a conventional device.

FIG. 5 is a processing flowchart when interrupts are prohibited in a conventional device.

[Explanation of symbols]

11 MPU 12 Address Decoder 13 State Setting Register 14 Preliminary Storage Area 15 State Reading Register 16 Decoder 17 Timing Pulse Generation Circuit 80-85, 91-94 Operation Step

Claims (1)

[Claims] 1. A state setting register (13) for setting an internal state of a device, and a spare storage area (14) for writing the same content to read the content of the state setting register (13),
A write circuit of the state setting register of the device which, when writing to the state setting register (13), continuously writes to the spare storage area (14), is a write circuit of the state setting register (13) and the spare A writing circuit for a status setting register, which is characterized in that writing to the storage area (14) is performed at the same time.