JPH06222960A - Cpu reset circuit - Google Patents

Abstract

PURPOSE:To improve efficiency for using a CPU by eliminating necessity to use any special program for cyclically resetting a watchdog timer (WDT) in the CPU reset circuit provided with a WDT function. CONSTITUTION:An address (reference address) to be surely accessed as long as a program is normally operated is previously set to a reference address set circuit 51. An address comparator circuit 52 compares the access address under program execution of a CPU 1 with the reference address, when they are equal to each other, a reset pulse 15 is generated, and a reset circuit 8 with timer is reset. When the timer is not reset by the reset pulse 15 before the time-up of the timer in this reset circuit 8, a CPU reset signal 18 is generated by time-up, the CPU 1 is reset, and run-away is eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU reset circuit, and more particularly to a CPU reset circuit having a watchdog timer function for resetting the CPU when the CPU malfunctions or runs out of control.

[0002]

2. Description of the Related Art A CPU reset method using a watchdog timer is known as a means for monitoring an abnormal operation such as CPU runaway. A conventional circuit block of this type of CPU reset system is shown in FIG. The CPU 1 is a target of abnormal operation monitoring by the CPU reset circuit 3, and the CPU 1 and the peripheral circuit 2 are interconnected by a data bus 10, an address bus 11, and a control signal bus 12.

The configuration of the CPU reset circuit 3 will be described. The power-on reset circuit 4 generates a power-on reset signal 16 when the power is turned on, and the timer reset pulse generation circuit 5 generates a timer reset pulse 15 in response to a control command from the CPU 1. The OR gate 7 uses these power-on reset signal 16 and timer reset pulse 1
5 and 2 are two inputs, and the timer reset signal 17 is generated when at least one of the two inputs is generated.

The timer-equipped reset circuit 8 is reset by the timer reset signal 17 and generates a reset signal 18 when the reset signal 17 is not generated and time is up, and has a watchdog timer function. The OR gate 9 receives the reset signal 18 and the power-on reset signal 16 as two inputs, and generates the CPU reset signal 19 when at least one of the two inputs is generated.

In such a configuration, when the power is turned on and the power is turned on, the power-on reset circuit 4 outputs the power-on reset signal 16, and the CPU 1 and the reset circuit with timer 8 are both in the initial reset state.

A timer reset pulse generator 8 periodically resets the timer reset circuit 8 by inserting a program into the program to be executed so that the timer reset pulse generator 5 periodically generates the reset pulse 15. It Therefore, at this time, by setting the time-up value of the timer-equipped reset circuit 8 longer than the generation period of the reset pulse 15, the timer-equipped reset circuit 8 does not time-up unless the CPU 1 runs out of control. , The reset signal 18 is not generated.

When the CPU 1 goes out of control due to disturbance or the like and the reset pulse 15 is no longer periodically output from the timer reset pulse generation circuit 5, the timer-equipped reset circuit 8 times up, so a reset signal 18 is output and the CPU 1 It will be in the reset state and will be forcibly returned to the normal processing routine.

[0008]

[Problems to be Solved by the Invention] Such a CP as described above
The U reset circuit has a drawback in that, because of the watchdog timer function, a processing program for periodically resetting the timer-equipped reset circuit must be inserted in the original program. Further, since the CPU needs to execute this processing program, there is a drawback that the processing efficiency of the CPU is reduced.

Therefore, the present invention has been made to solve the above-mentioned drawbacks of the prior art, and its purpose is to eliminate the need for a program for the watchdog timer function other than the original program, and to perform CPU processing. It is to provide a CPU reset circuit capable of improving efficiency.

[0010]

According to the present invention, there is provided a CPU reset circuit having a watchdog timer function for discriminating whether or not a program is periodically executed, which is always accessed when the program is normally executed. A reference address setting means for presetting a reference address to be set,
A match signal generation unit that outputs a match signal when the access address at the time of executing the program is compared with the reference address and a match signal is generated, and a power-on reset unit that generates a power-on reset signal in response to power-on. And reset means with a timer that is reset by at least one of the coincidence signal and the power-on reset signal and that generates a reset signal at the time-up,
A CPU reset circuit is obtained which includes means for resetting the CPU by at least one of the reset signal and the power-on reset signal.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and the same parts as those in FIG. 2 are designated by the same reference numerals. The difference from FIG. 2 is that the timer reset pulse generation circuit 5 includes a reference address set circuit 51 and an address comparison circuit 52.

The reference address setting circuit 51 includes a CPU 1
In response to a command (12) from (1), a reference address (which means an address that is always accessed as long as the program operates normally) is set via the address bus 11. The address comparison circuit 52 fetches the address accessed during the program running from the address bus 11 in response to the address latch signal 13 from the CPU 1 and compares it with the reference address 14, and both addresses 13 and 14 match. Reset pulse 1
5 is generated.

The other structure is the same as that of FIG. 2 and its explanation is omitted.

In this configuration, when the circuit is powered on, the power-on reset signal 16 from the power-on reset circuit 4 causes the CPU 1 and the timer-equipped reset circuit 8 to be initially reset. The reference address is set in the reference address setting circuit 51 immediately after the CPU 1 is initially reset by the power-on reset signal.
It is performed under the control of the CPU 1.

As described above, as the reference address, an address that always passes as long as the program is operating normally is used. Generally, a program to be executed is repeatedly executed in a loop. In a program including a conditional branch instruction, the address of the instruction returning from the branch destination may be used as the reference address.
This is because this address is the address of the instruction that must be executed regardless of whether the conditional branch is taken.

The address comparison circuit 52 compares the reference address 14 with the access address of the execution program,
When they match, the reset pulse 15 is generated. Therefore, the reset circuit with timer 8 is reset by the reset signal 17 that passes through the OR gate 7 of the reset pulse 15, so that the reset circuit with timer does not time up. That is, as long as the CPU 1 is operating normally, the reset circuit 8 with timer is periodically reset by the reset pulse 15 of the address comparison circuit 52 before the time is up, and the reset signal 18 is not generated.

However, if the CPU 1 runs out of control due to a disturbance or the like, the CPU 1 will not access the reference address within the time-up period of the reset circuit with timer 8.
Therefore, the reset circuit with timer 8 times up and generates the reset signal 18, and the CPU 1 is reset.

[0019]

As described above, according to the present invention, it is not necessary to previously incorporate a special program for the watchdog timer function into the program to be executed, thus improving the processing efficiency of the CPU. There is an effect of doing.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a conventional CPU reset circuit.

[Explanation of symbols]

 1 CPU 2 Peripheral circuit 3 CPU reset circuit 4 Power-on reset circuit 5 Timer reset pulse generation circuit 7, 9 OR gate 8 Reset circuit with timer 51 Reference address set circuit 52 Address comparison circuit

Claims (1)

[Claims] 1. A CP having a watchdog timer function for determining whether or not a program is periodically executed.
It is a U reset circuit, and a reference address setting means for presetting a reference address that is always accessed when the program is normally executed is compared with an access address at the time of execution of the program and the reference address is matched. Match signal generating means for outputting a match signal to,
Power-on reset means for generating a power-on reset signal in response to power-on, and reset means with a timer that is reset by at least one of the coincidence signal and the power-on reset signal and generates a reset signal at the time-up A CPU reset circuit comprising: means for resetting the CPU by at least one of the reset signal and the power-on reset signal.