JPH0250233A - Computer abnormality processing system - Google Patents

Abstract

PURPOSE:To attain the high speed restarting of a system by informing a condition that abnormality is generated in a computer and sys end dump processing following the generation is finished to an external part. CONSTITUTION:A dump end processing means 23 to generate a dump ending signal MEND when the sys end dump processing is finished and a condition holding means 27 to execute condition transition when the dump ending signal goes to be true are provided. Then, in order to inform the end of the sys end dump processing to the external part, an output signal DEND of this condition holding means 27 is outputted out of the computer. When a dump practical end signal EEND from an error detecting means 24, which detects an error in the sys end dump processing and generates the dump practical end signal to show the practical end of the dump processing, is also true, the condition transition is executed to the condition holding means 27. Thus, even when an initializing request is immediately outputted from the external part to the computer in correspondence to the dump end announcement, since memory contents are kept, the high speed restarting of the system can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a computer abnormality processing method suitable for when an abnormality occurs in a computer.

(Prior art) Conventionally, in a computer system as shown in FIG.
(2) Initialization of the CPU II when an abnormality occurs is generally performed as follows.

First, the state of the CPU II is an online state where the CPU II normally operates (CPU operating state, CPU operating state), and when an abnormality occurs, the contents of the main memory (not shown) in the CPU II are saved in the external storage 12 (so-called Perform system end dump processing) System end dump status (CPU
There is a state in which the CPU II is in a processing state but not in an operating state that can be used by the user), and an offline state in which the CPU II has stopped operating. C that is online
When an abnormality occurs in the PUII, the online signal 0NLINE output from the CPUII (indicating whether the CPUII is in a normal operating state) changes from true (1°) to false (1°) as shown in the timing chart of Figure 8. “0”)
Transition to. These signals 0NLI and NE are led to the control panel 13, and when the signal 0NLINE changes to false, the control panel 13 makes the external initialization signal EXTINZ true as shown in FIG. 8, and initializes the CPU II. make a request. Signal EXTI from control panel 13
NZ is delayed for a certain period of time by the delay circuit 14 and is transmitted to the CPU II as an initialization signal INZ.

Upon receiving this initialization signal INZ, the CPU 11 starts initialization.

Now, the CPU II enters the system end dump state as shown in FIG. 8 from the time when the online signal 0NLINE becomes false, and when the dump (the operation of saving the main memory contents to the external storage 12) is completed, it enters the offline state.

Therefore, during the period when the CPU II is in the system end dump state, the above initialization signal INZ is sent to the CPU II.
If this is transmitted, there will be an inconvenience that initialization will be performed before the system end dump (SYSEND process) for saving the main memory contents is completed. Therefore, conventionally, in order to prevent the initialization signal EXTINZ indicating an initialization request from the control panel 13 from being transmitted (as the initialization signal INZ) to the CPU II before the end of the system end dump, this signal is delayed as described above. It is delayed by circuit 14.

Now, the time required for a system-end dump of the CPU is determined by the capacity of the main memory, the speed of external storage, etc. However, the capacity of main memory, the speed of external storage, etc. differ depending on the system, and therefore the time required for system end dump also differs depending on the system. For this reason, the control panel,
Even if the initialization signal from the CPU is delayed as described above, depending on the system, the CPU
A problem arises in that the main memory contents are initialized and all saved main memory contents are destroyed. Furthermore, in order to solve this problem, it may be possible to set a sufficiently long delay time, but with this method, a new problem arises in that restarting the system is delayed.

(Problems to be Solved by the Invention) As mentioned above, in the conventional method, when a computer (CPU) abnormality occurs, an initialization request given from the outside is delayed for a certain period of time by a delay circuit and then transmitted to the computer. If the system requires a long time to save a system end dump, there is a problem that the computer will be initialized during the system end dump, and if the delay time is set long enough, the initialization after the system end dump will be Although this is guaranteed, there is a problem in that restarting the system is delayed.

Therefore, this invention notifies the end of a dump to the outside according to the processing status of a sysend dump inside a computer when an abnormality occurs in the computer (CPU), so that the sysend dump processing time is optimal for each system. The problem to be solved is to be able to transmit an initialization request from the outside to a computer at the appropriate timing.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a dump completion processing means that generates a dump completion signal indicating the end of system end dump processing;
A state holding means that makes a state transition when the dump end signal from the dump end processing means becomes true is provided, and the output signal of this state holding means is used to externally notify the end of the system end dump processing to an external device. The feature is that the output is made as follows. The present invention also provides error detection means for detecting an error during system end dump processing and generating a dump substantial end signal indicating the substantial end of the dump processing; The present invention is characterized in that it further includes gate means for causing the state holding means to undergo a state transition in the same way as when the dump end signal becomes true even when the dump end signal becomes true.

(Function) According to the above configuration, if an abnormality occurs in the computer and the subsequent system end dump processing ends normally (if an error detection means and gate means are provided, an abnormality occurs during the system end dump). (including the case where the system end dump is treated as completed), the state holding means undergoes a state transition, and this fact (system end dump completed) is notified externally.

Therefore, even if an initialization request is immediately issued from the outside to the computer in response to this system-end dump completion notification, and the request is directly transmitted to the computer and initialized without delay as in the past, at this time, the system-end Since the dump has finished and the memory contents have been saved, the same problem will not occur and the system can be restarted quickly.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

Figure 1 shows a microprogram-controlled computer (CPU).
) is a block configuration diagram showing extracted portions directly related to the present invention. In the figure, 21 is a control memory in which various microprograms are stored, and 22 is a sysend dump which is a machine language instruction (user instruction) that is executed (taken out from the main memory (not shown)) at the end of the sysend dump process. Termination processing instruction (hereinafter referred to as DEND instruction), 23
is taken out from the control memory 21 by the execution of the DEND instruction 22, and is used to generate the signal MEND (dump end signal, A at "1") indicating the end of the sysend dump (hereinafter referred to as the MEND microinstruction). It is.

24 is an error detection circuit that detects various errors such as program stalls and hardware errors (deadlock state) and outputs an error signal E (true at 1°); 25 is C
This is an AND gate (AND) that allows output of the error signal E from the error detection circuit 24 when the online signal ONLINE indicating whether or not the PU is in the online state is "0" (false). The output of the AND gate 25 is a signal EEN indicating that the sys-end dump has substantially ended.
It is used as D (dump effective end signal, true at "1"). 26 is an OR gate (OR) for ORing the signal MEND and the signal EEND; 27 is set according to the output signal of the OR gate 26, and outputs the signal DEND (A at "1") indicating the end of the sysend dump. This is a flip-flop (F/F) for output.

Next, the operation of the configuration shown in FIG. 1 will be described with reference to the timing chart shown in FIG. 2 in the case where a system end dump due to a CPU abnormality is normally completed.

When an abnormality occurs in the CPU shown in Figure 1, the online signal 0
NLINE changes from “1” (true) to “0” as shown in Figure 2.
Transition to ° (false). At this time, the CPU transits from the online state to the system end dump state, and a system end dump process is started for saving the contents of the main memory (not shown) in the CPU to external storage. At the end of this system end dump process, the DEND instruction 22 is taken out from the main memory and executed. By executing the DEND instruction 22, the MEND microinstruction 23 is retrieved from the control memory 21, and this MEND microinstruction 23 causes the logic to be output (from a microinstruction decoder (not shown) or a specific bit of the MEND microinstruction 23) as shown in FIG. “1” signal MEN
D is generated. As a result, the output signal of the OR gate 2B transitions to "1", thereby setting the flip-flop 27. When the flip-flop 27 is set, the logic "1" signal DE is output from its Q output as shown in FIG.
ND is output and the system end dump processing (processing to save the contents of the CPU's main memory) is completed externally (for example, from the control panel).
will be notified.

Next, a case where an error occurs during a system end dump due to a CPU abnormality will be described with reference to the timing chart of FIG.

Errors such as program stalls and hardware errors (deadlock state) occur during the period when the system end dump process is being performed due to an abnormality occurring in the CPU as shown in Figure 1.
It is assumed that this fact has been detected by the error detection circuit 24. In this case, the error detection circuit 24 outputs an error signal E of logic 1°. Error signal E from error detection circuit 24 is guided to AND gate 25. The AND gate 25 indicates that the CPU is in the sysend dump state as in this embodiment, and therefore the online signal ONL I
If NE is 00'', the error signal E from the error detection circuit 24 is output as is to the orgate 28 as the signal EEND (indicating that the sysend dump is treated as finished because an error occurred during the sysend dump). As a result, the output signal of the OR gate 26 transitions to m12,
This causes flip-flop 27 to be set. When the flip-flop 27 is set, the logic m1m signal DEND is output from its Q output as shown in FIG. 3, and the end of the sys-end dump process is notified to the outside.

The logic “1° signal D is output from the flip-flop 27 of the CPU.
For example, the external control panel that received END (control panel 1 in Figure 4)
3) immediately outputs an initialization request to the CPU if necessary. At the time this initialization request is output, the one-system end dump processing due to the occurrence of a CPU abnormality has essentially ended (including when an error occurs during the system end dump), so the initialization request is Even if the initialization process is performed by directly transmitting the data to the CPU (without being delayed by a delay circuit and then transmitting the data to the CPU), there is no problem.

In the above embodiment, the Q output signal of the flip-flop 27 that is set upon completion of the sysend dump process, that is, the signal DEND indicating whether or not the CPU is in the sysend dump completion state, is used to determine the end of the sysend dump process. Although the case where the termination is notified to the outside (control panel, etc.) has been described, the present invention is not limited to this. For example, a signal (this signal is called ALIVE) indicating whether the CPU is in a processing state (i.e., in a normal operating state, in a normal system end dump processing state, or in neither state) It is also possible to externally notify the end of system end dump processing. This notification method will be explained below with reference to the block diagram of FIG. 4 and the timing charts of FIGS. 5 and 6. In the configuration of FIG. 4, the same parts as in FIG. 1 are given the same reference numerals.

In the configuration shown in FIG. 4, reference numeral 31 indicates an operation start processing instruction (hereinafter referred to as A
(referred to as the LIVE instruction). This AL IV
When the E instruction 31 is executed, the AL I
MAL I VE corresponding to VE instruction 31? The microinstruction 32 is taken out, and based on the microinstruction 32, a signal MALIV of logic "11" is generated as shown in FIGS. 5 and 6.
E is generated. This signal MALIVE is supplied to the S input of flip-flop 33, thereby setting flip-flop 33. When the flip-flop 33 is set, the CPU processing signal ALIVE of logic "1" is output from its Q output as shown in FIGS. 5 and 6, indicating that the CPU is in the processing state (online signal ONL).
Not only the operating status of INE "1@, but also the normal processing status of system end dump" is notified to the outside.

Now, when the operation (operation) of the CPU is started and an abnormality occurs in the CPU during the operation, the signal 0NLINE becomes "0" and the system end dump process is started as described in the above embodiment.

Then, when this system end dump processing is completed, the first
The DEND instruction 22 is executed in the same manner as in the configuration shown in the figure. As a result, the MEND micro-instruction 23 corresponding to the DEND instruction 22 is retrieved from the control memory 21, and based on this MEND micro-instruction 23, the logic 1 degree signal MEND is generated as shown in FIG. The signal MEND is supplied to the OR gate 2B as described in the previous embodiment, and as a result, the output signal of the OR gate 2B transitions to logic -°1''.

The output signal of the OR gate 2B is as shown in FIG.
(different from the configuration shown in the figure) is supplied to the R input of the flip-flop 33, so that the flip-flop 33 is reset at the end of the sysend dump process. When the flip-flop 33 is reset, the signal A which is its Q output signal
As shown in Figure 5, LIVE transitions from logic "1" to logic #0, and the CPU is in the processing state (ALIVE state).
The external device is notified that the system has transitioned from the state to the DEAD state, that is, that the system end dump processing has ended. The subsequent operations are similar to those in the previous embodiment.

On the other hand, during the period when the system end dump process is being performed, an error is detected by the error detection circuit 24, and the circuit 2
When the logic "1" error signal E is output from the AND gate 25, the logic "1" signal EEND indicating the substantial end of the sysend processing is outputted from the AND gate 25 as shown in FIG. Output. The signal EEND is supplied to the OR gate 2B as described in the previous embodiment, and as a result, the output signal of the OR gate 26 transitions to logic "1".

When the output signal of the OR gate 26 transitions to logic "1",
The flip-flop 33 is reset in the same way as when the system end dump process is normally completed, and the signal AL I VE, which is the Q output signal, becomes logic "1" as shown in FIG.
to logic “0”.

[Effects of the Invention] As detailed above, according to the present invention, when an abnormality occurs in a computer and the subsequent system end dump processing is completed (or when an abnormality occurs during a system end dump and the system end dump (in the event that the transaction is deemed to have ended), that fact will be notified to the outside in place of the conventional online signal. Therefore, even if an initialization request is immediately issued to the computer from the outside in response to the completion notification of the system end dump process, and the time required for the system end dump, which differs from computer to computer, is not taken into consideration, the initialization request is directly sent to the computer and initialized. ,
At this time, the system end dump in the computer has been completed and the memory contents have been saved, so the same problem does not occur and the system can be restarted quickly.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing an embodiment of the present invention, FIGS. 2 and 3 are timing charts for explaining the operation when a computer abnormality occurs in the configuration of FIG. 1, and FIG. 2 is a system diagram. FIG. 3 is a timing chart when an end dump ends normally; FIG. 3 is a timing chart when an error occurs during system end dump; FIG. 4 is a block configuration diagram showing another embodiment of the present invention; FIG. 6 is a timing chart for explaining the operation when a computer abnormality occurs in the configuration shown in FIG. 4, FIG. 5 is a timing chart when the system end dump ends normally, and
The figure is a timing chart when an error occurs during a system end dump, FIG. 7 is a block diagram showing a conventional example, and FIG. 8 is a timing chart for explaining the conventional operation when a computer abnormality occurs. 21...Control memory, 22...System end dump termination processing instruction (DEND instruction), z4...Error detection circuit, z5...And gate (AND) 2G...Or gate (OR), 27.33 ...Flip-flop (F/F), 31...Operation start processing command (ALJVE)
order). Fig. 1 Fig. Fig. Fig. Fig. 4 Fig. Fig. CPU expenses incurred ↑ Ini 5V line closed woman 6 No. 81! f

Claims (2)

[Claims] (1) In a computer system in which the computer performs sys-end dump processing that saves the contents of the main memory of the computer to external storage when a computer error occurs, a notification to that effect is sent to the computer at the end of the sys-end dump process. a dump end processing means for generating a dump end signal indicated by the dump end processing means; and a state holding means for making a state transition when the dump end signal from the dump end processing means becomes true, and the output signal of the state holding means is A computer abnormality processing method, characterized in that the computer abnormality processing method is configured to output an output signal to the outside of the computer, and notify the end of the system end dump processing to the outside by a state transition of the output signal. (2) The computer includes an error detection means for detecting an error during the system end dump processing and generating a dump substantial end signal indicating the substantial end of the dump processing, and a dump substantial end signal from the error detection means; The computer abnormality according to claim 1, further comprising gate means for causing the state holding means to undergo a state transition when either one of the dump end signals from the dump end processing means becomes true. Processing method.