JPS60229141A - Preserving system of register data - Google Patents

Abstract

PURPOSE:To restart execution of a microprogram after stopping temporarily the execution and extracting the contents of a register, by preserving the contents of the register by a support program when the execution of the program is stopped temporarily. CONSTITUTION:An address to be stopped of a microprogram executed by a central processor 100 is written to an address matching register 5 from a support processor 200. Then the processor 100 executes a microprogram stored in a control memory 1. A microprogram sequencer 3 applies an address to read the microprogram out of the memory 1 and execute it. This address data is also supplied to a comparator 6 and compared with the contents of the register 5. When the coincidence is obtained, an output is delivered to a control circuit 4 and the processor 200. The coincidence signal sent to the circuit 4 stops temporarily by working of the sequencer 3. The processor 200 delivers the start address of a support program S to send the contents of registers 11 and 12 to an internal memory 13.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a register data storage system in a computer controlled by a microprogram.

[Technical background of the invention and its problems] Conventionally, when depacking a program in a computer controlled by a microprogram, the execution of the microphone program is temporarily interrupted in the middle of execution, and the various components that make up the computer are It is very useful and convenient to be able to examine the contents of registers.

Therefore, in the past, as a means of temporarily stopping the microprogram being executed and checking the contents of various registers, an address match was performed on the address at which the microprogram was to be stopped, and the contents of the various registers at this time were written to the main memory. This was done by doing this. However, since this method uses the main memory, it is necessary to reserve an area for storing registers in the main memory. This has the disadvantage that when the microprogram is executed again, it cannot be resumed from the point where the microprogram was previously stopped because the registers that are used, such as data registers and address registers, change.

[Object of the Invention] In view of the above drawbacks, an object of the present invention is to temporarily interrupt the execution of a microprogram, retrieve the contents of various registers, and then restart the execution of the microprogram from the point where it was interrupted. The purpose of this invention is to provide a method for storing data in registers that allows for the storage of register data.

Summary of the Invention] The present invention provides a microprogram control computer that reads and executes a microprogram stored in a control storage device using a microprogram sequencer, and has an internal memory that saves the contents of various registers when the microprogram is stopped. After setting the stop address of the microprogram using the support program stored in the control storage device, the contents of various registers are transferred to the internal memory when the microprogram is stopped, and the data once saved in this internal memory is imported. After that, a support processor that re-executes the microprogram, an address match register that holds the stop address of the microprogram set by the support processor,
a comparator that compares the microprogram read address output from the microprogram sequencer with the address held in the address match register and outputs a match signal; and a comparator that outputs a match signal between the two; The above object is achieved by providing a circuit that allows a support processor to set a read address in a microprogram sequencer.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a schematic configuration of a computer controlled by a microprogram to which the register data storage method of the present invention is applied. The computer is composed of a central processing unit (CPU) 100 and a support processor (Sp) 200.

FIG. 2 is a block diagram showing an embodiment of the central processing unit 100 shown in FIG. The central processing unit 100 is composed of the parts described below. Reference numeral 1 denotes a control storage device in which a microprogram is stored, and a support program S for saving the contents of registers in an internal memory (described later) is also stored in this storage device. Reference numeral 2 denotes a register (
CDR>, numeral 3 is a microprogram sequencer (μm5EQ) that controls the execution of microprograms. Reference numeral 4 is a control circuit (CONT> that controls the microprogram sequencer 3, and reference numeral 5 is an address match register (AMR>) that holds an address when applying an address match to the microprogram. Reference numeral 6 is a control circuit (CONT>) that controls the microprogram sequencer 3. A comparator (COMP>) compares the contents with the address for control storage output from the microprogram sequencer 3, and the reference numeral 7 selects the direct address input from the support processor 200 and the address from the address match register 5. This is a multiplexer. Reference numeral 8 is a multiplexer that selects either the address from multiplexer 7 or the address field of register 2. Reference numeral 9 is a decoder that inputs the signal from register 2 and performs various controls. Reference numeral 10 is Arithmetic unit M,
(ALU>, symbols 11 and 12 are various registers.

Reference numeral 13 is an internal memory (IM>) that stores the contents of various registers 11 and 12 when an address match occurs in the microprogram, and reference numeral 14 is an address register (TMAR) that specifies the address of the internal memory. Reference numeral 15 is a multiplexer that selects either data from the support processor 200 or data sent through the pass line (back; [) 72 of the central processing unit 100.

Next, the signal lines forming the central processing unit 100 will be explained. Reference numeral 40 is a signal line for transmitting microinstructions from the control memory 1 to the register 2. code 4
1 is a signal line that transmits the address part of register 2 to one input of multiplier 8, and 42 is a signal line that transmits the address part of register 2
This is a signal line that transmits the output signals of the decoder 9 to the decoder 9 as various control signals.

Reference numerals 43, 44, 45, 46, 47 are signal lines for transmitting output signals from the decoder 9 to the arithmetic unit 10, various registers 11, 12, internal memory 13, and address register 14. Reference numeral 50 is a signal line that transmits the address of the microprogram sequencer 3 to the control storage device 1 and also transmits it to one input of the comparator 6 as comparison data of an address match. A signal line 51 transmits the address from the address match register 5 to the other input of the comparator 6 and also to one input of the multiplexer 7.

Reference numeral 52 transmits a signal generated by the comparison result of the comparator 6 to the control circuit 4.

This is a signal line for transmitting to the support processor 200. Reference numeral 53 is a signal line for transmitting the address from multiplexer 7 to the other input of multiplexer 8.

Reference numeral 54 is a signal line for transmitting the address from the multiplexer 8 to the microprogram sequencer 3, and reference numeral 55 is a signal line for transmitting the output signal of the control circuit 4 to the microprogram sequencer 3. code 6
0.61.62 is a signal line from the support processor 200, the signal line 60 transmits a control signal to the multiplexer 7, the multiplexer 8, and the control circuit 4, and the signal line 61 transmits an address for address match to the address match register 5. At the same time, the start address of the support program is transmitted to the microprogram sequencer 3 via the multiplexer 7.8, and the signal line 62
is the address for reading the internal memory 13 of the CP IJ 100 from the support processor 200 through the multiplexer 15 and the address register 14.
This is a signal line that transmits signals to the

Reference numerals 10, 71, and 72 are pass lines for inputting and outputting data to the arithmetic unit 10, and pass lines 70, 71 input the contents of various registers 11, 12 to the arithmetic unit 10,
The pass line 12 is for sending the calculation results of the calculation device 10 to various registers 11, 12 and the internal memory 13. Reference numeral 73 indicates the contents of the internal memory 13 (data in various registers 11 and 12 when an address match occurs) in the support processor 2001. : This is the signal line to send. code 74
is a signal line that transmits an execution completion signal from the decoder 9 to the support processor 200.

Next, a description will be given of an operation in which the central processing unit 100 of this embodiment temporarily suspends the execution of a microprogram during execution, checks the contents of various registers, and then causes the microprogram to be executed again. First, from the support processor 200, the central processing unit 10
The address at which the microprogram executed by 0 is to be stopped is sent to the address match register 5 through the signal line 61, and the address at which the microprogram is to be stopped is written in advance in this address match register 5. Thereafter, the central processing unit 100 executes the microprogram in the control storage device 1. The microprogram sequencer 3 provides the control memory 1 with an address for reading a microprogram from the control memory 1 and causing it to be executed through a signal qn 50. This hetress data is also output to one side of the comparator 6 at the same time. Since the contents of the rear address match register 5 (the address at which the microprogram is to be stopped) are given to the other input of the comparator 6 through the signal line 51, the comparator 6 receives the execution address of the microprogram and the address at which the microprogram is to be stopped. Detect a match with the desired address. When the comparator 6 detects an address match, the comparator 6 sends a match signal through the signal line 52 to the control circuit 4 that controls the microprogram sequencer 3 and to the support processor 200.
The coincidence signal sent to the control circuit 4 is used to temporarily stop the operation of the microprogram sequencer 3, and when the coincidence signal is sent to the support processor 200, it is stored in the control storage device 1. The start address of the port program S is output from the 1-port processor 200 to the other input of the multiplexer 7 through the signal line 61 in order to run the support program S which is executed and sends the contents of the various registers 11 and 12 to the internal memory 13. At the same time, a control signal is outputted to the multiplexer 7.8 and the control circuit 4 through the signal line 60. The address data outputted through the signal line 61 is sent to the microphone Dgram sequencer 3 via the multiplexer 7, signal line 53, multiplexer 8, and signal line 54 according to the control signal outputted through the signal line 60 to start the support program. Set as address. When the start address of the support program is set in the microprogram sequencer 3, the support processor 200 sends a command to cancel the operation stop of the microprogram sequencer 3 to the control circuit 4 through the signal line 60. Then, this control circuit 4
As a result, the temporary stop of the microprogram sequencer 3 is canceled and the support program S in the control storage device 1 starts running.

Read from control memory 1 or port 10g S
microinstructions are held in register 2 through signal line 40. The microinstruction held in register 2 is
The signal is input to the decoder 9 through the signal line 42, where it is converted into various control signals, and these control signals are sent to the arithmetic unit 10 and various registers 11, 12 through the signal lines 43, 44, 45, and 46, 41.゜Internal memory 13,
The data is sent to the address register 14 and controlled according to the microinstruction. That is, the support program S contained in the control storage device 1 is stored in various registers 11.1.
2 is sent to the internal memory 13 via the pass line 10.11, the arithmetic unit 10, and the pass line 12. At this time, the address created by the microinstruction as the write address of the internal memory 13 is transferred from the register 2 to the internal memory via the signal line 42, path line 70, arithmetic unit 10, path line 12, and multiplexer 15. Address register 1 that specifies the address
Set to 4. Therefore, the internal memory 13 has a.

According to the address set in the address register 14, various registers 11. : The contents of 12 are written. When the execution of the support program S is completed, a support program execution completion signal is output from the gamer 9 to the lipo-1 processor 200 through the signal line 14. When the processor 200 receives this signal, it performs an operation to fetch data indicating the contents of the various registers 11 and 12 stored in the internal memory 13. For this purpose, the support processor 200 sets a data acquisition start address in the address register 14 via the signal line 62 and the multiplexer 15, and reads the contents of the various registers 11 and 12 from the address in the internal memory 13 specified by this address register 14. Read and import.

Next, when the above-mentioned import is completed and the microprogram in the control storage device 1 is to be executed again by the central processing unit 100 from the address where it was paused, the support processor 200 sends a signal via a control signal through the signal line 60. By setting the address (restart address of the microprogram) to which the address has been matched via the line 61, multiplexer 7, signal line 53, multiplexer 8, and signal line 54 to the microprogram sequencer 3, the support program described above can be executed. Execution of the microprogram by the central processing unit 100 is resumed in the same manner as at the start address.

According to this embodiment, when the central processing unit 100 temporarily suspends the execution of the microb 0 gram that is currently being executed, the support program S saves the contents of various registers 11 and 12 in the internal memory 13 and stores them in the main memory. No access is made to the equipment, and the microprogram sequence is
By adopting a configuration that does not use any memory stack mechanism, etc., the central processing unit 100 can restart the microprogram from the address where it stopped, without changing the state when the microprogram was stopped. Execution can be resumed. Also, if the address match is executed again (if the error occurs, you can set the address to stop the microprogram in the address match register 5 before setting the restart address in the microprogram sequencer 3. Furthermore, since addresses other than the address where the address match occurred can be freely set in the microprocessor sequencer 3 from the leave processor 200,
Execution of the microprogram can be resumed from any address, making software and hardware debugging much easier.

[Effects of the Invention] As described above, according to the register data saving method of the present invention, when the execution of a microprogram is temporarily stopped, the contents of various registers are saved in the internal memory by the support program, and the contents of various registers are saved at this time. By configuring the structure so that no access is made to the main memory, execution of the microprogram is temporarily interrupted, the contents of various registers are retrieved, and then execution of the microprogram is restarted from the point where it was interrupted. There are benefits to be gained.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram showing an embodiment of a computer controlled by a microprogram to which the register data storage method of the present invention is applied, and FIG. 2 shows a detailed example of the central processing unit shown in FIG. 1. FIG. 1... Control storage device 2... Register 3... Micro program sequencer 4... Control circuit 5... Address match register 6... Comparator 7.
8.15...Multiplexer 9...Decoder 10
...Arithmetic unit 11.12...Various registers 13.
・Internal memory 14 ・Address register 100・
... Central processing unit 200 ... Support processor agent Patent attorney Noriyuki Chika (1 person) Figure 1

Claims (1)

[Claims] A microprogram control computer that reads and executes a microprogram stored in a control storage device by a microphone 0 program sequencer includes an internal memory that saves the contents of various registers when the microprogram is stopped, and a microprogram stored in the control storage device. After setting the stop address of the microprogram using the support program, the contents of various registers are transferred to the internal memory when the microprogram stops, and the data once saved in this internal memory is loaded, and then the microprogram is re-executed. A support processor that stores the microprogram, an address match register that holds the stop address of the microprogram set by the support processor, and a microprogram read address output from the microprogram sequencer and the address held in the address match register are compared. and a circuit that allows a support processor to set a read address when reading the support program from the control storage device from the support processor. method.