JPH06348543A - Method for connection with input/output simulator - Google Patents

Abstract

PURPOSE:To virtually construct an input/output device in a target system and improve the processing speed by providing a connection program which analyzes interruptions and instruction words and receives and passes data in synchronism with operation to the address of the input/output device. CONSTITUTION:When a central processing unit 1 equipped with an interruption input terminal performs reading/writing operation to the address of the input/ output device set in an address specification register 2 while executing a target program 10 to be debugged, a comparator 3 generates an interruption request and the central arithmetic processor 1 interrupts the execution of the target program 10 and the processing is branched to the connection program 11. The final instruction of the interruption request is analyzed and when the connection program 11 is a write instruction, the value of the operand corresponding to the value of an address latch register 4 is passed to the input/output simulator 31. When the connection program is a read instruction, on the other hand, the value from the input/output simulator 4 is substituted in the corresponding destination operand after the value of the source operand is passed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for connecting a debug device to an input / output simulator, and more particularly to connecting to an input / output simulator in a debug device for a device having a built-in computer system and whose operation is regulated by program instructions. Regarding the method.

[0002]

2. Description of the Related Art In recent years, not only word processors and personal computers but also air conditioners, television receivers, etc., which have a computer and a built-in program have been widely used. By the way, in these devices, program verification (d
ebug) must be performed. By the way, the conventional debug system is roughly divided into two methods. The first method is a target system that is a device that contains a program, and an emulator (ICE, in-circuit emulator) that is a device that connects the target system to a microcomputer.
tor) is connected to a microcomputer, and hardware resources of the target system are used except for the program execution unit, and therefore debugging can be performed in an environment substantially equal to real time. The second method uses a software simulator and does not use the target system hardware at all, but uses a system virtually built on a computer, and therefore does not wait for the completion of the target system. Debugging is possible.

[0003]

However, in the above debug system, each of the methods has the following problems. In the first ICE method, debugging cannot be performed unless the target system is equipped with all input / output devices.

In the second software simulator method, the instruction word is read from the memory, the instruction is determined from the read bit pattern, and C is determined based on the determination result.
The execution processing speed is IC because it is necessary to realize the procedure of changing the contents of the internal register and memory in the PU by a program.
It is extremely slow compared to the method by E, and is therefore inefficient for interactive debugging. Further, it takes a great deal of effort to virtually realize all the input / output devices to be provided in the target system by software.

In view of the above problems, the present invention virtually constructs an input / output device that is not provided on a computer, and at the same time, improves the execution processing speed by connecting the input / output simulator of a debug system. The purpose is to provide.

[0006]

In order to achieve the above object, in the invention of claim 1, an input / output simulator, a central processing unit having an interrupt input terminal, and an address assigned to the input / output device are provided. A specified address register, a comparator that compares the value of the address register and the value of the address bus and inputs the judgment output signal of the result to the interrupt input terminal, and the address output of the address bus in synchronization with the judgment output signal of the comparator. An input / output simulator using a debug device composed of a main storage device in which a connection program between an address latch register for capturing a value and an input / output simulator executed by an interrupt request from an interrupt input terminal is arranged. In the connection method with the CPU, the central processing unit is not A step of causing the comparator to issue an interrupt request to the central processing unit when a read / write operation is performed with respect to the address set in the address designation register; The step of branching to
The step of analyzing and determining whether the last instruction at which the connection program has caused an interrupt request is a write or read; and the address latch register if the connection program is also a write operation instruction in response to the determination step. Value and the value of the corresponding source operand are passed to the I / O simulator, while if it is a read operation instruction, the value of the address latch register is also passed to the I / O simulator, and then the corresponding destination operand is sent from the I / O simulator. A method of connecting to an input / output simulator is characterized in that it comprises a step of substituting a value and a step of the central processing unit subsequently executing the target program interrupted by an interrupt.

According to another aspect of the present invention, an input / output simulator, a central processing unit having an interrupt input terminal, an input / output covered memory arranged at an address assigned to the input / output device, and an input / output device are assigned. Address register that specifies the specified address, the value of the address register and the value of the address bus are compared, and the result is judged.The comparator that inputs the output signal to the interrupt input terminal of the central processing unit, and the judgment of the comparator A debug device including an address latch register that captures an address bus value in synchronization with an output signal, and a main memory device in which a target program and a connection program with an input / output simulator that is executed by an interrupt request from an interrupt input terminal are arranged. In the method for connecting to an input / output simulator using When the device performs a read / write operation to the address set in the address designation register during execution of the target program, the comparator generates an interrupt request to the central processing unit, and the interrupt request by the step causes the comparator to generate the interrupt request. A central processing unit branches to the connection program, a step of determining whether the last instruction where the connection program caused an interrupt request is a write or a read, and the determination step, and similarly the connection program If it is a write operation command, the value of the input / output covered memory indicated by the value of the address latch register is delivered to the input / output simulator and a data transmission request is issued, while if it is a read operation command, the address latch register Input / output simulator Substituting a value from the input / output simulator into the input / output covering memory indicated by the value of the address latch register after the delivery, and interrupting the program counter of the target program interrupted by the central processing unit by the interrupt. Connecting the input / output simulator with the step of re-executing the target program from the address of the last instruction that caused the request, and then continuing execution of the target program interrupted by the interrupt. I am trying.

In the third aspect of the invention, the step of determining the read / write operation of the last instruction that caused the interrupt request by the connection program is performed by analyzing the last instruction word that caused the interrupt request. According to a second aspect of the present invention, there is provided a method for connecting to an input / output simulator. According to a fourth aspect of the present invention, a read / write latch register is provided for capturing the value of the read / write identification signal in synchronization with the judgment output of the comparator, and the last instruction that caused the interrupt request by the connection program. 3. The method for connecting to an input / output simulator according to claim 2, wherein the read / write operation determination step is performed based on the value of the read / write latch register.

According to another aspect of the present invention, an input / output simulator, a central processing unit having an interrupt input terminal, an input / output covered memory arranged at an address assigned to the input / output device, and an input / output device are assigned. The address register that specifies the specified address, the value of the address register and the value of the address bus are compared, and the resulting judgment output signal is synchronized with the comparator connected to the interrupt input terminal and the judgment output signal of the comparator. Using a debug device consisting of an address latch register that captures the value of the address bus and a connection program between the target program and the input / output simulator that is executed by an interrupt request from the interrupt input terminal In the connection method with the input / output simulator, the central processing unit is a target. When a read / write operation is performed with respect to the address set in the address designation register during execution of the program, the comparator issues an interrupt request to the central processing unit, and the central operation is performed by the interrupt request by the step. The processing device branches to the connection program, determines whether the last instruction at which the connection program caused an interrupt request is a write or read, and if the connection program is a write operation instruction, the address The value of the input / output covered memory indicated by the value of the latch register is passed to the input / output simulator, and if it is a read operation instruction, the value of the address latch register is also passed to the input / output simulator and a data transmission request is issued, and then the address is sent. Shown in the latch register value A step of substituting a value from the input / output simulator for the input / output covered memory to prepare for the next access; and a step of the central processing unit subsequently executing the target program interrupted by an interrupt. The connection method with the input / output simulator is characterized by the following.

In the sixth aspect of the invention, the step of determining the read / write operation of the last instruction that caused the interrupt request by the connection program is performed by analyzing the last instruction word that caused the interrupt request. According to a fifth aspect of the present invention, there is provided a method for connecting to an input / output simulator. According to a seventh aspect of the present invention, a read / write latch register that captures the values of the read and write identification signals in synchronization with the determination output signal of the comparator is provided, and the last one that caused an interrupt request by the connection program. 6. The step of determining the read / write operation of the instruction is performed by the value of the read / write latch register.
The connection method with the described input / output simulator is used.

According to an eighth aspect of the present invention, an input / output simulator, a central processing unit having an interrupt input terminal, an input / output covered memory arranged at an address assigned to the input / output device, and an input / output device are assigned. Address register that specifies the specified address, the value of the address register and the value of the address bus are compared, and the result is judged.The comparator that inputs the output signal to the interrupt input terminal of the central processing unit, and the judgment of the comparator A debug device including a main memory device in which an address latch register that captures the value of the address bus in synchronization with an output signal and a connection program for a target program and an input / output simulator that is executed by an interrupt request from an interrupt input terminal are arranged. In the method of connecting to the input / output simulator using When the processor performs a read / write operation to the address set in the address specification register during execution of the target program, the comparator generates an interrupt request to the central processing unit, and the interrupt request by the step The central processing unit branches to the connection program; a step of determining whether the last instruction at which the connection program caused an interrupt request is a write or a read;
If the connection program also receives the determination step and is a write operation command, the value of the input / output covered memory indicated by the value of the address latch register is passed to the input / output simulator to transfer the input data from the input / output simulator. A value and an address value of the input / output covered memory are received, and the value of the input data is substituted into the input / output covered memory for read operation, and then the target program interrupted by the interrupt is continuously executed, In the case of a read operation instruction, the step of continuously executing the target program that has been interrupted immediately by an interrupt is also adopted, and the connection method with the input / output simulator is provided.

In the ninth aspect of the invention, the step of determining the read / write operation of the last instruction that caused the interrupt request by the connection program is performed by analyzing the last instruction word that caused the interrupt request. The connection method with the input / output simulator according to claim 8 is characterized in that According to a tenth aspect of the present invention, a read / write latch register for capturing the value of the read / write identification signal in synchronization with the judgment output signal of the comparator is provided, and the last interrupt request by the connection program is generated. 9. The instruction read / write operation determination step is performed based on the value of the read / write latch register.
The connection method with the described input / output simulator is used.

[0013]

With the above construction, in the invention of claim 1, the input / output simulator, the central processing unit having the interrupt input terminal, the addressing register for designating the address assigned to the input / output device, and the addressing register are provided. A comparator that compares the value with the value on the address bus and inputs the resulting judgment output signal to the interrupt input terminal, an address latch register that captures the value on the address bus in synchronization with the judgment output signal from the comparator, and the target program Also, in the debug device including the main storage device in which the connection program with the input / output simulator executed by the interrupt request from the interrupt input terminal is arranged, the connection with the input / output simulator is made by the following steps. As a first step, when the central processing unit performs a read / write operation on an address set in the address register during execution of a target program, the comparator issues an interrupt request to the central processing unit. . As a second step, the central processing unit branches to the connection program in response to the interrupt request from the step. As a third step, the connection program analyzes and determines whether the last instruction that caused the interrupt request is a write or a read. As a fourth step, if the connection program also receives the write operation instruction in response to the determination step, the value of the address latch register and the value of the corresponding source operand are passed to the input / output simulator, while the read operation instruction is issued. For example, similarly, after passing the value of the address latch register to the input / output simulator, the value from the input / output simulator is assigned to the corresponding destination operand. As a fifth step, the central processing unit thereafter continues to execute the target program interrupted by the interrupt.

According to a second aspect of the present invention, an input / output simulator, a central processing unit having an interrupt input terminal, an input / output covering memory arranged at an address assigned to the input / output device, and an input / output device are assigned. Address register that specifies the specified address, the value of the address register and the value of the address bus are compared, and the result is judged.The comparator that inputs the output signal to the interrupt input terminal of the central processing unit, and the judgment of the comparator A debug device including an address latch register that captures an address bus value in synchronization with an output signal, and a main memory device in which a target program and a connection program with an input / output simulator that is executed by an interrupt request from an interrupt input terminal are arranged. In, the connection with the input / output simulator is made by the following steps. As a first step, when the central processing unit performs a read / write operation on an address set in the address register during execution of a target program, the comparator issues an interrupt request to the central processing unit. . As a second step, the central processing unit branches to the connection program in response to the interrupt request from the step. As a third step, it is determined whether the last instruction where the connection program caused an interrupt request is a write or a read. As a fourth step, in response to the determination step, if the connection program is also a write operation command, the value of the input / output covered memory indicated by the value of the address latch register is passed to the input / output simulator and data is transmitted. On the other hand, if it is a read operation instruction, the value of the address latch register is also passed to the input / output simulator, and then the value from the input / output simulator is assigned to the input / output covered memory indicated by the value of the address latch register. To do. As a fifth step, the central processing unit re-executes the target program from the address of the last instruction that caused the interrupt request to the program counter of the target program which was interrupted by the interrupt, and then interrupted by the interrupt. Continue executing the target program.

According to the third aspect of the invention, the step of determining the read / write operation of the last instruction that caused the interrupt request by the connection program is performed by analyzing the last instruction word that caused the interrupt request. Be seen. According to a fourth aspect of the present invention, there is provided a read / write latch register that captures the value of the read / write identification signal in synchronization with the determination output of the comparator. Thus, the step of determining the read / write operation of the last instruction that has caused the interrupt request by the connection program is performed by the value of the read / write latch register.

According to the invention of claim 5, an input / output simulator, a central processing unit having an interrupt input terminal, an input / output covering memory arranged at an address assigned to the input / output simulator, and an input / output simulator are assigned. The address register that specifies the specified address, the value of the address register and the value of the address bus are compared, and the resulting judgment output signal is synchronized with the comparator connected to the interrupt input terminal and the judgment output signal of the comparator. In an input / output simulator device having a main memory device in which a connection program between an address latch register that captures the value of the address bus and an input / output simulator that is executed by an interrupt request from an interrupt input terminal is arranged. , Follow the steps below to connect to the I / O simulator. It is. As a first step, when the central processing unit performs a read / write operation on an address set in the address register during execution of a target program, the comparator issues an interrupt request to the central processing unit. . As a second step, the central processing unit branches to the connection program in response to the interrupt request from the step. As a third step, it is determined whether the last instruction where the connection program caused an interrupt request is a write or a read. As a fourth step, if the connection program is a write operation instruction, the value of the input / output covered memory indicated by the value of the address latch register is passed to the input / output simulator, and if it is a read operation instruction, the address latch is also changed. After passing the register value to the input / output simulator and issuing a data transmission request, the value from the input / output simulator is assigned to the input / output covered memory indicated by the value of the address latch register to prepare for the next access. As a fifth step, the central processing unit thereafter continues to execute the target program interrupted by the interrupt.

In the sixth aspect of the invention, the step of determining the read / write operation of the last instruction that caused the interrupt request by the connection program is performed by analyzing the last instruction word that caused the interrupt request. Be seen. According to a seventh aspect of the present invention, there is provided a read / write latch register for capturing the value of the read / write identification signal in synchronization with the determination output signal of the comparator.
Thus, the step of determining the read / write operation of the last instruction that has caused the interrupt request by the connection program is performed by the value of the read / write latch register.

According to the present invention, an input / output simulator, a central processing unit having an interrupt input terminal, an input / output covered memory arranged at an address assigned to the input / output device, and an input / output device are assigned. Address register that specifies the specified address, the value of the address register and the value of the address bus are compared, and the result is judged.The comparator that inputs the output signal to the interrupt input terminal of the central processing unit, and the judgment of the comparator A debug device including a main memory device in which an address latch register that captures the value of the address bus in synchronization with an output signal and a connection program for a target program and an input / output simulator that is executed by an interrupt request from an interrupt input terminal are arranged. In, the connection with the input / output simulator is made by the following steps. As a first step, when the central processing unit performs a read / write operation on an address set in the address register during execution of a target program, the comparator issues an interrupt request to the central processing unit. . As a second step, the central processing unit branches to the connection program in response to the interrupt request from the step. As the third step,
The connection program determines whether the last instruction that caused an interrupt request is a write or a read. Fourth
When the connection program receives the determination step and the write operation instruction, the connection program transfers the value of the input / output covered memory indicated by the value of the address latch register to the input / output simulator. Receives the value of input data and the address value of the input / output cover memory from this and substitutes the value of the input data in the input / output cover memory to prepare for the read operation, and then continues the target program interrupted by the interrupt. On the other hand, if it is a read operation command, the target program that was interrupted immediately by the interrupt is continuously executed.

In the invention of claim 9, the step of determining the read / write operation of the last instruction that caused the interrupt request by the connection program is performed by analyzing the last instruction word that caused the interrupt request. Be seen. According to a tenth aspect of the present invention, there is provided a read / write latch register that captures the value of the read / write identification signal in synchronization with the determination output signal of the comparator.
Thus, the step of determining the read / write operation of the last instruction that has caused the interrupt request by the connection program is performed by the value of the read / write latch register.

[0020]

EXAMPLES The present invention will be described below based on examples. (First Embodiment) This embodiment relates to the invention of claim 1. FIG. 1 is a block diagram of a debug device adopting the method of connecting to the input / output simulator of this embodiment. In this figure, 1
Is a central processing unit having an interrupt input terminal (not shown), 2 is an address (address) designation register, 3 is a comparator, 4 is an address latch register, and 5 is a main memory. Reference numeral 10 is a device, 10 is a target program which is arranged in the main memory 5 and is to be debugged, 11 is also a connection program, and 20 is a judgment output signal line for outputting the comparison result of the comparator 3. , 21 is an address bus, 22 is a data bus, and 31 is an input / output simulator that is virtually configured on a CPU to simulate the operation of an input / output device that is supposed to be electrically connected. .

Assume that the address assigned to the input / output simulator 31 is 100. At this time, although not shown, the value "100" is set in the address designation register 2. Further, the comparator 3 compares the set value of the address designation register 2 with the value of the address bus 21, and outputs "1" if the two values match and outputs "0" if they do not match. Therefore, “0” is normally output to the determination output signal line 20. The central processing unit 1 branches (jumps) to the interrupt processing program when "1" is input to the interrupt input terminal from the determination output signal line 20, and the address latch register 4 also strobes this signal. It operates as a (strobe) signal, and when the value is "1", the latch (latch,
Hold) action. Here, the connection program 11 is registered as the interrupt processing program.

The central processing unit 1 has an address bus 2
1. The target program 10 stored in the main storage device 5 is read out via the data bus 22 and executed. When the central processing unit 1 accesses the address assigned to the input / output simulator 31 for performing the input / output operation, that is, the address 100, the comparator 3 outputs the set value in the address register 2 and the address bus 21. It is detected that the existing values match, and the determination output signal line 20
The value "1" representing the coincidence is output as the determination output signal.
Since the determination output signal line 20 is connected to the interrupt input terminal of the central processing unit 1 and the strobe terminal (not shown) in the address latch register 4, an interrupt request is issued to the central processing unit 1. Then, the value of the address bus 21 at that time, that is, “100” in this case is captured in the address latch register 4. Then, the central processing unit 1 suspends the execution of the target program after performing the necessary saving of the program counter in preparation for the return after the end of the instruction currently being executed, and then interrupts the connection program 11 which is an interrupt processing program. Branch to.

FIG. 2 is an operation flow chart of the connection program 11. The contents will be described below with reference to this figure. (Step 10) The interrupt request is accepted, and the connection program 11 starts execution. (Step 11) Subtract the address value by the word length of the read / write operation instruction to the input / output device from the value of the program counter (PC, program countr, indicating the address of the next instruction) at the time of interruption by the interrupt, and input. Find the storage address of the output operation instruction.

(Step 12) The instruction word is analyzed. (Step 13) It is determined whether the input / output operation instruction stored at the obtained address is a write operation instruction or a read operation instruction. Operation code (operation code)
In the case of an instruction word that cannot be determined only by itself (for example, when both reading and writing are performed by "MOV"), the destination operand (destination operand, target arithmetic part, written instruction) is the address latch register 4
Value of 100, that is, 100 address, is a write operation instruction, and if the source operand (original arithmetic part) is 100 address, a read operation instruction is determined.

(Step 14) If it is a write operation instruction, the value of the address latch register 4 and the content of the source operand are delivered to the input / output simulator 31.
For example, the instruction is now "MOV 100, R1" (100
If the content of R1 is 15, the value "100" of the address latch register 4 and the content of the source operand, that is, the content "15" of R1 are input / output. It will be handed over to the simulator 31.

(Step 15) If it is a read operation instruction, the value of the address latch register 4 is delivered to the input / output simulator 31. Now the command is "MOV R2
(R0) ”(store the value of the address indicated by the register R0 in the register R2). At this time, the content of R0 is 10
If it is 0, the value of the address latch register 4 is "1".
00 ”will be delivered to the input / output simulator 31.

(Step 16) Input / output simulator 31
When the input value is received from, the value is stored in the destination operand. For example, the input / output simulator 3
If the input value is 1 to "23" and the destination operand is R2, the value "23" is stored in the register R2. (Step 17) Since the connection work with the input / output simulator 31 is completed, the interrupt processing program, that is, the connection program 11 is returned to the target program 10.

As described above, according to this embodiment, the circuit is constructed so that the interrupt is generated in synchronization with the read / write operation to the address assigned to the input / output device, and then the interrupt processing program By connecting the input / output simulator, which is not connected to the target system by hardware, by software, by providing a connection program that analyzes the last executed instruction word that caused the interrupt request and transfers data It will be possible.
That is, the instruction word is decoded and executed by the CPU hardware without intervention of the simulator.

In this embodiment, the above (step 1
In the operation of 1), the word length of the read / write operation instruction to the input / output device is assumed to be known, but if it cannot be specified in advance, the target program while subtracting the address value from the value of the program counter when interrupted by an interrupt 10 may be disassembled, that is, returned to the assembler, and an instruction word in which the value of the disassembled source operand or destination operand is equal to the value of the address latch register 4 may be obtained. Further, as shown in FIG. 3, a register (LPC, Last Program Counter) for storing the address of an instruction word executed immediately before by hardware is provided, and this register (LPC) is also saved when an interrupt is accepted. The arithmetic processing unit may be designed and the value may be obtained from this LPC value.

(Second Embodiment) This embodiment relates to the inventions of claim 2, claim 3 and claim 4. FIG. 4 is a configuration diagram of a debug device adopting the method of connecting to the input / output simulator of this embodiment. In the figure, 1 is a central processing unit, 2 is an addressing register, 3 is a comparator, 4 is an address latch register, 5 is a main memory, 6 is an input / output covered memory. 10 is a target program arranged in the main memory 5, 12 is a connection program, 20 is a judgment output signal line for outputting the comparison result of the comparator 3, and 21 is an address bus. Yes, 22 is a data bus, and 31 is an input / output simulator.

It is to be noted that, in this figure, components having the same functions as those of the device shown in FIG. 1 are designated by the same reference numerals as those in FIG. And this is the same in the later embodiments. Next, regarding the device unique to this embodiment, the input / output covered memory 6 is arranged so as to overlap the address assigned to the input / output simulator, and the central processing unit 1 sets the address set in the addressing register 2. It is designed to operate in preference to I / O devices when reading and writing. Therefore, the input / output simulator 3
Reading and writing to 1 is suppressed.

Assume that the address assigned to the input / output simulator 31 is 100. Further, it is assumed that the connection program 12 is registered as the interrupt processing program. The central processing unit 1 has an address bus 2
1. The target program 10 stored in the main storage device 5 is read and executed via the data bus 22.

When the central processing unit 1 accesses the address assigned to the input / output simulator 31 in order to access the input / output device, that is, the address 100, the comparator 3 causes the set value of the address designation register 2 and the address bus 21. It is detected that the values output to the output signal "1" match, and the value "1" representing the match between the two values is output to the determination output signal line 20.
Since the judgment output signal line 20 is connected to the interrupt input terminal of the central processing unit 1 and the strobe terminal of the address latch register 4, an interrupt request is made to the central processing unit 1 and the address latch register 4 In this case, the value of the address bus 21 at that time, that is, "100" in this case is captured. The above operation is the same as that of the first embodiment. Then, the central processing unit 1 suspends the execution of the target program 10 and branches to the connection program 12 which is an interrupt processing program. FIG. 5 is an operation flow chart of the connection program 12. Hereinafter, description will be given with reference to FIG. In the figure, steps having basically the same operations as those in the previous embodiment are designated by the same step numbers, and corresponding steps having different operations are changed by changing the number of the leading digit from 1 to 2. The digit number is combined with the second digit number of the corresponding step. The same applies to the subsequent embodiments.

(Step 10) Accept an interrupt request,
The execution of the connection program 12 is started. (Step 11) The address value is subtracted by the word length of the read / write operation instruction to the input / output device from the value of the program counter when interrupted by the interrupt to obtain the storage address of the input / output operation instruction.

(Step 12) The instruction word is analyzed. (Step 13) It is determined whether the input / output operation instruction stored at the obtained address is a write operation instruction or a read operation instruction. If the instruction word cannot be determined only by the operation code, it is determined that the destination operand is the write operation instruction if the value of the address latch register 4, that is, the address 100, and the read operation instruction if the source operand is the address 100.

(Step 24) If it is a write operation command, the value of the address latch register 4 and the contents of the input / output covering memory 6 assigned to the address indicated by the value of the address latch register 4 are input / output simulator. Three
Hand over to 1. For example, the command is now "MOV 100,
If R1 "(store the value of register R1 at address 100), the value of address latch register 4 is" 100 "and 1
The contents of the input / output covered memory 6 assigned to address 00 (here, the contents of R1 are stored) are delivered to the input / output simulator 31.

(Step 15) If it is a read operation instruction, the value of the address latch register 4 is delivered to the input / output simulator 31. For example, the command is now "MOV
If R2, (R0) "(store the value of the address indicated by the register R0 in the register R2), the value" 100 "of the address latch register 4 is delivered to the input / output simulator 31. (At this time, the content of R0 is (Step 261) When the input value is received from the input / output simulator 31, the value is stored in the input / output covering memory 6 assigned to the address indicated by the value of the address latch register 4. For example, "23". When receiving the value, the value "23" is stored in the address 100 indicated by the address latch register 4.

(Step 262) The program counter of the interrupted target program is returned to the address of the instruction that caused the interrupt, and the instruction is re-executed. As a result, a data read operation is performed. (Step 17) Since the connection work with the input / output simulator 31 is completed, the interrupt processing program, that is, the connection program 12 is returned to the target program 10.

As described above, according to this embodiment, by providing the input / output covering memory 6, the value of the source operand at the time of writing can be obtained from the input / output covering memory 6, and the destination at the time of reading. Data can be stored in the operand by re-executing the instruction after setting the contents of the input / output cover memory 6, and the work of transferring data between the target program and the input / output simulator can be greatly improved.

In the present embodiment, the above (step 1
In the operation of 1), it is assumed that the word length of the read / write operation instruction to the input / output simulator is known, but if it cannot be specified in advance, it can be specified by taking another method as in the first embodiment. It's ridiculous. Further, as shown in FIG. 6, a read / write (read write) for capturing the value of the read / write control signal line 23 of the central processing unit 1 in synchronization with the output signal of the comparator 3.
(e, read / write) By providing the latch register 7 and referring to this value, it is possible to determine the read / write operation without analyzing the instruction word in (step 12).

(Third Embodiment) This embodiment relates to the inventions of claims 5, 6 and 7. FIG. 7 is a configuration diagram of a debug device that employs the method of connecting to the input / output simulator according to the present embodiment. In the figure, 1 is a central processing unit having an interrupt input terminal (not shown), 2 is an addressing register, 3 is a comparator, 4 is an address latch register, and 5 is a main memory. 1 is a device, 6 is an input / output covered memory, 7 is a read / write latch register, 10 is a target program arranged in the main memory 5, 13 is a connection program, and 20 is a comparator 3. Is a determination output signal line for outputting the comparison result of, 21 is an address bus, 22 is a data bus, 23 is a read / write control signal line,
Reference numeral 31 is an input / output simulator.

Components having the same functions as those shown in FIGS. 1 and 4 are designated by the same reference numerals, and the description thereof will be omitted in principle. I / O simulator 31
Addresses assigned to addresses 100 (for output) and 1
Address 01 (for input) is assumed. At this time, the values "100" and "101" are set in the address designation register 2. At the address 101, an initial value "23" is preset in preparation for reading the first data. Similarly, the connection program 13 is registered in advance as an interrupt processing program.

The central processing unit 1 has an address bus 2
1. The target program 10 stored in the main storage device 5 is read out via the data bus 22 and executed. The central processing unit 1 uses the address assigned to the simulator 31 for input / output operation, that is, 1
Access address 00 or address 101. As a result, the comparator 3 detects that the set value of the address designation register 2 and the value output to the address bus 21 match, and the judgment output signal line 20 shows a value “1” indicating the match of both values.
Is output. The judgment output signal line 20 is connected to the interrupt input terminal of the central processing unit 1, the strobe terminal of the address latch register 4, and the strobe terminal of the read / write latch register 7. At this time, an interrupt request is issued to the central processing unit 1, the value of the address bus 21 at that time is captured in the address latch register 4, and the value of the read / write control signal line 23 is stored in the read / write latch register 7. To be captured. Then, the central processing unit 1 suspends the execution of the target program 10 and branches to the connection program 13 which is an interrupt processing program.

FIG. 8 is an operation flow chart of the connection program 13. The contents will be described below with reference to this figure. In the figure, the steps having basically the same operations as those in the second embodiment are given the same step numbers, and the steps having different operations are provided with the first digit number from 1 or 2 to 3.
And change the second digit to the corresponding step number 2
It is also combined with the digit number.

(Step 10) Accept an interrupt request,
The execution of the connection program 13 is started. (Step 31) The value of the read / write latch register 7 is read. (Step 33) It is determined whether the read / write operation command to the input / output device when the interrupt is generated is the write operation command or the read operation command.

(Step 24) If the value of the read / write latch register 7 indicates a write operation, it is assigned to the value of the address latch register 4 (“100” in this example) and its address (100 address in this example). The contents of the input / output covered memory 6 that have been stored are delivered to the input / output simulator 31. (Step 15) If the value of the read / write latch register 7 indicates a read operation, the value of the address latch register 4 (“101” in this example) is delivered to the input / output simulator 31. At this time, the target program is
The value "23" is read from address 101.

(Step 36) Input / output simulator 31
When an input value, for example "45", is received from the address latch register 4, the value "45" is read out to the address 101 (where the input / output covered memory 6 is arranged). Store for operation. (Step 17) Since the connection work with the input / output simulator 31 has been completed, interrupt processing, that is, the connection program 13
Then, the program returns to the target program 10.

As described above, according to the present embodiment, it is not necessary to analyze what the last executed instruction word is and to determine the word length, and further, as explained below, resources at the time of reading. There is no destruction of (resource). Although it is the destruction of resources, for example, AND R3,
The instruction 101 (take the logical product of the contents of R3 and the contents of address 101 and store the result in R3) was issued.
If the correct value is not entered in the address 101, the execution of this instruction will destroy R3. Therefore, even if the correct value is entered in the address 101 after this, and the instruction is re-executed, the correct result cannot be obtained because R3 has already been destroyed. However, in this example,
Since a correct value has been prepared at the 101st postponement, such destruction of Lithos does not occur.

(Fourth Embodiment) This embodiment relates to the inventions of claim 8, claim 9 and claim 10. FIG. 9 is a configuration diagram of a debug device that employs the method of connecting to the input / output simulator according to the present embodiment. In the figure, 1 is a central processing unit having an interrupt input terminal (not shown), 2 is an addressing register, 3 is a comparator, 4 is an address latch register, and 5 is a main memory. Reference numeral 6 is a device, 6 is an input / output covered memory, 7 is a read / write latch register, 10 is a target program arranged in the main memory 5, 12 is a connection program, and 20 is a comparator. 3 is a determination output signal line for outputting the comparison result, 3 is an address bus, 22 is a data bus, and 32 is an input / output simulator.

Components having the same functions as those shown in FIGS. 1, 4 and 7 are designated by the same reference numerals and the description thereof will be omitted in principle. Now, it is assumed that the addresses assigned to the simulator 32 are address 100 (for output) and address 101 (for input). A connection program 14 is registered as an interrupt processing program.

The central processing unit 1 has an address bus 2
1. The target program 10 stored in the main storage device 5 is read out via the data bus 22 and executed. The central processing unit 1 uses the address assigned to the simulator 32 for input / output operation, that is, 1
Access address 00 or address 101. As a result, the comparator 3 detects that the set value of the address designation register 2 and the value output to the address bus 21 match, and the judgment output signal line 20 shows a value “1” indicating the match of both values.
Is output. The judgment output signal line 20 is connected to the interrupt input terminal of the central processing unit 1, the strobe terminal of the address latch register 4, and the strobe terminal of the read / write latch register 7. At this time, an interrupt request is issued to the central processing unit 1, the value of the address bus 21 at that time is captured in the address latch register 4, and the value of the read / write control signal line 23 is stored in the read / write latch register 7. To be captured.

The operation up to this point is the same as in the third embodiment. Then, the central processing unit 1 interrupts the execution of the target program 10 and branches to the connection program 14 which is an interrupt processing program, but this content is different.
FIG. 10 is an operation flow chart of the connection program 14. The contents will be described below with reference to this figure. Also in this figure, the same step number is basically attached to the step of the same operation as the previous embodiment, and the number of the leading digit is changed from 1 or 2 or 3 to 4 for the step of different operation, The second digit is matched to the second digit of the corresponding step.

(Step 41) Accept an interrupt request,
The execution of the connection program 14 is started. (Step 31) The value of the read / write latch register 7 is read. (Step 33) It is determined whether the read / write operation command to the input / output device when the interrupt is generated is the write operation command or the read operation command.

(Step 24) If the value of the read / write latch register 7 indicates the write operation, the value of the address latch register 4 ("100" in this example) and its address (100 in this example) are assigned. The contents of the input / output covered memory 6 and the input / output covered memory 6 are transferred to the input / output simulator 32. (Step 441) When the address value “101” and the input value, for example, “45” are received from the input / output simulator 32, the value “45” is set to the address 101 (where the input / output covered memory 6 is arranged). Store and prepare for read operation.

(Step 17) Input / output simulator 32
Since the connection work with is completed, the interrupt process, that is, the connection program 13 is returned to the target program 10. As described above, according to this embodiment, the next input value can be changed according to the output value, and the overhead required for connecting the target program and the input / output simulator can be significantly improved.

[0056]

As described above, according to the present invention,
It is possible to substitute an input / output device, which is not provided in the target system but is necessary for debugging, by an input / output simulator virtually built on the computer. Therefore, it is possible to construct a debug system capable of program debugging even if the target system does not have all input / output devices. In addition, since the simulator is not involved in interpreting and executing the instruction word and the instruction is executed by the CPU hardware, the execution speed can be suppressed only to the slowness of the input / output simulator when compared with the pure software simulator method. Therefore, its practical effect is great.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of a debug device adopting a method of connecting to an input / output simulator according to the invention of claim 1. (First embodiment)

FIG. 2 is an operation flow chart of a connection program in the above embodiment.

FIG. 3 is a configuration diagram of a small change unit in the above embodiment.

FIG. 4 is a configuration diagram of an embodiment of a debug device adopting the connection method with the input / output simulator according to the inventions of claim 2, claim 3 and claim 4; (Second embodiment)

FIG. 5 is an operation flowchart of a connection program in the above embodiment.

FIG. 6 is a configuration diagram of a small change unit in the above embodiment.

FIG. 7 is a configuration diagram of an embodiment of a debug device adopting the connection method with the input / output simulator according to the inventions of claim 5, claim 6 and claim 7. (Third embodiment)

FIG. 8 is an operation flowchart of a connection program in the above embodiment.

FIG. 9 is a configuration diagram of an embodiment of a debug device adopting the connection method with the input / output simulator according to the inventions of claim 8, claim 9 and claim 10. (Fourth embodiment)

FIG. 10 is an operation flowchart of the connection program in the above embodiment.

[Explanation of symbols]

 1 central processing unit 2 address designation register 3 comparator 4 address latch register 5 main memory 6 input / output covered memory 7 read / write latch register 10 target program 11 connection program (first embodiment) 12 connection program (second embodiment) ) 13 connection program (third embodiment) 14 connection program (fourth embodiment) 20 determination output signal line 21 address bus 22 data bus 23 read / write control signal line 31 input / output simulator (first, second and third embodiments) ) 32 input / output simulator (fourth embodiment)

Claims (10)

[Claims] 1. An input / output simulator, a central processing unit having an interrupt input terminal, an addressing register for specifying an address assigned to the input / output device, and a value of the addressing register and a value of an address bus are compared. By the comparator that inputs the resulting judgment output signal to the interrupt input terminal, the address latch register that captures the value of the address bus in synchronization with the judgment output signal of the comparator, and the interrupt request from the target program and the interrupt input terminal. In a method of connecting to an input / output simulator, which is made by using a debug device composed of a main memory device in which a program to be connected to an input / output simulator to be executed is arranged, the address designation is performed while the central processing unit is executing a target program. When you read or write to the address set in the register The comparator generates an interrupt request to the central processing unit, the central processing unit branches to the connection program due to the interrupt request by the step, and the connection program causes the interrupt request. After the step of analyzing whether the last instruction is write or read, and in response to the step of determining, the connection program also determines the value of the address latch register and the value of the corresponding source operand if it is a write operation instruction. If it is a read operation instruction, the value of the address latch register is also passed to the input / output simulator, and then the value from the input / output simulator is assigned to the corresponding destination operand; The device is later Method of connecting the input and output simulator, characterized in that comprising the step of performing continuously a target program that was interrupted by only. 2. An input / output simulator, a central processing unit having an interrupt input terminal, an input / output covered memory arranged at an address assigned to the input / output device, and an address assigned to the input / output device are specified. Synchronize with the addressing register, the comparator that compares the value of the addressing register and the value of the address bus and inputs the resulting judgment output signal to the interrupt input terminal of the central processing unit, and the judgment output signal of the comparator. This is done using a debug device consisting of an address latch register that captures the value of the address bus, and a main memory device in which a connection program with a target program and an input / output simulator that is executed by an interrupt request from an interrupt input terminal is arranged. In the connection method with an input / output simulator, the central processing unit is a target program. The step of causing the comparator to issue an interrupt request to the central processing unit when a read / write operation is performed on the address set in the address designation register during execution; and the central processing unit according to the interrupt request by the step. Branch to the connection program, a step of determining whether the last instruction at which the connection program caused an interrupt request is a write or a read, and the connection program also receives a write operation in response to the determination step. If it is an instruction, the value of the input / output covered memory indicated by the value of the address latch register is passed to the input / output simulator and a data transmission request is issued, while if it is a read operation instruction, the value of the address latch register is also input / output. After handing over to the simulator, Substituting a value from the input / output simulator into the input / output covered memory indicated by the value of the latch register, and causing the central processing unit to cause an interrupt request to the program counter of the target program that was interrupted by the interrupt. And re-execution of the target program from the address of the last instruction, and continuing execution of the target program interrupted by an interrupt. 3. The determination step of the read / write operation of the last instruction that caused the interrupt request by the connection program is performed by analyzing the last instruction word that caused the interrupt request. The method for connecting to the input / output simulator according to claim 2. 4. A read / write operation of the last instruction that causes an interrupt request by the connection program, comprising a read / write latch register that captures the value of a read / write identification signal in synchronization with the judgment output of the comparator. 3. The method for connecting to an input / output simulator according to claim 2, wherein the determining step is performed based on the value of the read / write latch register. 5. An input / output simulator, a central processing unit having an interrupt input terminal, an input / output covered memory arranged at an address assigned to the input / output device, and an address assigned to the input / output device are designated. The value of the address bus is compared with the value of the address register and the value of the address bus, and the judgment output signal of the result is connected to the interrupt input terminal, and the value of the address bus is synchronized with the judgment output signal of the comparator. And an input / output simulator using a debug device consisting of a main memory in which an address latch register that captures the target program and a connection program with the target program and an input / output simulator that is executed by an interrupt request from an interrupt input terminal are arranged. In the connection method of, the central processing unit is The step of causing the comparator to generate an interrupt request to the central processing unit when a read / write operation is performed with respect to the address set in the address designation register; and the central processing unit having the connection program in response to the interrupt request in the step. And a step of determining whether the last instruction where the connection program caused an interrupt request is a write operation or a read operation, and if the connection program is a write operation instruction, it is indicated in the value of the address latch register. The value of the input / output covered memory is transferred to the input / output simulator, and if it is a read operation command, the value of the address latch register is also transferred to the input / output simulator and a data transmission request is issued, and then the value is displayed in the value of the address latch register. Input / output covered memory And a step of substituting a value from the input / output simulator for the next access, and a step of subsequently executing the target program interrupted by the central processing unit by an interrupt. How to connect to the input / output simulator. 6. The step of determining the read / write operation of the last instruction that caused the interrupt request by the connection program is performed by analyzing the last instruction word that caused the interrupt request. The method for connecting to the input / output simulator according to claim 5. 7. A read / write latch register for capturing the value of a read / write identification signal in synchronization with a judgment output signal of the comparator, and a read / write latch register for the last instruction that caused an interrupt request by the connection program. 6. The method of connecting to an input / output simulator according to claim 5, wherein the read / write operation determination step is performed based on the value of the read / write latch register. 8. An input / output simulator, a central processing unit having an interrupt input terminal, an input / output covered memory arranged at an address assigned to the input / output device, and an address assigned to the input / output device are designated. Synchronize with the addressing register, the comparator that compares the value of the addressing register and the value of the address bus and inputs the resulting judgment output signal to the interrupt input terminal of the central processing unit, and the judgment output signal of the comparator. This is done using a debug device consisting of an address latch register that captures the value of the address bus, and a main memory that has a connection program with the target program and an input / output simulator that is executed by an interrupt request from an interrupt input terminal. In the connection method with the input / output simulator, the central processing unit is the target program. The step of causing the comparator to generate an interrupt request to the central processing unit when a read / write operation is performed on the address set in the address designation register during execution of the RAM, and the central processing by the interrupt request by the step. The device branches to the connection program, determines whether the last instruction where the connection program caused an interrupt request is write or read, and the connection program also receives the write operation in response to the determination step. If it is an instruction, the value of the input / output covered memory indicated by the value of the address latch register is passed to the input / output simulator to receive the value of the input data and the address value of the input / output covered memory from the input / output simulator. And the value of the input data in the input / output cover memory Substituting for the read operation by substituting, and then continuously executing the target program interrupted by the interrupt, and if it is a read operation instruction, the target program interrupted immediately by the interrupt is continuously executed. How to connect to the input / output simulator. 9. The step of determining the read / write operation of the last instruction that caused the interrupt request by the connection program is performed by analyzing the last instruction word that caused the interrupt request. The method for connecting to the input / output simulator according to claim 8. 10. A read / write latch register for capturing the value of a read / write identification signal in synchronism with the judgment output signal of the comparator, and reading / writing the last instruction that caused an interrupt request by the connection program. 9. The method of connecting with an input / output simulator according to claim 8, wherein the operation determining step is performed by the value of the read / write latch register.