JPS58106642A - Parallel operating device - Google Patents

Abstract

PURPOSE:To execute the processing of each operating section in parallel and to attain a high operating speed, by providing plural operation elements in common use for each operating section and an instruction register entried with an instruction, to plural operation sections performing specific operation processing. CONSTITUTION:An instruction read out from a main storage device 11 is entried to an instruction register 13, and an instruction from the register 13 is operated at operation sections 201-20m having a specific operation processing function. Operating elements 16116n of common use are connected to the operating sections 201-20m and the operation sections 201-20m monitor the state of the register 13. The operation sections 201-20m discriminate whether or not the instruction of the register 13 is processed at the corresponding operation section, and the instruction entried to the register 13 is fetched in response to the state of an information 22 and the usage of the element and the operation is done by using the corresponding elements 161-16n. It is outputted to the line 22 that the elements 161-16n are in use and the instruction to be executed from an instruction buffer 12 is entried to the register 13.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a parallel computing device using an ideal line control method.

TECHNICAL BACKGROUND OF THE INVENTION In general, a computing device using the Neudelein control system is structured as shown in FIG. In the figure, the 11-digit main memory (
-MEM), 12fd MEM (hereinafter referred to as -MEM), 7a (hereinafter referred to as IB) in which instructions read ahead from the 12fd MEM 11 are sequentially stored. By pre-reading instructions from MEM JJ by an instruction pre-reading mechanism (not shown) in the IB 12, it becomes possible to carry out so-called parallel e-line control in which instructions are processed continuously. In addition, this
Naka Eveline'I! Since the II system is not directly related to the gist of the present invention, its explanation will be omitted. The instruction prefetched into the IB 12 is placed in an instruction register (hereinafter referred to as IR) 13 after its type and the like are decoded. At this time, if the instruction is of the RX type, the operand is read from the MEM Z 7, and the operand is stored in the non-illustrated Navelland L nonostar.

The instruction placed in IRJJ is taken into the arithmetic unit 14, and the instruction is executed by the arithmetic unit 14. Arithmetic unit J
The 4Fi has a control storage section (not shown), which opens the microinstruction Kjl for instructions taken in from IRJJ and performs the corresponding processing. That is, the microinstruction taken out from the arithmetic unit 14 is sent to the microinstruction path 15. As a result, various calculation elements 16. Some of the ~16A are activated and processing based on microinstructions is performed. Arithmetic elements 161-16. Each Fi has a unique function, for example, the calculation elements 161, 16, . are an adder and a drop calculator, respectively. These calculation elements 16
Data is exchanged between 1 and 16n via a data bus 17.

Problems with the Background Art In an arithmetic unit using the Eveline control method as shown in FIG.
Processing is performed in the order of the instruction read stage IF for reading instructions from 1, the operand door P address @)H stage F-NOA1O (land read stage)<, and the execution stage E. And each command is...
The instruction read stage is processed backward by one cycle (1 machine cycle) by the mother line control. If a command is issued and MEM is executed at different timings,
l I K reading, MEM 11
Processing can be performed within the same cycle using known techniques, such as using a storage memory (not shown) installed in the preceding stage as a memory for storing instructions and a memory for storing operands. It is possible. However, execution stage E is 1
In the case of an instruction that does not complete within a cycle (1 machine cycle), it is impossible to perform processing at an execution stage that overlaps with the execution stage of a subsequent instruction. Therefore, the subsequent instruction tD
Execution <Teso E was forced to wait until the execution stage E of the preceding instruction was completed. Therefore, as shown in FIG. 2, if the execution stage E of the preceding instruction 1° is an instruction that requires an execution time of N cycles, for example, 4 cycles (N=4), the following instructions 11+11+11... and -N-1 periods, or 38 expected.

In this way, in the conventional arithmetic unit using the motherboard control method, if the execution stage E of the preceding instruction does not complete in one cycle, the execution stage E of the subsequent instruction is forced to wait, and the flow of the execution line is interrupted. Therefore, there was a drawback that it became a major obstacle in speeding up calculations.

Purpose of the Invention The present invention has been made in view of the above circumstances, and its purpose is to:
Parallel processing of the execution stage can be performed efficiently, which is the fourth advantage.
The turbulence of the eveline flow can be significantly reduced,
An object of the present invention is to provide a parallel arithmetic device capable of increasing the arithmetic speed.

Summary of the Invention: An instruction register in which prefetched instructions are stored in an instruction register, a plurality of arithmetic units having unique arithmetic processing functions,
A plurality of arithmetic elements shared by these arithmetic units are provided, each of the arithmetic units monitors the instruction register, and determines whether the instruction placed in the instruction register is an instruction to be processed by the own performance wing, and If it is determined that the arithmetic element used to execute the instruction is not in use, it fetches the instruction placed in the instruction register above and starts executing the instruction, and also sends the instruction to other arithmetic units. By outputting a signal indicating that the arithmetic element to be used is in use and storing the next instruction to be executed in the instruction register, processing operations of the arithmetic unit while instructions are being executed can be controlled. In parallel, other arithmetic units take in and execute subsequent instructions newly placed in the instruction register.

Furthermore, the present invention provides a comparison circuit that compares the information of the register specification part included in the instruction currently being executed and the instruction to be executed next, and uses the comparison output of this comparison circuit as the instruction to be executed next. By incorporating this as a condition for starting instruction execution, a plurality of arithmetic units can multiplex the general-purpose registers at the register level depending on the usage status of the general-purpose registers.

Embodiment 11 of the Invention Figure 3 is a diagram showing an embodiment of the invention. Components that are the same as those in FIG. 1 are given the same reference numerals and detailed explanations will be omitted. In the figure, 201 to 2ρ1 are specific arithmetic processing functions (for example, fixed-point arithmetic functions, floating-point arithmetic functions,
or function calculation function). The arithmetic units 20˜j O, are basically functionally distributed versions of the arithmetic unit 14 in FIG. 1, and each has an independent control memory (not shown) and can operate in parallel with other arithmetic units. . 2 is an operation scene 19 for transferring the contents of IRJJ to the calculation units 201 to zO□, 22 is a signal line OPF,
This is an element-in-use information line consisting of I to OPE n. Signal lines OPP: J to OPE n are used to indicate whether or not the calculation elements 16, to 16n are in use, and are all commonly connected to each calculation unit zo1 to 20rn. In this embodiment, these signal lines OPE1-0Pli:n are at a high level ("H level") in the normal state, and when the corresponding calculation elements 161-16i are used, the calculation units 201-20
It is set to low level ('L' level) by one of the calculation units of m, and this state is maintained until the corresponding calculation element is released. PG is a road clock signal line.

The signal line PG is commonly connected to the road clock terminal of IRJJ and each of the calculation units 201 to 20rllll. In this embodiment, the signal line PG is in the normal state at the "H" level, and when any one of the computing units 201 to XO takes in an instruction held in IRJJK, the signal line PG is "゛This arithmetic unit is connected to the machine clock signal line PG after one cycle of CLK.
is set to return to @H” level.

Next, the operation of the configuration shown in FIG. 3 will be explained with reference to the timing chart shown in FIG. 4. Currently, IRJJ holds an instruction A that requires an execution stage of one machine cycle.
It is assumed that the signal line PC is at the "L" level. In addition, the calculation unit JO.

Assume that the instruction A held in the IR,13 is taken in and the arithmetic element 163 is used to execute arithmetic processing. At this time, the signal line OPE j is connected to the calculation unit 2.
0. This indicates that the arithmetic element 16° is in use. In this state, the arithmetic unit 201 returns the signal line PC to the "H" level one cycle after executing the instruction A (at the end of the first cycle in the timing chart of FIG. 4). In this example, one machine cycle after the execution of instruction A is also the end of the execution stage of instruction A, and the signal line OPE j is set to ``H'' level in the calculation unit 20, and the calculation element 16 is set to ``H'' level. to release. □ By the signal line PG reaching 1H" level, IB
The next instruction to be executed, such as instruction B, output from Jj is held in lR13. This command for company B, for example 4
It is assumed that the instruction requires the execution status of a machine cycle.

Each arithmetic unit 201 to 20rn receives and decodes the instruction (instruction B) held in the IRf 3 via the operating unit 4 bus 21, and executes this instruction (instruction B) in its own nose section. It is determined whether the command is appropriate or not. That is, the calculation unit 20. ~20 ITl is Operation 1 Pass 2
He constantly monitors the orders that appear on the screen. For example, if the calculation unit 201 executes the above instruction B, i! It shall be deemed that the At this time, the arithmetic unit 201 determines which arithmetic element is necessary to execute instruction B, and determines whether or not the arithmetic element is in use. if,
If it is in use, the execution of instruction B by the arithmetic unit 201 is put on hold. In this embodiment, it is assumed that the arithmetic element necessary to execute instruction B is the arithmetic element 16n (not limited to one arithmetic element). Operation W
2'01 indicates whether the arithmetic element 1'6n is in use or not by checking the state of the signal line OPEn (“H”t or “L”).
Leh! Judgment based on the rules. In this example, the signal line 0P
En is at the °H'' level, and the arithmetic unit 201 determines that the arithmetic element 16n is in the undesired i state.As a result, the arithmetic unit 201 transfers the instruction B held in the lR13 to the internal instruction renoster (Fig. (not shown) (it does not matter if arithmetic elements other than the arithmetic element 16tl are in use), at this time, the arithmetic unit 20 sets the signal line PG to the m L 11 level, and also sets the signal line OPE n to the same level. After that, the arithmetic section 20: uses the arithmetic unit 76F to
Execute.

Similarly to the execution of the instruction A described above, the arithmetic unit 20t outputs the signal line PG one machine cycle after executing the instruction B (at the end of the second period in the timing chart of FIG. 4).
Return to 1H# level. As a result, the next instruction to be executed output from IBJj, such as instruction C, is
3. This instruction C, for example, is an instruction that requires an execution stage of one machine cycle like instruction A,
Each calculation unit 201 to 20 via the fourth ray scene path 21
mK is transferred. Since the arithmetic unit 20 is continuing to execute instruction B, the arithmetic units 20! except for the arithmetic unit 20! ~20. is monitoring the command (command C) appearing on the oil transmission path 21. At this time, the arithmetic unit 203 determines that the instruction C should be executed, and the arithmetic element 16m necessary for executing the instruction C (signal line OPE
Based on the state #2), it is determined that the device is not in use. , whereby the calculation unit 20. takes the above instruction C into the internal instruction register, and connects the signal line PG to @
At the same time, the signal line OPE J also executes the instruction C by setting the signal line OPE J to "L#L# element 161.

On the other hand, the arithmetic unit 201 continues to execute instruction B using the arithmetic element 16n. That is, according to this embodiment, even if the preceding instruction B is an instruction that does not finish in one machine cycle, the next instruction C is executed in parallel without waiting for the execution stage of this instruction B to finish. Talk about what you can do. Hereinafter, regarding instructions 1 and E (both instructions requiring an execution stage of one machine cycle), the arithmetic unit 20 that executes these instructions is the arithmetic unit 20 that executes instruction B.
1 (in this example, each calculation unit 20..20
．． ], and if the arithmetic elements used to execute instruction B do not overlap (each arithmetic element 161+1'* in this example), then the instruction B is executed in parallel with the instruction B in the same way as the instruction C. Therefore, as shown in FIG. 5, even if the execution stage E of the preceding instruction B is an instruction requiring four cycles of execution time, the subsequent instruction C,
D, ni: only start execution with a delay of one cycle each. In the 9-line control system, in the normal state, subsequent instructions are processed one cycle after the preceding instruction, and according to this embodiment, the execution stage E of the preceding instruction is delayed by one cycle. Even in the case of instructions that do not end with , the flow of the pipeline is not interrupted. Therefore, it is important to increase the speed of calculations.

Next, the operation when parallel processing is not possible will be explained. It is now assumed that the arithmetic unit 202 is executing the arithmetic processing of the instruction F using the arithmetic element 16K as shown in FIG. It is assumed that this instruction F is an instruction requiring an execution stage of two machine cycles. In this case, as is clear, the signal line OPE1 becomes @L level due to the calculation unit 20. In this state, the calculation unit 20. signal line P after one machine cycle after executing instruction F (at the end of the 6th cycle in the timing chart of Fig. 4).
G to '''H#H# level.

When the signal line PG becomes "H level," the next instruction to be executed, such as instruction G, is held from lB12 to IRJJ.This instruction G is an instruction executed by the arithmetic unit 201 using the arithmetic element 16B. In this case, since the arithmetic element 16 is used by the arithmetic unit J(ll) which is continuing to process the instruction F, the arithmetic unit 20. is in a state of waiting for execution of the instruction G. On the other hand,
Arithmetic unit 20. When the instruction F finishes processing two machine cycles after executing the instruction F, the signal line OPE
1 back to the 1H" level. The calculation section 20% is connected to the signal line 0.
The state of the PEI is monitored, and when it is detected that the signal life 0PE l has reached the 1H2 level as described above, the calculation element 161 is released (unused state).
judge it as something. As a result, the calculation unit 201 takes in the instruction G into the internal instruction register.
sets the signal line PG to the "L" level, and also sets the signal line PG to the "L" level.Then, the arithmetic unit 301 uses the arithmetic element 161 to process the instruction G.
Depth.

Next, another embodiment of the present invention will be described. FIG. 6 is a diagram showing another embodiment of the present invention.

The same parts as in Figure @3 are given the same reference numerals and detailed explanations are omitted. In Figure 0, 31 is the IRJ l of Figure @1 and Figure 3.
Same as <, the instruction register (first instruction register) that holds the instruction fetched from xBix, and J2 is the instruction register that holds the contents of instruction register S1 (hereinafter referred to as 1n31) (
This is the instruction register (second instruction register) to be loaded). A signal line LG, which will be described later, is connected to the load clock, rear terminal, and clear terminal of the instruction register 32 (hereinafter referred to as IRJJ), and the state of the signal line LG changes from, for example, @H'''# to ''''L''. lR31 according to the transition of
The content held in is loaded and cleared to 1 in response to the transition from "L" to "R2." 3S is IRJJ.

This is a comparison circuit (hereinafter referred to as CMP) that compares the information in the register designation part included in each instruction held in the CMP. The symbols OP written in lR31°32 in FIG. @2 Operand storage register specification part, 9,
The situation in which RR type instructions are held in In81.82 is illustrated. The first in the RR type command. @2 Operand storage register designation section RJ, one of the general-purpose registers (not shown) indicated by RJ. CM
P s s is the RJ and I of the RR type instructions in IR81 when RR type instructions are held in xnsi and sz respectively.
Matching/mismatching of the RR type instruction in RJJ with RJ and 82 is detected respectively. This CMP j3
The comparison result is to compare the operation result of the preceding instruction (stored in one of the general-purpose registers specified by R4) with the first instruction (stored in one of the general-purpose registers specified by 2nd CRJ) of the next instruction. ) or the second o(run l'(R
(stored in one of the general-purpose registers specified by J)
It has meaning when used in . In other words, CM
Before executing the next instruction, PJl now detects whether a register in the general-purpose registers used when executing the instruction is used as a register for storing the operation result of the preceding instruction. ing. IPG is CMP
This is an output signal line for the comparison result (match/mismatch detection output) of J j.

In this embodiment, during the coincidence detection period of CMP J J, the signal line IPG is not at @L" level, and during the mismatch detection period (excluding the period of 1 machine clock), the signal line IPGFi' is In other words, CPM j l is designed to hold the match detection state for an additional l machine clocks.

401-40rnArithmetic units having almost the same configuration as the arithmetic units io1-20rn shown in FIG.
This is a signal line that is commonly connected to the load black, rear, and clear terminals of rn, IRJ2, and IRJ2. Arithmetic unit 401~
40o is different from the calculation units 201 to 20m in FIG. 3 as follows. The arithmetic units 401 to 40- monitor the commands sent from the IR 31 onto the O'Heresy path 21, monitor the signal lines 0PFXJ to OPEn, and also monitor the signal lines 0PFXJ to OPEn. It is now possible to monitor the
At least during the period when the signal line IPG is at the @L" level, the calculation units 401 to 40 are forced to wait for the above-mentioned instruction to be received. Furthermore, the calculation units 401 to 40m have two machines in which the execution stage of the instruction in the execution state is 2. If the instruction requires more than one cycle, change the signal 2in LG from ``H'' level to ``'' to load the instruction from xnsi to IRJ2.
In this embodiment, the operations [401 to 40ffi] set the signal line LG to ``''LL level one machine cycle after executing the instruction, and set the L'L level of the required execution stage. The signal line LGt@H'' level is returned to the signal line 5 before the machine cycle.The calculation units 401 to 401 also monitor the signal line LG.The calculation units 401 to 40m monitor the signal line LG Even if the command sent out is a command to be executed by the self-playing nose, if the execution stage of the command requires 2W syncycles or more, at least the period when the signal line LG is at the 1L" level. During this time, the user is forced to wait for the above command to be retrieved. This is because lR111 is in use,
The calculation units 401 to 46 indicate that the next instruction cannot be loaded (saved) in succession. is detected in advance based on the contents of the instruction (Is it an instruction that requires 2-v syncycles or more and a ■-dead to IRJj?) and the state of the signal line LG to prevent the occurrence of problems. It's for a reason.

Next, the operation of the configuration shown in @6 will be explained with reference to the timing chart shown in FIG.
Takes instruction J held in K and executes calculation element 1
6. Assume that the execution of arithmetic processing is started using .

At this time, the signal lines PG, LG, and IPG are at low level and 'H# level, respectively. The signal line OPE is at the "L# level."If the above instruction J is an instruction that requires two or more machine cycles, for example, four machine cycles, the arithmetic unit 40m executes the instruction J and then After 1w syncycle (at the end of tX3 period in the timing chart in Figure I!7), the signal twin LGt-@L' level is set. As a result, the instruction J held in IRjJK becomes I
Loaded into R31. At this time, the calculation unit 40m returns the signal line PG to the "IH level."
1 holds an instruction to be executed next, for example, instruction K. This instruction requires, for example, an execution stage of 1W thin cycle.

IRJJK The held instructions are sent to each operation unit 401 to 40I! via the operation bus 21. Transferred to 1. Here, it is assumed that the operation 11A4o determines that the above-mentioned instruction K should be executed. Then, the arithmetic unit 40 detects the 1H" level of the signal line IPG (CMP J J detects a mismatch in the register designation part), the arithmetic element to be used, for example, the arithmetic element) 11.0 unused state II (signal line OPE J ``H'' level) and determines that the instruction K is an instruction that will be completed in one machine cycle, the instruction K is taken into the internal instruction register regardless of the ``L'' level of the signal line LGO. Arithmetic unit 4
The offIId signal line PG is set to 1L" level, and the signal twin OPE j is set to the same (@L" level. After that, the calculation unit 40□ executes the instruction K using the calculation element 161. The calculation unit 40rn One machine cycle after executing instruction K (in this example, at the end of instruction execution), signal line PGt
- @Return to H' level. As a result, the next instruction to be executed after the instruction, such as instruction R, is held in IRJ 1. For example, this instruction is an instruction that requires an execution stage of 3 machine cycles.
~46mK transferred. Here, it is assumed that the arithmetic unit 401 determines that the above instruction should be executed. If the instruction is an instruction that requires an execution stage of K2-r syncycles or more as described above, as shown in the timing chart of FIG. 7, even if the signal twin IPG is "H".
level, the calculation element to be used, for example calculation element 111, is in an unused state (signal twin OPK 1 is ""
Even if there is a HH level, if the signal line LG is at the 1Lm level, the arithmetic unit 401 is forced to wait until the signal line LG reaches the @Hm level to receive the above-mentioned command. In other words, execution of the instruction J in parallel with the currently executed instruction J is awaited. If an instruction requiring 112-v thin cycles is executed in parallel with instruction J, IRjJK, which should save the instruction, will
This is because it becomes impossible to save the instruction to IRJ1. If the instruction is an instruction that completes in 11 syncycles, it is clear that the instruction will be fetched and executed.

The arithmetic unit 40 continues executing the instruction J, and one machine cycle before the execution stage J) (4 machine cycles) required to execute the instruction J (at the end of the 5th cycle in the timing chart of Fig. 187). Return the signal line LG to @H” level,
The arithmetic unit 40 monitors the signal line LG, and when the signal line LG5f@H' level is set, the instruction stored in the IFtJJ is loaded into the internal instruction register.
At this time, the calculation unit 4o1 operates on the signal line p.

is set to 1L" level and one calculation element 16.
signal line OPE to indicate that it is in use.
J is brought to the @L'' level. Thereafter, the arithmetic unit 401 uses the arithmetic element 161 to execute the instruction.

The arithmetic unit 401 sets the signal line LG to the 1L# level one machine cycle after executing the instruction. This is a trap, D. The instructions held in IRJJ are loaded (saved) into IRJJ.

At this time, the calculation unit 40. is returned to the signal line PGt-@H" level. This causes J to hold the next instruction to be executed, for example, instruction M. An instruction that performs an operation using the contents of the register in the general-purpose register specified by the first operand storage register specification part R1.
It is assumed that the instruction is completed in one machine cycle.

CMP J, 9 is the information of the first operand 0 storage register specification part R1 of the instruction held in IRJ J,
Compare and detect whether or not the first o (land storage register specifying part R1 information or wc2 o) (2nd o) of the instruction M held in lR81 matches the ZOS! specifying part R20 information. In this example, , since a match is detected, the open signal line IPG for the match detection period + 1 machine cycle is CM
P 3 J K is set to @L” level. On the other hand, the command M held in IRJJ is set to
1 to the calculation units 401 to 4orn.

Operation during execution of instruction WI640. Each operation unit except for
l. 'For example, assume that the arithmetic unit 4o has determined that instruction M should be executed. However, the signal line IPG is 1
Hm level, even if the arithmetic element to be used, such as arithmetic element 16, is in the unused state tQ (signal line 0PEj is @H" level) and the instruction M is an instruction that completes in one machine cycle. , calculation section 4
01 is made to wait until the signal 2-in IPG reaches the 1H" level before receiving the instruction M.

This is because if instruction M is executed before the execution stage of the rounding instruction, which is an instruction that uses the operation result of the preceding instruction, is completed, the execution result will be incorrect.

The arithmetic unit 401 continues to execute instruction 4b, and outputs a signal one machine cycle (at the end of the seventh cycle in the timing chart of FIG. 7) before the execution stage (three machine cycles) required to execute the instruction. When the line LG returns to the 1Hm level and the signal line LG transitions from ``L# to -H'', IRj J is cleared. As a result, CMP J
The above-described match detection of J is completed, but since CMP J j holds the match detection state for one more machine cycle, the signal line IPGO1L level is held until the end of execution of the command. Then, at the end of execution of the instruction (7th
In the timing chart shown in the figure, when the signal line IPG is returned to the "H" level at the end of the 8th period), the calculation unit 40
M determines that the execution stage of the preceding instruction has been completed, and executes instruction M using the nine operation results (the contents of the registers in the general-purpose registers) obtained by executing the above instruction.

In this way, according to the real-world side, the usage status of general-purpose lenostano can be detected in advance at the register level, so even the instruction that performs an operation using the operation result of the preceding instruction can be executed in parallel with the preceding instruction. This can prevent problems that could result in incorrect results being obtained. In addition, if a general-purpose register can be used as one of the calculation elements, the above problem can be prevented even if the usage status of the general-purpose register is not detected at the nostar level, but instructions that continue even if the used registers do not match , the execution of which will have to wait, resulting in lower general-purpose register usage efficiency and lower processing speed. In contrast, in this embodiment, the usage status of general-purpose registers can be detected at the register level, and if the used registers do not match, instructions can be executed in parallel, thereby improving the usage efficiency and processing speed of general-purpose registers.

Note that in the other embodiments described above, CMP3J is the first instruction storage register designation part RJ, @2 of the RR type instruction.
(Although we have explained the case where the information in the land storage register specification section R2 is compared, RR type instruction and RX type instruction, RX
The same applies to the case where the information in the register designation part (including the index register designation part) of a type instruction, an RR type instruction, and an RX type instruction is compared. However, CMP3
3 is a function to determine the type f (type) of an instruction, and according to the result of this determination, information on the register specification part to be compared is sent to Ht3.
It is necessary to have a function to select from IRJJ, 51 (or a function to mask information that is not a comparison target in each instruction held in IRJJ, 51).

Effects of the Invention As detailed above, according to the parallel computing device of the present invention, parallel processing in the execution stage can be efficiently performed, so disturbances in the pipeline flow can be significantly reduced, and the computing speed can be increased. can be achieved.

[Brief explanation of drawings]

Figure 1 is a diagram showing the configuration of a general arithmetic unit.
The cz diagram is a diagram for explaining the flow of a general pipeline.
FIG. 5 is a timing chart for explaining the operation of the above embodiment, FIG. 5 is a diagram for explaining the flow of the four ideal lines in the above embodiment, and FIG. 6 is a block diagram showing another embodiment of the present invention. , FIG. 7 is a timing chart for explaining the operation of the other embodiment. 11... Main memory (MEM), J! ...Instruction parable ν7a (IB), 13.31.32...Instruction register (IR), 14.201~2o, 40s~40ol・-
Arithmetic unit, 161-16n... Arithmetic element, 22.
...Element in use information line, 3 J-...Comparison circuit (CMP), OFF, 1~OPE n. PC, LG, IPG-・Signal line. Applicant's agent Patent attorney Takehiko Suzue 307

Claims (7)

[Claims] (1) Instructions P and F in which instructions prefetched from the main memory are sequentially stored, an instruction register in which instructions retrieved from these instruction P and A are stored, and the above-mentioned instructions stored in this instruction register. , a plurality of arithmetic units each having a unique arithmetic processing function to execute an instruction, a plurality of arithmetic elements shared by these arithmetic units, and a plurality of arithmetic elements commonly connected to the plurality of arithmetic units and Each of the arithmetic units monitors the instruction placed in the instruction register, and if this instruction is fetches the instruction placed in the instruction register according to whether or not it is an instruction to be processed by the instruction register and the state of the element usage information line, and performs the operation using the corresponding arithmetic element; The device is configured to output a signal indicating that the arithmetic element is in use to the element usage information line, and to set an instruction to be executed next from the instruction pad in the instruction register. Parallel computing device. (2) Instructions in which instructions read ahead from main memory are stored sequentially - 1. F1, this instruction P, the @1 instruction register where the instruction fetched from F is stored, and the above instruction whose number is stored in this first instruction register Kll is stored.
2 instruction registers, a comparison circuit that compares these I@l and the information of the renostar specification part included in each instruction stored in the second instruction register, and the first instruction register Kft. 1 each to execute the command
a plurality of arithmetic units having arithmetic processing functions, a plurality of arithmetic elements shared by each of these arithmetic units; Each operation section monitors the above-mentioned instruction placed in the first instruction register, and at least confirms that this instruction is processed by the own execution section. Whether it is a command to be executed or not, the status of the element usage information line above,
In accordance with the comparison result of the comparator circuit, the @l command takes in the instruction numbered by Nostar KffR, and performs the calculation using the corresponding calculation element, while receiving a signal indicating that this calculation element is in use. is output to the element usage information line, and the instruction placed in the first instruction register is output to the second instruction register as necessary.
A parallel processing device characterized in that it is configured to store an instruction in an instruction register, and to store an instruction to be executed next from the instructions N and F in the first instruction register. (3) Parallel processing according to claim 2, characterized in that the arithmetic unit is made to wait for the fetching of the instruction stored in the first instruction register at least during the match detection output period of the comparison circuit. Computing device. (4) If the execution stage of the instruction stored in the first instruction register requires two or more cycles, the calculation unit in the calculation execution state places the instruction in the second instruction register. A parallel computing device according to claim 3, characterized in that: (5) The arithmetic unit located in the upper r operation execution state cape performs a load clock to place the instruction stored in the army 1 instruction register into the upper 1 rillE2 instruction register. The load clock is output one cycle before the end of the execution stage of this instruction. 5. The parallel computing device according to claim 4, wherein the output of the signal is stopped. (6) Each performance I1 above. 6. The parallel arithmetic device according to claim 5, further comprising a load clock signal line which is commonly connected to the @2 instruction register and the load clock signal line to which the load clock signal is transferred. (7) If the execution stage of the instruction placed in the w, l instruction register is an instruction that does not complete in one cycle, the arithmetic unit is connected to other arithmetic units via at least the load clock drop signal line. 7. The parallel arithmetic device according to claim 6, wherein during a period when the load clock signal is being transferred from the load clock to the load clock signal, the fetching of the instruction stored in the empty instruction register is made to wait.