JPH0322042A - Mircoprocessor control system - Google Patents

Abstract

PURPOSE:To easily find misprogramming by storing a specific address and deciding that the runaway state occurs when the instruction in this specific address is not executed within a certain time. CONSTITUTION:If the time elapses without input of a reset signal, and the counted value of a counter 5 reaches the upper limit value held in an upper limit value register 9 it decided, that the runaway state occurs, then an interrupt signal 11 of a CPU 2 from a comparator 10 is outputted. When the interrupt signal 11 is inputted, the CPU 2 interrupts execution of a program. It is considered that the cause of runaway exists in a program range between the specific address outputted from an address register 1 at the time of resetting the counter 5 and that outputted from the register 1 when it is decided that the runaway occurs. Thus, only this range is checked at the time of searching the cause of runaway.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a control system for a microprocessor. In particular, the present invention relates to a control method for detecting a runaway state of a program.

[Conventional technology]

Conventional. If the microprocessor goes out of control when executing a program, The user interrupts execution of the program and uses a debugging mechanism to step through the program from the beginning to find the cause of the runaway.

[Problems to be Solved by the Invention] However, in the conventional control system described above, when a runaway occurs, the cause of the runaway must be searched for in order from the first instruction of the program, which is time-consuming. It takes a while. The disadvantage is that it is difficult to find the cause.

The present invention detects when a microprocessor goes into a runaway state while executing a program. The purpose is to provide a microprocessor control method that stops program execution.

[Means for Solving the Problems] The present invention comprises: storage means for storing a specific address specified by a user; comparison means for comparing the specific address stored in the storage means with an address output by a processor; A counter whose count is updated at predetermined time intervals and reset by a match signal from the comparison means, and which generates an interrupt to the processor when the count of the counter reaches a predetermined upper limit. It is characterized by having a means.

[Operation] In the present invention. Store multiple specific addresses in the address register. If the microprocessor does not execute the instruction at the specific address within a predetermined time, it determines that the program is running out of control and stops executing the program.

[Examples] Examples of the present invention will be described below with reference to the drawings.

ml diagram is a configuration diagram showing one embodiment of the present invention.

Referring to FIG. 1, the microprocessor control system of the present invention includes an address register 1 that stores a specific address specified by the user, a CPU 2, comparators 4 and 10, a counter 5, and a constant register that holds a constant to be added. 6, and an upper limit value register that holds the upper limit value specified by the user.

Address register 1 stores a plurality of specific addresses specified by the user. These multiple specific addresses are
It may be determined based on the size of the program and the time required for execution.

The upper limit value register 9 holds an upper limit value that specifies the upper limit of the count number of the counter 5. This upper limit value is set larger than the number of counts counted by the counter 5 during the time until the program at the specific address held in the address register 1 is executed.

Next, the operation will be explained.

Register 1 inputs to comparator 4 a specific address of a program to be executed next among a plurality of specific addresses. The CPU 2 also inputs the address 3 of the program currently being executed to the comparator 4.

The comparator 4 compares the address 3 input from the address register 1 with the address input manually from the CPU 2,
When the two addresses match, a counter 5 reset signal 8 is output.

The counter 5 outputs to the comparator 10 a count number obtained by adding a constant held in the constant register 6 by an adder 7 every predetermined period of time to the count number. When the reset signal 8 is input from the comparator 4, the counter 5 resets its count number. When time passes without the reset signal 8 being input and the count number of the counter 5 becomes equal to the upper limit value held in the upper limit value register 9, it is determined that the runaway has occurred, and the comparator 10 outputs C
The interrupt signal of PU2 is output.

When the CPU 2 receives the interrupt signal 11, it interrupts the execution of the program. In this way, when a runaway occurs, program execution is automatically interrupted, so if the cause of the S run is memory or program corruption, the damage can be kept to a minimum. Also, the cause of the a run is the previous one. This is considered to be in the program from the specific address that was output from the address register when the counter 5 was reset to the specific address that was output from the register 1 when the runaway was determined.

Therefore. 'When trying to find out the cause of 4-run, it is only necessary to examine this area.

[Effects of the Invention] As explained above, the present invention stores a specific address and determines that a runaway condition exists if the instruction at that specific address is not executed within a certain period of time. Since the range in which a program error exists in a program can be limited, the program error can be easily discovered and the time required to debug the program can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention. 1...Address register, 2...CPU, 3...
Address output by CPU. 4... Comparator, 5...
counter. 6...Constant register, 7...Adder, 8
... Reset signal, 9 ... Upper limit value register, 10.
... Comparator, 1 1 ... Interrupt signal.

Claims (1)

[Claims] 1. A storage means for storing a specific address specified by a user, a comparison means for comparing the specific address with an address output by the processor, and a count number updated at every predetermined time and a match from the comparison means. A control system for a microprocessor, comprising: a counter that can be reset by a signal; and means for generating an interrupt to the processor when the count of the counter reaches a predetermined upper limit.