JPH03158936A - Testing method for program - Google Patents

Abstract

PURPOSE:To facilitate the contention test of resources by delaying a specific program or the operation time of a specific processing of a specific program to an arbitrary value, and giving a difference to the execution speed of every program. CONSTITUTION:In the case the section to processings S4 - S7 is designated as an execution time delay section with respect to a program 1, a processor drives and executes an interruption processing program by the head of the processing S44, and executes the interruption for ending the interruption processing program by the end of the processing S7. Subsequently, the execution of the processing S5 of the suspended program is restarted, and after the execution of the next one instruction 4 is ended, the processor generates an interruption again. Thereafter, until the processor executes an interruption generation end instruction 6, an during interruption processing program 5 is executed at every one instruction. In such a way, during the instruction execution time of the program, the interruption processing program 5 is executed at every one instruction, therefore, it becomes virtually longer by the execution time portion of the interruption processing program, and the test of a contention management processing can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for testing a program, and particularly to a method for testing a program by measuring a delay in execution time.

[Conventional technology]

The O8 of an electronic computer is generally multi-programming or multi-user ○S in which multiple programs are executed simultaneously for the purpose of efficient use of hardware resources and improvement of responsiveness. Here, multiprogramming means 2
The above programs operate in a time-division manner, and the multi-user O8 means that the O8 is configured to operate two or more of these programs.

In order for programs that are processed in parallel to work together under multiprogramming O8, two or more programs must access a common data area (shared data) in main memory. is necessary.

In this case, inconveniences may occur if shared data is updated by multiple pro gamers at the same time.

Assume that there are two programs 1 and 2, and shared data that is accessed in common is located in main memory.

For simplicity, the operation of each program is as follows:
The movement of program 1 increases the value of the shared data by 5. After that, the action of program 2 is to increase the value of the shared data by three. Therefore, if the initial value is 1, (1+5)
This means that +3=9 shared data.

The sequence of machine language that executes each program is as follows.

Movement of program 1: (A1) Read the shared data value into the shared data buffer within program 1.

- (A2) The value of the buffer for shared data in program 1 is 5.
Add.

(A3) Write the value of the shared data buffer in program 1 to the shared data.

Movement of program 2: (B1) Read the shared data value into the shared data buffer within program 2.

(B2) Set the buffer value for shared data within program 2 to 3.
Add.

(B3) Write the value of the shared data buffer in program 2 to the shared data.

Incidentally, related conventional examples include Japanese Patent Application Laid-Open No. 60-65350.

[Problem to be solved by the invention]

Instructions (Al) and (A2) in program 1.

Execution of (A3) and (Bl) in program 2.

If the executions of (B2) and (B3) are different in time, the value of the shared data may not be 9.

For example, as shown in Figure 2, (A1) is executed, then (A2)
This is a case where (B1) and (B1) are executed at the same time (CPU processing - considering above), then (A3) and (B2) are executed at the same time, and finally (B3) is executed.

As a result, the shared data temporarily becomes 6 due to (A3), but the shared data becomes 4 instead of 9 due to execution of (B3).
It becomes.

A method to prevent this problem from occurring is to prevent two or more programs from updating shared data at the same time, that is, to allow them to mutually exclude each other.

A conflict management processing program manages conflicts in this shared data and achieves mutual exclusion.

In testing the conflict management processing program, it is necessary to intentionally cause conflicts in shared data as shown in Figure 2, so while one program is updating shared data, it is necessary to Update processing must be performed. However, the actual execution time of the shared data update process is IMIP S (Million
Input per 5 seconds on an electronic computer is only a few μs, so when one program attempts to update shared data, it is possible that another program is in the process of updating shared data. sex is very small.

In reality, even if there is an error in the conflict management process, inconveniences occur only once every few years, even in online systems that operate 24 hours a day.

However, errors in the creation of conflict management processing programs are highly likely to lead to system failure, and the social impact of such occurrences is large, so it is necessary to reliably detect them through testing.

However, since the possibility of a shared data conflict occurring itself is small, it has conventionally been difficult to reliably test conflict management processing that requires the occurrence of a shared data conflict.

In order to reliably test the conflict management processing program mentioned above, it is necessary to extend the execution time of shared data update processing by executing instructions slowly, thereby increasing the possibility of shared data conflicts occurring in terms of time. There is a need to. In addition, by intentionally increasing the CPU load, the CPU
I would like to test the movement of In such cases as well, it would be effective to delay the processing of some programs or some steps thereof.

The above conventional example, JP-A No. 60-65350, is an example of lengthening the execution time, but this is an attempt to see the detailed movement of the program by slowing down the movement of the program, and the contention management process There is no mention of an increase in load.

An object of the present invention is to provide a program control method in which a competition management process test and a CPU load increase test are realized by varying the execution time.

[Means to solve the problem]

According to the present invention, (1) First, the section in which the interrupt processing program operates is specified. Specifically, the beginning and end of a program to be delayed or a step to be delayed whose instruction execution time is to be changed is specified. 0 Upon receiving this designation, the processing device starts the interrupt processing program at the beginning position, and terminates the interrupt processing program at the end position. (2) Furthermore, in the interval between the start and the end, the above-mentioned interrupt processing program is activated to slow down the execution speed of the program or step during that period.

■This interrupt processing program is a program whose execution time can be set arbitrarily.

Specifically, the processing device functions ① and @ may utilize trace interrupts used during debugging. The I-race interrupt is a function in which the processing device generates an interrupt by itself every time one instruction is executed. Therefore, if the target is a program, the interrupt processing program will work for all steps constituting that program, and if the target is one step, the interrupt processing program will work only once for that step.

[For production]

FIG. 1 is a diagram showing the principle of the present invention, and will be explained using FIG.

1 indicates the sequence of program instructions, and 2 indicates the execution order of the processing device.

Assume that for this program 1, the section from processing 84 to S7 is designated as an execution time delay section. When this designation is made, the processing device starts and executes the interrupt processing program at the beginning of process S4, and performs an interrupt to end the interrupt processing program at the end of process S7. That is, when trace interrupts are adopted, the processing device executes instruction 4, and after executing interrupt generation start instruction 3, generates an interrupt every time execution of one instruction is completed. When an interrupt occurs, the processing device interrupts the processing of the currently executing program and executes the interrupt processing program 5. The interrupt processing program 5 performs arbitrary time processing and ends the interrupt processing.

After the interrupt processing path r, the processing device resumes execution of the interrupted program process S5. After the execution of the next instruction 4 is completed, the processing device generates an interrupt again.

Thereafter, the interrupt processing program 5 is executed one instruction at a time until the processing device executes the interrupt generation termination instruction 6.

As a result, the instruction execution time of the program is apparently increased by the execution time of the side interrupt processing program, since the interrupt processing program 5 is executed for each instruction.

〔Example〕

Hereinafter, an embodiment in which the present invention is used for a resource contention test will be described with reference to FIGS. 3, 4, 5, and 7.

The resource conflict test is a test for mutual exclusion of conflict management processing parts by causing conflict in access to resources shared between multiple programs.

In this embodiment, processing unit interrupts are used as a means of slowing down instructions. FIG. 7 is a block diagram of the computer system, and FIG. 7 is a processing bag fi'iTO+.

It consists of a main memory 102 and peripheral devices 103. Processing device 1
01 consists of an instruction control section 104 and an execution unit 105, and upon reading and decoding of instructions from the instruction control section 104, the execution unit 105 executes the instructions. execution unit 10
5 is a register group 106. It consists of an arithmetic unit 108, and the arithmetic unit h108 performs a predetermined operation while exchanging data with the register group 106. Status register 107 in register group 106 plays an important role in this embodiment. 33rd
The figure shows an overview of interrupt processing.

In general, an interrupt occurs when the peripheral device 103 requests a service from the processing unit 101 or when an error occurs while executing a program stored in the main memory device It is used to execute stored processing programs. This embodiment uses trace interrupts.

When an interrupt occurs, the processing unit 1.01 checks each peripheral device 10 to identify which processing program to execute.
The interrupt vector number assigned to 3 (signal indicating the interrupt type) is received from the peripheral device 103, the interrupt vector address that stores the start address of the interrupt processing program is calculated from the interrupt vector number, and the interrupt vector is Read and execute the interrupt handling program.

To slow down the instruction execution speed by interrupt processing, generate an interrupt every time one instruction is executed, and use the time delay (
For example, it is necessary to execute the interrupt processing program 1 (no-operation processing, which is processing in which nothing is executed) during that time, and to delay the time using the interrupt processing program.

To generate an interrupt every time one instruction is executed, processing device 1
Uses the 01 instruction trace function (1-race interrupt function). The instruction tracing function is a function in which the processing device 101 generates an interrupt every time one instruction is executed when the instruction tracing bit of the status register 107 of the processing device is 1. In order to use this function, immediately before the conflict management process start part IS of program 1 in FIG.
A process for setting the instruction trace bit of the status register 107 to "0" is added, and a process for setting the instruction trace bit of the status register 107 to 0 is added immediately after the contention management processing path r part molecule I':.

Note that the section where the instruction execution speed is slowed is the section where an interrupt is generated, so by changing the position of the operation processing of the instruction tracking bit of the status register 107, the section where the instruction execution speed is slowed can be set arbitrarily. Become iJ Noh.

In order to execute the interrupt processing program 11 when an interrupt occurs, it is necessary to register the start address of the interrupt processing program 2 in the interrupt vector. Therefore, the address of the interrupt vector is calculated from the interrupt vector number of the instruction tracking interrupt, and the interrupt Register the start address of the processing program.

FIG. 4 is a flowchart of the interrupt processing program. Since the interrupt processing program has a 1:1 gain in time to slow down the apparent execution speed of instructions, it is sufficient to set the number of loops and run the program in a loop. The number of loops can be arbitrarily set depending on the time to delay the instruction.

Furthermore, since the purpose of the interrupt processing program is to buy time, it is also possible to have the interrupt processing program monitor whether or not a conflict occurs in shared data.

The conflict management processing program places another program that attempts to update shared data in a waiting state while one program is updating the shared data. The program placed in the waiting state is registered in a table that manages the waiting state, and the program that is updating the shared data is released from the waiting state by the conflict management processing progera 11 after the update processing path Y.

Therefore, whether or not a conflict has occurred in shared data can be determined by monitoring the table for managing wait states.By having the interrupt processing program monitor this table, it is easy to check whether or not a conflict has occurred. This improves test efficiency. By outputting the contents of the table when a conflict occurs, depacking efficiency is improved.

Also, instead of generating an interrupt, you can rough 1 hard instruction.
~ It is also possible to slow down the execution speed of instructions by simulating with software.

In order to generate an interrupt for each instruction, the instruction tracing function (referring to trace interrupts during depacking) of the processing device was used. In the instruction tracking function, the interrupt interval specified by the operator (from 84 in the example in Figure 1) is stored in the status register.
This is a register for setting the range S7 to S7. The processing device looks at the specified data in this register and instructs the activation and termination of the interrupt. When the instruction trace bit of the status register of the processing device is 1, an interrupt is generated every time one instruction is executed. An example of processing for using this trace interrupt function is shown in FIG. FIG. 5 shows an example in which program 1 is interrupted but program 2 is not interrupted. In addition, program 1 is 84
This is an example of an interrupt in the interval from ~S7, and an example in which the interrupt program ("I", +) is executed after each execution of 84 to S7 (after the processing time of τh τ2...) showed that. As a result, the probability of conflict occurring is normally low, but as you can see in the processing of program 1,
゛3 processes for conflict occurrence occurred,
You can intentionally create conflicts.

In order to realize the above process, add a process to set the instruction tracking bit of the status register to 1 immediately before the conflict management process start part IS of program 1 in FIG. Immediately after, a process for returning the instruction trace bit of the status register to O may be added.

Now, in FIG. 5, since program 2 does not use the present invention, the execution time T2 of the conflict management processing part is t, =
It becomes 0.5. Assuming that the overall actual waiting time of program 2 is t;=10 and that other programs can be executed uniformly during execution, the probability that a conflict will occur is calculated as follows: execution time of conflict management processing part/total It is expressed as the execution time of 0.05.

However, in the program 1 using the present invention, the interrupt processing program is executed every time one instruction of the conflict management processing section is executed, so the execution time '1'3 of the conflict management processing section is 1. =]:l, making it 26 times longer. Since the overall execution time of program 1 is t=21, the probability of conflict occurring based on the above assumption is 0.62, which is 12 times that of the case where the present invention is not used.

In this way, the present invention can increase the probability that competition will occur.

Next, in an example in which the present invention was used for load tests 1 to 1, FIG.
This will be explained using FIG.

A load test is a test of increasing the load on a processing device and drastically reducing the execution time of the program by the processing device, and examining the effect on the program whose execution time has been drastically reduced and other programs.

]6- The interrupt processing program uses flowchart 1- in FIG.

The operation of the program will be explained using FIG.

The interrupt generation section is the entire program (IS to TE).

Immediately after the program starts, an interrupt occurs after the - instruction is executed. As a result, the program execution time Ll-t2 becomes (program processing time Σl'l)+(interrupt processing program execution time ΣT2).

Therefore, even if only one program is running, the rate at which the processing device is processing the program is ΣT1
/(Σ1゛1+ΣT2), and by changing the number of loops of the interrupt processing program, it becomes possible to easily adjust the execution time T2 of the interrupt processing program and execute the program with an arbitrary value of load.

Although trace interrupt examples were used in each of the above embodiments,
That type of interrupt may substantially delay execution time.

〔Effect of the invention〕

According to the present invention, by slowing down the operation time of a specific program or specific processing of a specific program to an arbitrary value and making a difference in execution speed for each program, contention for resources shared by multiple programs occurs. The probability of doing so can be increased.

Therefore, a resource competition test, which has been difficult in the past, can be easily performed.

Furthermore, by slowing down the execution speed of the instructions of the entire program, it is possible to place a large load on the processing device by executing fewer programs.

Therefore, load tests can be easily performed by executing a small number of programs.

[Brief explanation of the drawing]

Fig. 1 is a diagram of the principle of the present invention, Fig. 2 is a flowchart for updating shared data, Fig. 3 is a flowchart showing an overview of interrupt processing, Fig. 4 is a flowchart of an interrupt processing program, and Fig. 5 is a flowchart of the present invention. FIG. 6 is a time chart when the present invention is used for a load test. FIG. 7 is a diagram of a computer system according to the present invention. 1... Arrangement of task instructions, 2... Execution order of processing device, 3... Interrupt generation start instruction, 4... Task instructions, 5... Interrupt processing program.

Claims (1)

[Claims] 1. In a program testing method that performs an operation to apparently slow down the execution speed of program instructions, the above operation generates an interrupt every time one instruction of the program is executed;
A method for testing a program, characterized in that the execution time of an interrupt processing program for time delay is added to the execution time of each instruction. 2. In a program testing method that performs an operation that apparently slows down the execution speed of program instructions, the above operation is performed by simulating hard instructions with software;
A program testing method characterized by adding overhead time by simulating the execution time of each instruction. 3. A program testing method according to claim 1, characterized in that the execution time of each instruction is made variable by making the processing time of the interrupt processing program variable. 4. A program testing method according to any one of claims 1 to 3, characterized in that a range in which the execution speed of instructions is to be slowed is specified, and instructions within that range are executed slowly. 5. A program testing method according to any one of claims 1 to 4, characterized in that an event occurring as a result of the test is monitored during the instruction execution delay process. 6. A program testing method, characterized in that a test is performed using the testing method according to any one of claims 1 to 5 in a multi-program system in which a plurality of programs can be executed in parallel. 7. The method for testing a program according to claim 6, characterized in that the usage time of hardware resources shared by the programs is lengthened by delaying instruction execution of a plurality of running programs. 8. In the test method according to claim 7, when a plurality of programs operate resources shared among programs that require exclusive control, instruction execution of a processing portion that operates the resources shared by some programs is delayed. A program testing method characterized by making a difference in the execution speed of each program and increasing the probability of occurrence of contention for shared resources.