JPH05204685A - Electronic computer - Google Patents

Abstract

PURPOSE:To attain re-execution at the time of generation of a parity error in instruction fetching. CONSTITUTION:At the time of generation of a parity error, a sequencer 18 allows an interruption control means 21 to reload an instruction part generating the parity error by a parity error signal 17. When no parity error is generated at the time of detecting that an instruction reloaded based upon a coincidence result from a comparator 20 coincides with an instruction address generating the preceding parity error, the instruction is continued, and if a parity error is generated, a double parity error signal 16 is generated from an AND gate 15 and the means 21 is allowed to abort the instruction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a control device for an electronic computer. In particular, the present invention relates to a control device that can re-execute a fetched instruction even if a parity error occurs.

[0002]

2. Description of the Related Art Conventionally, when a parity error occurs in an instruction fetch, an electronic computer generates an interrupt and aborts the task.

[0003]

However, in such a conventional electronic computer, when a parity error occurs in the instruction fetch, even if the parity error is reexecuted from that location, the parity error occurs again, and the instruction is reexecuted. There was a problem that the task could not be aborted and re-executed because of the danger of entering an infinite loop.

The present invention solves the above-mentioned drawbacks, and an object of the present invention is to provide an electronic computer which can be re-executed when a parity error occurs in instruction fetch.

[0005]

SUMMARY OF THE INVENTION The present invention is an electronic computer equipped with a parity check means for outputting a detection signal when a parity error in an input instruction is detected, and a first interrupt signal based on the detection signal. An interrupt means for outputting, an interrupt control means for controlling the reloading of the instruction part in which the parity error has occurred based on the first interrupt signal, and a reset signal set and input based on the detection signal or First storage means for resetting based on an instruction end signal, second storage means for storing an instruction address when the parity error occurs based on the detection signal, and reloading executed second storage means Reset means for outputting the reset signal when the contents of the above and the instruction address of the reloaded instruction portion match,
Re-detection means for outputting a re-detection signal when the detection signal corresponding to the reloaded instruction is input in the first storage means in the set state, and the interrupt means when the re-detection signal is input To output the instruction end signal and the second interrupt signal, and the interrupt control means includes means for performing control to abort the instruction being executed based on the second interrupt signal. And

Further, according to the present invention, the parity check means adds and stores a parity checker for performing a parity check of the instruction for each byte and a detection result of the parity checker for each byte of the instruction. A prefetch buffer, a decoder that decodes the contents of the prefetch buffer and outputs an instruction length, an instruction length decoder that outputs a signal indicating a portion that is the above instruction based on the output of this decoder, and each of the prefetch buffers stored in the prefetch buffer. A first AND gate for taking a logical product of a detection result and an output signal of the instruction length decoder; and an OR gate for taking a logical sum of outputs of the first and gates and outputting the detection signal, The second storage means counts the instruction address of the instruction being executed based on the input addition result and controls the interrupt. A program counter which is reset upon reloading the control of the stage, an adder providing the addition result by adding the instruction length from the decoder and the output of the program counter to the program counter,
An error program counter that stores the output of the program counter based on the detection signal, and the reset means compares the output of the program counter with the output of the error program counter and outputs a match result when they match. And a valid flag which is set at the time of reloading under the control of the interrupt control means and reset based on the reset signal, and the output of the valid flag and the coincidence result are ANDed to output the reset signal. And a second AND gate to perform.

[0007]

The interrupt means outputs the first interrupt signal based on the detection signal. The interrupt control means controls to reload the instruction part in which the parity error has occurred, based on the first interrupt signal. The first storage means is reset based on a reset signal or a command end signal that is set and input based on the detection signal. The second storage means stores the instruction address when the parity error occurs based on the detection signal. The reset means outputs the reset signal when reloading is executed and the contents of the second storage means and the instruction address of the reloaded instruction portion match. The re-detection means outputs the re-detection signal when the detection signal for the instruction reloaded in the set state of the first storage means is input. The interrupt means outputs the command end signal and the second interrupt signal when the re-detection signal is input. The interrupt control means controls to abort the instruction being executed based on the second interrupt signal.

As described above, if a parity error occurs in the instruction fetch, it can be re-executed.

[0009]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a computer according to an embodiment of the present invention.

In FIG. 1, the electronic computer comprises a parity check means for outputting a parity error signal as a detection signal when a parity error of an input instruction is detected.

A feature of the present invention is that the sequencer 18 serves as an interrupt means for outputting the first interrupt signal based on the parity error signal, and the instruction that has generated the parity error based on the first interrupt signal. An interrupt control means 21 for controlling the reloading of the part, an error flip-flop 14 as a first storage means for resetting based on a reset signal or an instruction end signal 19 which is set based on the parity error signal 17 or is input, and a parity error. Signal 17
A second storage means for storing an instruction address when a parity error occurs based on the above, and when the contents of the second storage means and the instruction address of the reloaded instruction portion match with each other when a reload is executed. The reset means for outputting the reset signal and the re-detection means for outputting the double parity error signal 16 as the re-detection signal when the parity error signal 17 for the instruction reloaded in the set state in the error flip-flop 14 is input. The sequencer 18 includes a gate 15, and the sequencer 18 includes means for outputting an instruction end signal 19 and a second interrupt signal when the double parity error signal 16 is input.
1 is to include means for controlling to abort the instruction being executed based on the second interrupt signal.

The parity check means includes a parity checker 2 that performs a parity check of an instruction for each byte, and a prefetch buffer 1 that stores the detection result of the parity checker 2 for each byte of the instruction. , A decoder 3 that decodes the contents of the prefetch buffer 1 and outputs an instruction length, and an instruction length decoder 4 that outputs a signal indicating a portion that is an instruction based on the output of the decoder 3.
And a AND gate 5 as a first AND gate for taking the logical product of each detection result stored in the prefetch buffer 1 and the output signal of the instruction length decoder 4, and the logical sum of the outputs of these AND gates 5 is taken as the parity. A program including an OR gate 6 for outputting an error signal, wherein the second storage means counts the instruction address of the instruction being executed based on the input addition result and is reset at the time of reloading under the control of the interrupt control means 21. The counter 10, the instruction length signal 7 from the decoder 3 and the output of the program counter 10 are added, the adder 9 which gives the addition result to the program counter 10, and the output of the program counter 10 based on the parity error signal 17 are stored. Error program counter 11 for resetting, and the reset means outputs the program counter 10. And the output of the error program counter 11 are compared with each other and a coincidence result is output when they coincide with each other, and a valid flag 12 which is set at the time of reloading and reset based on the reset signal by the control of the interrupt control means 21. And a AND gate 13 as a second AND gate that outputs a logical product of the output of the valid flag 12 and the coincidence result and outputs the reset signal.

The operation of the electronic computer having such a configuration will be described. FIG. 2 is a diagram showing an input / output truth table of the instruction length decoder of the electronic computer of the present invention. FIG. 3 is a flow chart showing a process in which a parity error has occurred in the electronic computer of the present invention. FIG. 3A shows a process when a parity error occurs, and FIG. 3B shows a process when a double parity error occurs.

In FIG. 1, the present embodiment has a structure having a 4-byte prefetch buffer, and in order to show the gist of the present invention as clearly as possible, parts irrelevant to the present invention are omitted. .

The prefetch buffer 1 has a flag of a parity error detected by the parity checker 2 for each byte. The decoder 3 decodes the contents of the prefetch buffer 1 and outputs the instruction length signal 7 by taking out the instruction length as information. As shown in FIG. 2, the instruction length decoder 4 outputs up to what part of the prefetch buffer 1 the relevant instruction is according to the instruction length. Therefore, the AND gate 5 logically ANDs each of the four flags of the parity error of the prefetch buffer 1 and the four outputs of the instruction length decoder 4, and the result is ORed by the OR gate 6 to obtain the corresponding instruction. Has a parity error, a parity error signal 17 is output. When the parity error signal 17 becomes "1", the sequencer 18 causes the interrupt control means 21 to recognize it and generate an interrupt. At the same time, the error flip-flop 14
It is set by the parity error signal 17 and stores that a parity error has occurred. Further, at the same time, the error program counter 11 inputs the value of the program counter 10.

In general instructions, the program counter 10
Adds the instruction length input by the instruction length signal 7 by the adder 9 and always holds the instruction address of the instruction being executed. The comparator 20 compares the outputs of the program counter 10 and the error program counter 11. And gate 13
Is the error flip-flop 14 when the comparison result of the comparator 20 is the same and the valid flag 12 of the error program counter 11 is "1" or the instruction end signal 19 of the corresponding instruction is "1". To reset. The valid flag 12 is set by the interrupt control means 21 and reset at the same timing as the error flip-flop 14. When the error flip-flop 14 is "1", the AND gate 15 detects that a parity error has occurred, and a double parity error 1
6 is notified to the sequencer 18 via the signal line, and the interrupt control means 21 is provided as an interrupt different from the case of the parity error.
Can be recognized.

Next, an example of control by the interrupt control means 21 of the electronic computer of this embodiment will be described. In FIG. 3A, when a parity error interrupt occurs, the interrupt control means (interrupt handler) 21 reloads the instruction part of the program in which the parity error occurred.

Next, the valid flag of the error program counter 11 is set to "ON", and the program counter 10 is reset to return to the instruction in which the error of the original program occurred. If the instruction does not cause a parity error, execution returns to the state before the parity error occurred. When a new parity error occurs before the instruction in which the parity error of the original program has occurred is normally executed, the program abort is performed as shown in FIG. 3B.

As described above, according to the present embodiment, when a parity error occurs before the re-execution of the instruction in which the parity error occurs is successful, the software is notified as another interrupt and a parity error is generated. When the re-execution of the executed instruction succeeds, the state before the parity error occurs is returned to and the execution is continued.

[0020]

As described above, the present invention has an excellent effect that it can be re-executed when a parity error occurs in instruction fetch.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a computer according to an embodiment of the present invention.

FIG. 2 is a diagram showing an input / output truth table of an instruction length decoder of the electronic computer of the present invention.

FIG. 3 is a flow chart showing processing when a parity error occurs in the computer of the present invention.

[Explanation of symbols]

 1 Prefetch Buffer 2 Parity Checker 3 Decoder 4 Instruction Length Decoder 5, 13, 15 AND Gate 6 OR Gate 7 Instruction Length Signal 9 Adder 10 Program Counter 11 Error Program Counter 12 Valid Flag 14 Error Flip-Flop 16 Tabular Parity Error 17 Parity Error Signal 18 sequencer 19 instruction end signal 20 comparator 21 interrupt control means

Claims (2)

[Claims] 1. An electronic computer provided with a parity check means for outputting a detection signal when a parity error of an input instruction is detected, and an interrupt means for outputting a first interrupt signal based on the detection signal, An interrupt control means for controlling the reloading of the instruction part in which the parity error occurs based on the first interrupt signal; and a reset signal set based on the detection signal or reset based on an instruction end signal One storage means, a second storage means for storing an instruction address when the parity error occurs based on the detection signal, a reload is executed and the contents of the second storage means and the reloaded The reset means for outputting the reset signal when the instruction address of the instruction portion matches and the first memory means are in the set state, A re-detection means for outputting a re-detection signal when a detection signal corresponding to the received instruction is input, wherein the interruption means receives the instruction end signal and the second interruption signal when the re-detection signal is input. An electronic computer, wherein the interrupt control means includes means for performing control to abort the instruction being executed based on the second interrupt signal. 2. The parity check means includes a parity checker for performing a parity check of the instruction on a byte-by-byte basis, and a prefetch buffer for storing the result of the parity checker added on a byte-by-byte basis of the instruction. A decoder that decodes the contents of this prefetch buffer and outputs an instruction length, an instruction length decoder that outputs a signal indicating the portion that is the above instruction based on the output of this decoder, and each detection result stored in the above prefetch buffer and this A second AND means for taking a logical product of the output signal of the instruction length decoder and an OR gate for taking the logical sum of the outputs of the first AND gates and outputting the detection signal; The instruction address of the instruction being executed is counted based on the input addition result and is controlled by the interrupt control means. A program counter that is reset when reloaded, an adder that adds the instruction length from the decoder and the output of the program counter and gives the addition result to the program counter, and an output of the program counter based on the detection signal And an error program counter for storing, and the reset means compares the output of the program counter with the output of the error flip-flop and outputs a coincidence result when they coincide, and the interrupt control means. A valid flag which is set at the time of reloading and reset based on the reset signal under the control of the above, and a second AND gate which logically ANDs the output of the valid flag and the coincidence result and outputs the reset signal. The electronic computer according to Item 1.