JPH0235525A - Instruction fetch control method - Google Patents

Abstract

PURPOSE:To execute instructions with the shortest loss time even in the case of a failure in branch prediction by selecting respective instruction buffers according to the prediction success and failure, and branch success and failure of a branch instruction. CONSTITUTION:This method is provided with instruction address registers IARA- IARC and instruction buffers IWRA-IWRC which hold instructions temporarily. In a normal instruction sequence, the pair of the instruction address register IRA and instruction buffer IWR are used to prefetch and feed instructions. A control part 3 selects the respective instruction buffers IWRA-IWRC according to the prediction success and failure, and branch success and failure of the branch instruction to execute the instructions in the instruction buffer immediately.

Description

[Detailed Description of the Invention] [Summary] Regarding an instruction fetch control method used in an information processing device that performs instruction prefetching prior to instruction execution, the purpose is to reduce loss time due to branch instructions as much as possible. A branch prediction table is provided that stores the instruction address of the branch instruction and a flag indicating its validity in pairs, as well as the branch destination address of the branch instruction, and a branch prediction table is provided that stores the instructions of the currently executed instruction sequence. 1 instruction buffer and a second instruction buffer that stores instructions of an instruction sequence at an address predicted from the branch prediction table. At least two instruction buffers are provided, and an instruction address register for holding the instruction address of the instruction held in each of the instruction buffers is provided corresponding to the instruction buffer. Each of the instruction buffers is selected, the instructions in the instruction buffer are immediately executed, and the instruction sequence of the instruction is continuously fetched.

[Field of Industrial Application] The present invention relates to an instruction fetch control method used in information processing '1AiiW in which instructions are prefetched prior to instruction execution.

In information processing devices that require high-speed operation, instructions are pre-fetched in order to reduce loss time in fetching instructions. Here, instruction prefetching means that 17 memory accesses are made each time an instruction is executed.
Since high-speed operation becomes impossible due to the time required for access, M output, etc., there is a buffer? A memory is provided near the CPU, a plurality of instructions are brought into the buffer in advance, and the instructions are sequentially read out from the buffer memory.

However, instruction prefetching is difficult for branch instructions that change the instruction address. Incidentally, in normal operating systems and user programs, branch instructions appear very frequently, and therefore it is required to reduce the loss time associated with branch instructions as much as possible.

[Prior Art] FIG. 10 is a diagram showing a conventional instruction prefetch operation when executing a branch instruction. First, a condition code (CC) setting instruction is executed, and the CC is determined in the W cycle. Vibration beam shown here.

A, T, B, E, and W form one flow, and the meaning of each machine cycle is as follows.

D: Instruction decoding (interpretation) cycle A Ni-operand address calculation cycle T: Cycle that refers to the TLB and obtains the absolute address B: Buffer cycle (cycle that reads data from the buffer) E: Execution cycle (for example, addition 1 multiplication, etc.) )W: One instruction ends in more than one execution result capture cycle.

Next, a branch instruction is executed, and the branch is determined in the E cycle. After the establishment of the branch is determined in this way, fetching of the branch destination instruction is started, so the loss time is 7 cycles. In the figure, iA is an instruction address calculation cycle;
iT is TLB for instruction fetch (high speed address converter)
The reference cycle +et is an instruction cache memory reference cycle, and instruction execution starts from the next D cycle.

In a normal program, the branch success rate is higher than the failure rate, and branch instruction 1, which has taken a branch twice, has a very high possibility that the branch will be taken again. Therefore, the loss time when a branch is successful can be minimized, which greatly improves performance.Using this property, the execution result of a branch instruction can be predicted,
A method of prefetching instructions has been proposed.

FIGS. 11 to 13 are diagrams showing a method of prefetching a branch destination instruction by prediction. FIG. 11 is a diagram showing the internal structure of a branch prediction table that stores branch instruction addresses and branch destination addresses in pairs, and registers branch instructions that have shown branch success in the past. In FIG. 12, at the stage of instruction prefetching operation, a branch prediction table is retrieved using the branch instruction address, and if that instruction address is registered, the paired branch destination instruction address is read and the instruction prefetching address is read. Set in the register and continue prefetching subsequent instructions.

[Problem to be solved by the invention] When the branch prediction table is drawn, the predicted branch destination instruction can be executed immediately after the branch instruction, so the loss time is O as shown in FIG. . On the other hand, if the prediction ends in failure, such as when the branch is not taken or the branch destination address is changed, there is a problem in that a large loss time of 7 cycles occurs as shown in FIG. 13.

The present invention has been made in view of these problems, and in the instruction prefetch υ1110 in a branch instruction using a branch prediction table, the instruction can be executed with the shortest loss time even in the case of a branch prediction failure. The purpose of this invention is to provide an instruction fetch control method.

[Means for Solving the Problems] FIG. 1 is a flowchart showing the principle of the method of the present invention. The present invention provides a branch prediction table that holds the instruction address of the branch instruction several instructions before the branch instruction, the instruction address of the branch instruction, and a flag indicating its validity in pairs, as well as the branch destination address of the branch instruction. Step 1): A first instruction buffer that stores the instructions of the currently executing instruction sequence? and a second instruction buffer for storing instructions of the instruction sequence at the address destination predicted from the branch prediction table (two instruction buffers are provided (step 2), and the instructions held in each instruction buffer are An instruction address register for holding the instruction address is provided corresponding to the instruction buffer (step 3), and each instruction buffer is selected depending on whether the prediction of the branch instruction is successful, failure 1, branch taken, or not taken. The present invention is characterized in that the instruction is executed immediately and the instruction fetch of the instruction sequence is continued (step 4).

[Operation] A first instruction buffer that stores instructions of the instruction sequence currently being executed, and a second instruction buffer that stores instructions of the instruction sequence at the address destination predicted from the branch prediction table. At least two instruction buffers are provided. This allows us to proceed to the contents of the second instruction buffer in case of successful branch prediction and to the contents of the first instruction buffer in case of branch prediction failure. Execute the instructions in sequence. This makes it possible to reduce the loss time when executing a branch instruction as much as possible, regardless of whether the prediction of the branch instruction is successful, unsuccessful, 0 branches taken, or not taken.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a diagram showing the branch prediction table writing operation, and FIG. 3 is a diagram showing the entry format of the branch prediction table.

In FIG. 2, the CLC instruction is 370-(DATBE
This is an instruction that determines the condition code (CC) to determine whether to branch at a branch (8RA 1 flow).
NC)-1) Branch establishment is determined in the E cycle of the instruction.

PSWIAR is a PSW instruction address register, updated in the last W cycle of the instruction, and points to the instruction address of the next instruction.

At each cycle, IAR points to the instruction address of that instruction, OAR is the operand address register, and in the case of a branch instruction, points to the target instruction address. Here, BRANCH-T
AKEN) signal, PSWIAR is registered as the target fetch start address, E-IAR as the branch instruction address, and E-OAR as the target instruction address in the prediction table. In the case of Figure 2,
The instruction address of the CLC instruction is registered as the target start address (see FIG. 3).

Note that V in FIG. 3 indicates the validity of these instruction addresses (V
ALID).

FIG. 4 is a diagram showing the instruction prefetching operation. When D-FAR and target start instruction address match and the V flag indicating validity is set, the target instruction address is set to TARGET FAR, the branch instruction address is set to BREAR, and D-FAR is set to FCHFAR. and the VALID latch is set. When there is a valid trigger, DARGET rAR
The ffi instruction fetch address is selected, and the 2-bit ■D specifying the instruction buffer to be used is selected and sent.

Next, in the D cycle of the branch instruction, 0-fAR and BR-
IAR is compared, and as a result of decoding the instruction code of the D cycle, if it is found that it is a branch instruction, a control signal ■ is generated according to the comparison result, and the instruction buffer is transferred to the instruction buffer (second buffer), and from the next cycle, the predicted branch destination instruction is executed from the D cycle. On the other hand, in the A cycle of a branch instruction, the operand address generation circuit (
(not shown) is sent as an instruction fetch address, and there is another instruction buffer 10.
is selected and sent.

In the T cycle of the branch instruction, the target [AR and T
-OAR is compared, and a control signal ■ is generated based on the comparison result. In the E cycle of a branch instruction, if the branch is not taken, the instruction buffer is switched to a buffer (first buffer?) that holds the current instruction sequence. In addition, as such an instruction buffer, a third instruction buffer? (By this, if the branch is not taken and it is found that the branch destination address has been changed from the control signal buffer).

In addition, if there is a store in instruction 1jiI and the branch instruction is changed, if the branch destination address is changed by the signal ■, or if the branch is not taken by the signal ■, then the not branch token < N0T-BRANCH-TKN )
FC from GC)-1-V of the entry specified by IARFI
The pit will be reset.

FIG. 5 is a system configuration diagram for implementing the present invention. This figure shows the circuit configuration for instruction fetch and D cycle instruction input. In the figure, IAR is an instruction address register, and there are three, A, B, and C. The rWRs are instruction buffers that temporarily hold instructions, and there are three, A, B, and C, that hold 8-byte instructions. XR,BR,OR
are registers that hold an index register, a base register, and a displacement section respectively designated by the instruction, and the sum of these is calculated in the A cycle of the branch instruction and becomes the instruction address of the branch destination.

In a normal instruction sequence, a - pair of IAR, IWR (eg, 1iflAR-A, IWR-A>) is used to prefetch and inject instructions.

Next, when the prediction table hits and the parid latch of the predicted branch destination instruction fetch is set, the instruction fetch 11
11111 part 1 selects the target JAR and sends the instruction address, and also selects the instruction buffer rW to be used.
2-bit I-FCI-IREQ rD (I
Send a fetch request (rD). The contents of the target IAR are then set to the next EAR, namely FAR-B. Data obtained from the I-FCHLBS (I-fetch local buffer storage) 2 via the EAR (effective address register) in the IS cycle is set in the IWR indicated by I-FCHREQ IQ, that is, the instruction buffer IWR-8.

Here, when the signal ■ in FIG. 4 is detected, the control unit 3 selects and inputs a command from the IWR-8. Then, when it is confirmed that the branch is taken and the prediction of the 9th branch is successful in the E cycle of the branch instruction, the instruction is prefetched from the IAR-B, and thereafter the FAR-B.

The IWR-B continues to prefetch and input instructions.

In addition, in the ∆ cycle of a branch instruction, SR, XR, D
The branch destination instruction address obtained from R's adder (additional ts5>4) is selected and sent. At this time, the I-FCH
REQ ID points to instruction buffer fWR-C, and the address at this time is held in IAR-C.

When the branch is established in the E cycle of the branch instruction and the change of the branch destination address is confirmed by the signal (2), an instruction is input from rWR-C and an instruction is fetched from fAR-C.

Also, if it is confirmed that the branch is not taken, IWR-A, TA
Returning to RA, instructions are input and fetched. In this way, rAR and rWR are used cyclically as A, B, and C in sequence. According to the present invention, when a conditional branch is taken, the branch instruction address is immediately jumped to and the branch instruction is executed, and when the conditional branch is not taken, the instruction is quickly returned to the original instruction buffer and the instruction continues. becomes possible.

FIG. 6 is a time chart when branch prediction is successful. An example of jumping from instruction back yIWR-A to instruction buffer rWR-B by a branch instruction is shown. FIG. 7 is a time chart when prediction fails due to a change in branch destination address. The prediction by the predicted branch destination instruction fails and the instruction buffer F
The branch destination is changed to IWR-C and executed. The loss time in this case is 4 cycles.

FIG. 8 is a time chart when prediction fails due to branch failure. Predicted branch destination instruction 1 Any of the branch destination instructions fails,
The instruction is returned to the original instruction buffer IWR-A and the instruction following the branch instruction is executed, resulting in a loss time of 4 cycles.

As described above, in all cases where prediction fails, three cycles can be shortened compared to the conventional method.

In the above example, the condition setting instruction immediately before the branch instruction is
I have been thinking about CLC instructions that require flow, but 270-, 1
In the case of an instruction that ends at 70-, fetching of the predicted branch destination instruction will be delayed. This is solved by registering the register that shifted and held the PSW-JAR as the target fetch start instruction address. For example, as shown in FIG. 9, the instruction address of the instruction ■ is registered, and when the prediction table is used next time, the instruction fetch can be provided without delay using the conventional IJtll.

[Effects of the Invention] As described above in detail, according to the present invention, a first instruction buffer stores instructions of an instruction sequence currently being executed, and an instruction of an instruction sequence at an address predicted from the branch prediction table. At least two instruction buffers of the second instruction buffer that store? will be established. As a result, if the branch prediction is successful, the contents of the second instruction buffer are proceeded to, and if the branch prediction is unsuccessful, the instructions in the first instruction buffer are sequentially executed. This results in successful branch instruction prediction.

It is possible to provide an instruction fetch control method that can minimize loss time when executing a branch instruction, regardless of whether the branch is taken or not.

[Brief explanation of the drawing]

Figure 1 is a flowchart showing the principle of the method of the present invention, Figure 2 is a diagram showing the branch instruction prediction table write operation, Figure 3 is a diagram showing the entry format of the branch prediction table, and Figure 4 is a diagram showing the instruction prefetch operation. Figure 5 is a system configuration diagram implementing the present invention, Figure 6 is a time chart when branch prediction is successful, Figure 7 is a time chart 1-1 when prediction fails due to branch destination address change, Figure 8 is branch 9 is a diagram showing other operations according to the present invention; FIG. 10 is a diagram illustrating instruction prefetching operation when executing a conventional branch instruction; FIG. 11 is the inside of a branch prediction table. FIG. 12 is a diagram showing a method for prefetching a branch destination instruction by prediction. FIG. 13 is a diagram showing a method for prefetching a branch destination instruction by prediction. In FIG. 5, 1 is an instruction fetch control unit, 2 is an I-FCHLBS, 3 is a presentation control unit, 4 is an adder, IAR is an instruction address register,
BR and OR are registers, and IWR is an instruction buffer. Patent applicant: Fujitsu Limited
Company representative Patent attorney Ijima
Fuji, 1 person, 9th ward D ■ ■ Branch destination instruction T Diagram 1 showing the conventional 0 minute instruction jetting vjo instruction prefetching operation
0 figure

Claims (1)

[Claims] In an information processing device that performs instruction prefetching prior to instruction execution, an instruction address several instructions before a branch instruction, an instruction address of the branch instruction as well as a branch destination address of the branch instruction, and its validity. A branch prediction table is provided that stores the instructions of the currently executed instruction sequence in pairs (step 1), and a first instruction buffer stores the instructions of the currently executed instruction sequence, and the instruction sequence of the address destination predicted from the branch prediction table. At least two instruction buffers are provided as a second instruction buffer for storing instructions (Step 2), and an instruction address register for holding the instruction address of the instruction held in each instruction buffer is provided corresponding to the instruction buffer (Step 3). , select each instruction buffer according to whether the branch instruction is predicted successfully or unsuccessfully, whether the branch is taken or not, and immediately executes the instructions in the instruction buffer, and causes the instruction fetch of the instruction sequence to continue (step 4) An instruction fetch control method characterized by the following.