JPH04205425A - Data processor and its data processing method - Google Patents

Abstract

PURPOSE:To reduce the number of instructions and the number of memories by setting up a waiting time with a timer when an instruction is decoded as a wait instruction and generating signals from the generation of the waiting instruction until a specified required time lapse. CONSTITUTION:An instruction from a processor is read out to an instruction register 1 and decided by an instruction decoding part 2 to execute respective processing, but when a waiting instruction is set up in the register 1, a required waiting time is set up in an operand part of the instruction. Thereby when the instruction is decoded as the waiting instruction by the decoding part 2, a signal 3 is driven and the waiting time is set up in a timer 5. The timer 5 is counted down by a reference clock and the count-down operation is executed until a set value becomes '0'. Consequently the number of instructions and the number of memories can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to instructions for a data processing device, and particularly relates to a WAIT instruction for securing a certain period of time.

[Prior Art] Conventionally, in a data processing device, there is a wait instruction that does not expect any operation until a certain event occurs.

As shown in the instruction sequence diagram in Figure 3, A, B, C,
D is a general instruction, and the wait instruction has been issued five times. These wait instructions are mainly used to wait for processing performed by other instructions and to secure a certain amount of time.

In order to secure a certain amount of time based on the execution time of these wait instructions, it was necessary to issue wait instructions for that amount of time.

Therefore, the number of wait instructions required is the quotient (integer) of the required wait time divided by the instruction execution time of the wait instructions.

[Problems to be Solved by the Invention] However, when the number of instructions and memory increases, and the clock frequency of the processing device is changed,
As a result, the above-mentioned wait instruction execution time changes, so the number of wait instructions also has to be changed, resulting in a problem that the program must be changed.

Therefore, it is an object of the present invention to provide a data processing device that reduces the number of instructions, reduces the amount of memory, and eliminates the need to change the program even if the clock frequency of the data processing device changes.

[Means for Solving the Problems] According to the present invention, there is provided a clock generator that generates a clock for a processing device, an instruction setting unit that sets a wait instruction that can directly specify a desired wait time to wait, and a clock generator that generates a clock for a processing device. a timer that, when decoded as a command, sets the wait time and generates a signal until a specified desired time elapses from the time when the wait command is issued; and an output of the clock generator based on the output signal of the timer. A data processing device characterized in that it includes a control circuit for controlling the data processing device is obtained.

Further, according to the present invention, there is obtained a data processing device in which the control circuit includes an instruction register that reads instructions of the processing device, and an instruction decoder that decodes the instructions in the instruction register.

Further, according to the present invention, a clock for a processing device is generated by a clock generator, a wait instruction that can directly specify a desired wait time is used to wait, and when the wait instruction is decoded, a timer is used to generate a clock for the processing device. A data processing method for a data processing device, comprising: setting a time and generating a signal until a specified desired time elapses from when a wait command is issued; and controlling the output of the clock generator by the output signal of the timer. is obtained.

[Embodiment] FIG. 1 shows a data processing device according to an embodiment of the present invention.

Referring to FIG. 1, A, B, C, and D are general instructions, and the wait instruction has been issued five times. Assuming that the instruction execution time of this wait instruction itself is 4 clocks in terms of the number of clocks of the processing device, in this case, a time of 5.times.4-20 clocks will elapse between the B instruction and the C instruction.

Now, one clock of the data processing device is 20 nanoseconds (ns).
Then, it is 20X20-400ns, and there are 17-20 clocks (320-400ns) between the B and C instructions.
If s) is required, the instruction sequence will be like this.

FIG. 2 shows an embodiment of the invention.

The data processing device includes a clock generator 8 that generates a clock for the processing device as a control means, an instruction setting device that sets a wait command that can directly specify a desired wait time, and a timer 5. . When the timer 5 is decoded as a wait command, it sets a wait time and generates a signal until a specified desired time elapses from the time the wait command is issued.

First, the instruction of the processing device is read into the instruction register 1, decoded by the instruction decoding unit 2, and executed for each process. However, when a wait instruction is set in the instruction register 1, the operand part of this instruction contains the required information. Wait time is set.

Therefore, when the instruction decoder 2 decodes the instruction as a wait instruction, the signal 3 is driven and the wait time 4 is set in the timer 5. This timer 5 is counted down by the reference clock 6 and is executed until the set value reaches "0". Further, the output signal 7 of the timer 5 is driven to "1" when the counter value is rOJ, and is driven to "1" when a value other than "0" is set.

Furthermore, if the reference block is set to, for example, 10 ns and the reference block is set to wait 400 ns, this timer is set to 40 ns.
During the countdown (400ns
middle) The drive signal 7 is rO.

Therefore, the wait time set by the wait command causes the signal 7 to become "0", and the clock 9 from the clock generator 8 of the processing device is not propagated into the processing device by the gate circuit 10. Furthermore, when the wait time has elapsed, the signal 7 becomes "1" and the gate circuit 10 sends the clock 9 from the clock generator 8 to another processing section.

[Effects of the Invention] As described above in the embodiments, according to the data processing device of the present invention, the number of instructions can be reduced by directly specifying the wait time in the operand section using one wait instruction, and furthermore, the processing device can be This has the effect that even if the clock frequency changes, there is no need to change the program.

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[Brief explanation of the drawing]

FIG. 1 is an instruction sequence diagram in a data processing device showing an embodiment of the present invention, FIG. 2 is an instruction format and block diagram in a data processing device showing an embodiment of the present invention, and FIG. 3 is a conventional data processing diagram. FIG. 3 is an instruction sequence diagram in the device. 1: Instruction register, 2: Instruction decoder, 5: Timer, 6:
Reference clock, 8; clock generator, 10; gate circuit.

Claims (1)

[Claims] 1. A clock generator that generates a clock for a processing device;
an instruction setting means for setting a wait instruction that can directly specify a desired wait time to be waited; and an instruction set means for setting the wait time when the wait instruction is decoded, and a desired time specified from the time of issuance of the wait instruction. A data processing device comprising: a timer that generates a signal until a clock elapses; and a control circuit that controls the output of the clock generator using the output signal of the timer. 2. The data processing device according to claim 1, wherein the control circuit includes an instruction register that reads instructions of the processing device, and an instruction decoder that decodes the instructions in the instruction register. 3. Generating a clock for the processing device using a clock generator; Waiting using a wait instruction that can directly specify a desired wait time; and when the wait instruction is decoded, setting the wait time using a timer and executing the wait instruction. A data processing method for a data processing device, comprising: generating a signal until a specified desired time elapses from the time of issuance; and controlling the output of the clock generator by the output signal of the timer.