JPH0559449B2 - - Google Patents

Description

Detailed Description of the Invention [Summary] In a microprogram control system configured to prevent a microprocessor from running out of control by setting a stop command code to 0, a reset signal arrives when the value of an operation register is 0. After that, the microprogram is executed in synchronization with the clock, and operation after runaway or stoppage is possible without requiring a signal for execution from a higher-order circuit device.

[Industrial application field]

The present invention relates to a control system for preventing a microprocessor from running out of control.More specifically, the present invention relates to a control system for preventing a microprocessor from running out of control. In a microprogram control method that stops runaway by clearing the free space to zero,
A flip-flop is used to set the contents of the operation register to a predetermined value at the time of reset, allowing operation after stopping without requiring an instruction code or signal from a higher-order circuit device.

[Conventional technology]

The conventional microprogram control method uses control storage address register 1, control storage 2, and operation register 3, as shown in FIG. The control storage 2 generates an instruction to execute the instruction, and supplies the code for execution to the decoder 4 via the operation register 3. To prevent the microprogram from running out of control, the free space in control storage 2 is set to 0, and the stop command code is set to 0.
is set to . If a jump is made to this area during a runaway, the contents of all 0s are read from control storage 2 to operation register 3. Therefore, the code section of register 3 has the same contents as the stop instruction code, so the microprogram is not executed. For this reason, a command or signal is given from a higher order or external circuit device so that the command is executed from a predetermined address of the control storage 2, for example, address 0. However, even in a microprocessor configured to prevent runaway, it is desirable to be able to start its operation simply by supplying a signal from an internal circuit at the time of reset.

[Problem that the invention seeks to solve]

In this conventional method, if the circuit jumps to a free area in control storage 2 during a runaway, the circuit automatically stops, but a reset signal is supplied to control storage address register 1 and operation register 3. too,
A microprogram with the same content as the stop instruction code is not executed. For this reason, it has been necessary to resume execution of the suspended microprogram by applying a command or signal from a higher-level or external circuit device.

The present invention was created in view of these points, and an object of the present invention is to provide a microprogram control system that can be executed from an instruction at a predetermined address in the control storage 2 by simply supplying a reset signal.

[Means for solving problems]

FIG. 1 is an explanatory diagram of the principle of the present invention, and shows how the system starts from a stopped state at the time of runaway, including step S100 for checking the contents of the operation register, and step S110 for determining the arrival of a reset signal. , step S120 of setting the flip-flop and setting the control storage address register to a predetermined address upon arrival of the reset signal, AND condition of the set output of the flip-flop 5 and the decoder output of the operation register at the time of reset, and the clock. Step S130 to obtain the
A step to execute a microinstruction from the control storage microinstruction specified by the control storage address and register value in response to the clock output in an AND condition.
Consists of S140. Note that these determinations are achieved using a general AND/OR gate.

[Effect]

In step S100, the contents of the operation register are checked, and when a reset signal arrives in step S110, the process is started.
At S120, a flip-flop (not shown) is set and the stop release bit signal becomes 1. Also, the contents of the operation register set to the stop command due to runaway are output. The control storage address register is set to a predetermined address by a reset signal.

The set output of the flip-flop 5 and the decode output of the operation register at the time of reset,
When the AND condition with the clock signal is satisfied, the clock signal is output.

Control using this output clock signal.
The value of the storage address register is supplied to the control storage, and the microinstruction is executed from the microinstruction in the control storage specified by the value.

decoding the contents of the operation register set to the aforementioned stop command, setting the control storage address register to a predetermined address, outputting the clock with the decode output and stop release bit signal, and Control storage address register value in response
By supplying the storage, the stop instruction set in the operation register is equivalently
It will be executed as a NOP instruction, and it can be executed from a predetermined microinstruction in control storage, so it is possible to execute from a predetermined microinstruction in control storage just by supplying a reset signal. becomes.

〔Example〕

FIG. 2 shows an embodiment of the present invention in which control storage address register 1, control storage 2, and operation register 3 are used to create an address corresponding to the address set in control storage address register 1. The control storage 2 generates an instruction to execute the instruction, and supplies the code for execution to the decoder 4 via the operation register 3. Also, after the control storage address register 1 has generated one address, it is incremented to generate the next address. To prevent the microprogram from running out of control, the free space in control storage 2 is set to 0.
, and the stop command code is set to 0. If the circuit jumps to this area during a runaway, the contents read into the operation register 3 are all 0s, so all circuits are automatically stopped. The circuit shown in FIG. 2 further includes:
Flip-flop 5 and AND gates 6, 8 and OR for generating stop/release bits
Gate 7 is shown. Flip-flop 5 is set to generate a stop release bit when the system reset RESET is applied.
AND gate 8 generates an output when the contents of operation register 3 are all "0" and a stop release bit is generated. This output is generated because all "0"s in the operation register 3 are decoded by the decoder 4, and an OP signal of "1" is supplied to the AND gate 8.
OR gate 7 generates an output depending on the output of AND gate 8 and other input conditions. and,
The AND gate 6 supplies the clock after the output of the OR gate 7 to the control storage address register 1 to execute the microprogram. That is, prior to this supply, the system reset signal RESET is supplied to the control storage address register 1, and its contents have been reset to an all-0 address.
The all-0 address is supplied to the control storage 2, and the microinstruction stored at the address in the control storage 2 specified by the address is stored in the operation register 3.
The decoder 4 decodes the microinstruction and starts executing the microinstruction.

As is clear from the above, the stop instruction set in control storage address register 3 due to a runaway microprogram is equivalently executed as a NOP microinstruction, and the 0 in control storage 2 is executed. Causes microinstruction resumption from the microinstruction stored at address. That is, the contents of the operation register 3, which was issued as a stop command due to a runaway microprogram, are decoded by the decoder 4 and the OP is executed.
In addition to outputting the signal, a stop release bit signal is generated from the flip-flop 5 in response to the reset signal, and the clock gated in response to the stop release bit signal is set to all 0s by the reset signal. The address (0 address) of control storage address register 1 is set to control storage 2.
This would equivalently execute the stop instruction as a NOP microinstruction, and also result in a jump to the 0 address of control storage 2.

The flip-flop 5 is reset by executing the microinstruction read from the 0 address of the control storage 2.

In the above embodiment, an example was explained in which the stop command code is set to 0 and the free area of the control storage 2 is cleared to 0, but other bit patterns may be used, for example, all 1s.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a microprogram control method that can be executed from an instruction at a predetermined address in the control storage simply by supplying a reset signal, which is practical. extremely useful.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the microprogram control method of the present invention, and FIG. 2 is a block circuit diagram for implementing the microprogram control method of the present invention.
FIG. 3 is a block circuit diagram of a conventional example. In Figure 2, 1 is a control storage address register, 2 is a control storage, 3 is an operation register, 4 is a decoder, 5 is a flip-flop, and 6 and 8 are
AND gate, 7 is an OR gate.

Claims (1)

[Scope of Claims] 1. Information equivalent to the instruction code of the stop microinstruction is stored in the free area in the control storage 2, which has a microinstruction storage area for storing microinstructions and a free area, and A microprogram control for a microprocessor that stops the execution of a microinstruction when a free area is accessed by decoding the microinstruction set in the operation register 3 at the time of a runaway. In the method, a flip-flop 5 is set by a reset signal of a microprocessor and outputs a stop-release bit signal, and is reset by execution of a microprogram; a stop-release bit signal from the flip-flop 5 at the time of reset; and clock gate circuits 8, 7, and 6 that gate clock signals in response to the decoded output of the decoder 4 that decodes the contents of the operation register 3 at the time of reset, and clock gate circuits 8, 7, and 6 that gate the clock signal in response to the reset signal. and a control storage address register 1 which is controlled by the clock gate circuits 8, 7, and 6, in response to the clock signals output from the clock gate circuits 8, 7, and 6.
A microprogram control system characterized by supplying a predetermined address of a storage address register 1 to the control storage 2 and restarting execution of a microinstruction from a read microinstruction.