JP2532072Y2 - Pattern generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] This invention relates to a semiconductor test apparatus having a pattern generation unit for generating an applied pattern or an expected value pattern and a sequence control unit for controlling the pattern generation sequence. Regarding the generator.

"Prior Art" The operation principle of this type of pattern generator is basically the same as that of a general microprocessor, and a user writes a program in a memory in a machine language in advance. In general, the machine language of the pattern generator is composed of an operation code portion representing a jump, a subroutine call, and the like, and the pattern itself. For example, it is as follows.

The sequence control unit reads this program, executes a jump subroutine call, etc. according to the operation code, outputs a memory address to be executed next, and executes a pattern generation algorithm. And outputs the pattern stored at that address.

Here, the maximum operating frequency of the pattern generator is determined by the maximum operating frequency of the sequence control unit. The maximum operating frequency of the sequence controller is the memory access time,
It is determined by the operation code decoding time and the like. On the other hand, since the pattern generation unit only reads the memory according to the memory address from the sequence control unit, it can be operated at a higher speed than the sequence control unit that performs the decoding operation. Utilizing this, there is a method of operating the pattern generation unit two or more times while the sequence control unit operates once. The machine language program in this case is as follows, for example.

If this method is used, a higher-speed pattern can be generated even with a memory and a decoding circuit having the same access time as the pattern generator described above.

As described above, the operation mode in which the sequence control unit is set to the hold state and only the pattern generation unit operates is conventionally performed as follows. That is, as shown in FIG. 3, the pattern generation sequence of the pipeline-type pattern generation unit 12 is controlled by the pipeline-type sequence control unit 11, and the clock generation unit 13 passes through the gate 15 of the clock control unit 14. The clock A is supplied to the sequence control unit 11, and the sequence control unit 11 operates by the clock A. The clock B from the clock generator 13 is supplied to the pattern generation unit 12, and the pattern generation unit 12 operates. When data is set in the counter 16 of the clock control unit 14, and digital data indicating a numerical value 4 in the example of the program is set, the gate 15 is closed by the output of the counter 16, and the supply of the clock to the sequence control unit 11 is stopped. The sequence control unit 11 enters the hold state. The counter 16 counts down the clock of the clock generator 13, and when a carry output is output, the gate 15 is opened, and the clock is supplied again to the sequence controller 11 and the data is supplied to the counter 16 again. Repeated.
That is, in the above example, one clock is supplied to the sequence controller 11 every four clocks of the clock generator 13. While the supply of the clock to the sequence control unit 11 is stopped, the sequence control unit 11 stops operating and enters the hold state.

[Problem to be Solved by the Invention] As shown in FIG. 3, in the conventional pattern generator, clocks A and B having different frequencies (the frequency of the clock A is 1/4 of the clock B in the above example) are mixed. Therefore, mounting arrangement becomes difficult. Further, in order to perform a higher-speed operation in the pattern generator, a circuit configuration of a pipeline system is employed similarly to a microprocessor or the like. However, if the number of pipeline stages of the sequence control unit 11 is increased, the load of a clock increases accordingly. . In other words, the clock is distributed to each stage of the pipeline processing.However, in order to control the clocks with the same phase, the clocks are distributed to each stage by connecting a plurality of buffers in a tree shape, and each clock is distributed from the clock input stage. The number of buffers until the clock reaches the stage is equalized. The circuit scale of the tree-shaped clock distribution circuit increases as the number of pipeline stages increases. The period during which the sequence control unit 11 is in the hold state is 2
If the frequency is different, the frequency of the clock A also becomes two types, and the tree-shaped clock distribution circuit may need to be separately formed if the frequency is different. The circuit scale becomes significantly large.

According to the present invention, a hold signal is supplied to an enable terminal of a decoder in a sequence control unit, and while the hold signal is supplied, a sequence control command output from the decoder is output from the sequence control unit in the sequence control unit. The counting operation of the program counter is stopped.

"Embodiment" FIG. 1 shows an embodiment of the present invention, and portions corresponding to FIG. 3 are denoted by the same reference numerals. In the present invention, the clock A from the clock generator 13 is supplied directly to the sequence controller 11, and the hold signal from the counter 16 is supplied to the sequence controller 11. The hold signal is generated after data is set in the counter 16 until a carry output occurs.

In the sequence control section 11, a clock A is supplied to a program counter 21 via a gate 24 as shown in FIG. 2, and the sequence of pattern generation is controlled by the program counter 21. Also program counter
The memory 22 is accessed by the output of 21, and an instruction for determining the next output of the program counter 21 is coded and stored in the memory 22. The output of the memory 22 is the decoder 23
And the instruction is fetched. The gate 24 is output by the output of the sequence control instruction decoded by the decoder 23.
Is controlled to open and close.

The hold signal is input to the enable terminal of the decoder 23, the decoder 23 is disabled when the hold signal is input, and has the same output as when the hold instruction is decoded, that is, the sequence control instruction output becomes low level, The gate 24 is closed, the supply of the clock A to the program counter 21 is stopped, and the program counter 21 stops counting. Therefore, during the hold signal, the sequence control unit 11 stops operating and enters the hold state. Become.

"Effects of the invention" As described above, according to the invention, the sequence controller
Since the clock A supplied to the clock 11 and the clock B supplied to the pattern generator 12 have the same frequency, the mounting arrangement is easy. Since the hold signal is supplied to the decoder 23 and the clock supplied to the program counter 21 is controlled by the output of the sequence control instruction, a circuit for setting the hold state even when the number of pipeline stages of the sequence control unit 11 increases. There is no fear that the scale will increase.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a pattern generator according to the present invention, and FIG.
FIG. 3 is a block diagram showing a conventional pattern generator.

Claims (1)

(57) [Scope of request for utility model registration] A clock is counted by a program counter in a sequence control unit, a program memory is read using the count value as an address, the read instruction is decoded by a decoder, and the decoded sequence control instruction output is output by the decoded sequence control instruction output. The supply of the clock to the program counter is controlled, and the count value of the program counter is supplied to the pattern generation unit to control the sequence of pattern generation, and the clock is used to operate the pattern generation unit to generate a hold signal. The sequence control unit is set to a hold state by a hold signal from the means,
In a pattern generator having a mode in which only the pattern generating section operates, an output terminal of the hold signal generating means is connected to an enable terminal of the decoder of the sequence control section, and the hold signal is supplied to the enable terminal. And the decoder becomes inactive, and the sequence control command output stops the counting operation of the program counter.