JPH0317768A - Wait control system - Google Patents

Abstract

PURPOSE:To cope with a high speed processor in a system containing an input/ output device requiring an access cycle time larger than the fixed value by generating a wait signal having the waiting time necessary for the access cycle time. CONSTITUTION:A 15-bit address is connected to a decoder 1, an inverter 2, the AND 3 and 4, and the OR 5 and 6 as shown in a diagram. At the same time, the D type FF 7 - FF 10 are cascaded and a reference clock is inputted to the clock input with a command inputted to the reset input respectively. In such a constitution, the wait signal time width is controlled according to an address signal 15 kept at 1 or 0. That is, the AND 3 is turned on with the signal 15 kept at 1 and the output of the FF 9 is led out via the OR 5. While the AND 4 is turned on with the signal 15 kept at 0 and the output of the FF 10 is led out via the OR 5. As a result, the wait signal time width can be increased by an extent equal to a single cycle of the reference clock and the width of a command signal is kept constant even though the reference signal is changed to 75ns from 100ns.

Description

Detailed Description of the Invention Technical Field The present invention relates to a wait control method, and in particular, in an information processing system having an input/output device that requires an access cycle time of a certain value or more, the present invention relates to a wait control method, in particular, in an information processing system having an input/output device that requires an access cycle time of a certain value or more. This invention relates to a weight control method that generates a signal.

Prior Art In this type of conventional wait control method, a reference clock of the processor is set at the initial design stage of the system, and this clock is used to generate a wait signal having a reference wait time. The wait time is constant.

Therefore, when attempting to use a faster processor in an information processing system that includes an input/output device (1/0) that requires an access cycle time of a certain value or more, a problem of program compatibility arises.

That is, a timing chart of the generation of the wait signal is shown in FIG. 2. If the basic clock width is 100 ns and the command width is 300 ns as shown in (A), the wait signal will be as shown in the figure. ing.

Here, it is assumed that a faster processor is used and the basic clock width becomes 75 ns as shown in (B), making it possible to operate with a command width of 225 ns.

The wait signal at this time is uniquely set to terminate at the third reference clock as in the case (A) above, so the command width at high speed can be obtained. ing.

In this situation, although the system has become faster and has higher performance, the program that measures time based on the amount of software operations has until now been 300 ns x n times because the width of one command changes. The time is 225ns
It takes X n times, and a difference occurs between the two, making the software unusable.

Purpose of the Invention Therefore, the present invention has been made to solve the drawbacks of the conventional ones.The purpose of the present invention is to control the time width of the wait signal in a variable manner so that the command width can be adjusted to the performance of the system. It is an object of the present invention to provide a weight control method that does not change accordingly.

Aspects of the Invention According to the present invention, in an information processing system having an input/output device requiring an access cycle time of a certain value or more, there is provided a wait signal that generates a wait signal having a waiting time necessary for the access cycle time. A wait control method is obtained, which is characterized in that the generation period of the wait signal is switched in response to a switching instruction for switching and controlling the waiting time.

Example Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit block diagram of an embodiment of the present invention. For example, the output of the decoder 1 that decodes a 15-bit address is directly used as the output of the AND gate 4, and the inverted signal of the output by the inverter 2 is used as the output of the AND gate 3. Then, the output of both AND gates 3 and 4 is converted to OR gate 5.
Through another or gate 6 single power. A command signal is supplied to the other input of this OR gate 6, and the output of this OR gate 6 becomes a wait signal.

On the other hand, D-type flip-flops (FF) 7 to 10 are connected in cascade with each other, and logic 1 is applied to the data input of the first stage FF. Then, the Q output of the third stage FF9 becomes the external power of the AND gate 3, and the fourth stage FFIO
The Q output of is the other input to AND gate 4.

A reference clock is applied to the clock input of these FFs, and a command signal is manually input to the reset input.

In this configuration, the wait signal time width is switched and controlled depending on whether the address signal 15 is logic 1 or logic 0. When the address signal 15 is logic O, the output of the decoder 1 becomes logic 0, so the AND gate 3 is turned on and the Q output of the third stage FF 9 is derived via the OR gate. Therefore, the timing waveform at this time is equivalent to that shown in FIG. 2(A).

On the other hand, when the address signal 15 becomes a logic 1, the output of the decoder 1 also becomes a logic 1, and therefore the AND gate 4
turns on. As a result, the Q output of the fourth stage FFIO is derived via the OR gate 5. The timing waveform at this time is as shown in FIG. 2(C).

As can be seen from the above, even if the processor becomes faster and the reference clock changes from 75 ns to 75 ns, the width of the wait signal can be increased by one period of the reference clock, so the terminal of this wait signal The width of the command signal that terminates in response to the timing is set to 800ns.
It becomes possible to maintain the value at a constant value. Therefore, the problem of software compatibility can be solved.

The above embodiment shows a circuit in which four stages of FFs are connected in cascade, but the number of stages is appropriately selected in response to changes in the width of the reference clock, and the number of stages of FFs to be output is selected in accordance with the decoded output. It should be configured as follows.

Effects of the Invention According to the present invention, since the command width is maintained constant by changing the width of the wait signal appropriately according to the reference clock period, the program can be adapted to the performance of the processor. There is.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is an operation timing waveform diagram showing the operation of the embodiment of the present invention in comparison with the prior art. Explanation of symbols of main parts 1...Decoders 7 to 10...FF

Claims (1)

[Claims] (1) In an information processing system having an input/output device that requires an access cycle time of a certain value or more, a wait control method that generates a wait signal having a waiting time necessary for the access cycle time,
A wait control method characterized in that the generation period of the wait signal is switched in response to a switching instruction for switching and controlling the waiting time.