JP2003029965A - Microprocessor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a microprocessor capable of setting the number of the waits of operation time to a part of an instruction code. SOLUTION: The number of the waits corresponding to instruction performance required time is freely settable to the specified bit of the instruction code. The setting of the wait can be stopped by changing a specified bit value in a low-speed clock operation to the instruction to which the wait is set in a high-speed clock operation and the wait can be set to the instruction for which the need of wait setting is recognized after a product is made. Respective circuits perform the instruction by a control signal outputted by an instruction decoder 5 by decoding the instruction code stored in an instruction register 4. By a wait signal outputted by a wait counter 7 by the wait number setting of the specified bit of the instruction code, the instruction register 4 holds the storage of the next instruction code and a program counter 9 stops the output of the next address signal. The respective circuits inside the microprocessor 1A secure the required processing time corresponding to the number of the waits and the highly accurate and correct performance of the present instruction is possible.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, and more particularly to a microprocessor having a function of executing a wait process most suitable for an instruction to be executed.

[0002]

2. Description of the Related Art A conventional microprocessor for controlling the execution of an operation related to an instruction has a structure shown in FIG. 4, and a program executed by the microprocessor 1 is stored in the microprocessor 1. A program memory 2 is connected to the microprocessor 1,
An instruction register 4 for storing an instruction code Cis input from the program memory 2 is provided. Then, in the microprocessor 1, the instruction register 4
An instruction decoder 5 for decoding and decoding the instruction code Cis stored in the instruction register 4 and outputting a control signal Fc is connected to the instruction decoder 5. The instruction decoder 5 includes circuits in the microprocessor 1, a program counter 9, and an instruction register. 4 is connected. Here, the program counter 9 has a function of supplying to the program memory 2 an address signal Fa designating an address in which an instruction to be executed next is stored.

A wait signal Fw is inserted in the control signal Fc output from the instruction decoder 5 according to the instruction to be executed, if necessary.
The insertion condition of w is set in advance according to the type of operation related to the instruction, and for example, in the addition instruction, the wait signal Fw is used.
Has been inserted, and the wait signal is not inserted in the logical product instruction.

In the conventional microprocessor 1 having such a configuration, the program counter 9 inputs the address signal Fa for designating the address in which the instruction to be executed next is stored, to the program memory 2. The instruction stored in the address designated by the address signal Fa from the program counter 9 is read, and the instruction code Cis corresponding to the instruction is output to the microprocessor 1 and stored in the instruction register 4.

Next, the instruction code Cis supplied from the instruction register 4 is decoded and decoded by the instruction decoder 5, and the instruction decoder 5 controls the instruction code Cis corresponding to the instruction code Cis and inserting the wait signal Fw as necessary. A signal Fc is output, and this control signal Fc is input to the program counter 9 and each circuit in the microprocessor 1. When the wait signal Fw is inserted in the control signal Fc, the wait signal Fw is input to the program counter 9, the instruction register 4, and each circuit in the microprocessor 1.

In the conventional microprocessor 1, when the control signal Fc does not include the wait signal Fw, the program counter 9 advances the currently output address by 1 in order to execute the next instruction. The address signal Fa designating the address of the specified value or the address signal Fa designating the address related to the command of the control signal Fc from the instruction decoder 5 is supplied to the program memory 2 and designated by the program memory 2. The next instruction code Cis corresponding to the address is the microprocessor 1
To the next instruction execution. on the other hand,
When the control signal Fc includes the wait signal Fw, the program counter 9 stops the output of the next address signal Fa and continues the output of the current address signal Fa by the input wait signal Fw, and the instruction register 4 Then
The storage of the next instruction code Cis is suspended, and the operation of the current instruction is continued in each circuit of the microprocessor 1.

[0007]

As described above, in the conventional microprocessor 1, for example, the wait signal Fw is inserted in the add instruction and the wait signal Fw is not inserted in the AND instruction. Since the insertion condition is set in advance corresponding to the type of operation related to the instruction, in order to allow an instruction that takes a long time to perform an operation with high precision and accuracy when operating at a high speed clock, Wait signal F when decoding instruction code Cis
If the configuration is such that w is included, there is a problem in that the wait signal cannot be deleted even when operating with a low-speed clock that does not require the insertion of the wait signal Fw, and an unnecessary wait operation is executed. On the other hand, on the other hand, even after it is determined that it takes time to execute a specific instruction after the microprocessor 1 is commercialized, there is a problem that a wait signal cannot be separately inserted when the instruction is executed.

The present invention has been made in view of the current state of operation of the conventional microprocessor as described above,
It is an object of the present invention to provide a microprocessor in which an operation weight can be arbitrarily set by utilizing a part of an instruction code stored in a program memory.

[0009]

In order to achieve the above object, the invention according to claim 1 executes an instruction by a control signal output from an instruction decoder which decodes an instruction code, and a weight corresponding to the instruction. By inserting a wait cycle based on a number, in a microprocessor equipped with a function to secure the time required for instruction execution, a specific bit of the instruction code is set as the number of waits for instruction execution and set in the wait counter. The present invention is characterized by comprising wait number setting means and wait means for giving a weight to instruction execution based on the number of weights set in the wait counter by the weight number setting means.

According to such means, the instruction is executed by the control signal output from the instruction decoder for decoding the instruction code, but the wait number setting means causes the specific bit of the instruction code to be the number of waits when the instruction is executed. Is set to the wait counter, the wait means inserts a wait cycle based on the number of waits set in the wait counter by the wait number setting means to wait for instruction execution.
The optimum number of weights corresponding to the type of operation and clock speed related to the instruction to be executed is set at any time independently of the instruction, and the optimum number of waits is executed depending on the type of operation related to the instruction and the clock speed. The instruction is executed with high precision, accuracy and efficiency by arbitrarily securing the optimum time.

Similarly, to achieve the above object, the invention according to claim 2 executes an instruction by a control signal output from an instruction decoder for decoding an instruction code, and waits based on the number of weights corresponding to the instruction. In a microprocessor having a function of securing a time required for instruction execution by inserting a cycle, a wait type setting means for setting a specific bit of an instruction code as a wait type at the time of instruction execution, and the wait type. A conversion output means for converting and outputting the type of weight set by the setting means into a corresponding weight number, and a weight for setting the number of weights converted and output from the conversion output means in the weight counter as the number of weights at the time of executing the instruction. Number setting means, and a weight set in the weight counter by the weight number setting means Based on, it is characterized in that it has a weight means for applying a weight to instruction execution.

According to such means, the instruction is executed by the control signal output from the instruction decoder which decodes the instruction code, but the wait type setting means causes the specific bit of the instruction code to indicate the weight at the time of executing the instruction. When the weight type set by the conversion output means is converted and output by the conversion output means to the corresponding weight number, the number of weights converted and output from the conversion output means by the weight number setting means Is set in the wait counter as the number of waits at the time of instruction execution, and the wait means inserts a wait cycle based on the number of waits set in the wait counter by the number of waits setting means to wait for instruction execution. For this reason, the conversion of the weight type into the number of weights by the conversion output means is optimal in accordance with the type of operation and clock speed related to the executed instruction,
In addition, a wide range of wait numbers for specific bits of the instruction code is set at any time independently of the conversion instruction, and a wide range of optimum time for instruction execution is set according to the operation type and clock speed of the instruction. Are arbitrarily secured, and the instruction is executed with higher precision, accuracy and efficiency.

Similarly, to achieve the above object, the invention according to claim 3 executes an instruction by a control signal output from an instruction decoder for decoding an instruction code, and waits based on the number of weights corresponding to the instruction. In a microprocessor having a function of securing a time required for instruction execution by inserting a cycle, a wait type setting means for setting a specific bit of an instruction code as a wait type at the time of instruction execution, and the wait type. Conversion output means for converting and outputting the corresponding number of weights based on the type of weight set by the setting means and the conversion coefficient detected by the instruction decoder from the instruction code, and converted and output from the conversion output means. A wait number setting means for setting the wait number in a wait counter as a wait number when executing an instruction; Based on the number of waits by Eight number setting means is set in the wait counter, it is characterized in that it has a weight means for applying a weight to instruction execution.

According to such means, the instruction is executed by the control signal output from the instruction decoder which decodes the instruction code, but the wait type setting means causes the specific bit of the instruction code to indicate the weight at the time of executing the instruction. Based on the weight type set by the weight type setting means by the conversion output means and the conversion coefficient detected by the instruction decoder from the instruction code, the corresponding weight number is converted and output to set the number of weights. The number of weights converted and output from the conversion output means by the means is set in the weight counter as the number of weights at the time of executing the instruction, and the weight is set by the weight means based on the number of weights set in the weight counter by the weight number setting means. Cycles are inserted to give weight to instruction execution Therefore, the number of weights is converted and output by the conversion output means based on the type of weight set in the specific bit of the instruction code by the weight type setting means and the conversion coefficient detected from the instruction code by the instruction decoder, and then executed. The optimum number of weights corresponding to the type of operation and clock speed of the instruction to be executed, and a wide range of fine weights for specific bits of the instruction code is set at any time independently of the conversion instruction. According to the type of operation and the clock speed, the wide range of time optimal for instruction execution is arbitrarily secured, and the instruction is executed more finely, precisely, accurately and efficiently.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] A first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing the configuration of this embodiment.

In the present embodiment, as shown in FIG. 1, the microprocessor 1A is different from the microprocessor 1A.
A program memory 2 in which a program executed by A is stored is connected, and an instruction register 4 for storing an instruction code Cis input from the program memory 2 is provided in the microprocessor 1A. In the above form, a wait cycle can be set in a specific bit of the instruction code Cis to insert a wait cycle when the instruction is executed and to secure a time required for the instruction execution. In the microprocessor 1A, the instruction register 4 decodes and decodes the instruction code Cis stored in the instruction register 4 and outputs the control signal Fc, and the number of weights set in the instruction code Cis. Is connected to a weight counter 7 that is loaded and set.

Here, the weight counter 7 has a function of outputting a weight signal Fw corresponding to the number of weights to be set. The weight counter 7 is an up counter, a down counter, or a preset count value from the set value. It is possible to use various counters such as a counter that counts until a predetermined value or a counter that counts from a predetermined value to a set value. Then, in the present embodiment, the output terminal of the instruction decoder 5 is connected to the program counter 9 and each circuit in the microprocessor 1A, and the output terminal of the weight counter 7 is connected to the program counter 9, the instruction register 4, and the microprocessor. Processor 1A
Is connected to each circuit inside.

The operation of this embodiment having such a configuration will be described. When an address signal Fa designating an address at which an instruction to be executed next is stored is input from the program counter 9 of the microprocessor 1A to the program memory 2, the program memory 2 causes the address signal Fa from the program counter 9 to be changed. The instruction stored in the designated address is read, and the instruction code Cis corresponding to the instruction is output to the microprocessor 1A and stored in the instruction register 4.

Next, the instruction code Cis stored in the instruction register 4 is decoded and decoded by the instruction decoder 5,
A control signal Fc corresponding to the instruction code Cis is output from the instruction decoder 5, and this control signal Fc is input to the program counter 9 and each circuit in the microprocessor 1A. Further, when the number of waits is set in the specific bit of the instruction code Cis, the number of waits is set in the wait counter 7, and the wait counter 7 outputs the wait signal Fw corresponding to the number of waits set. The wait signal Fw is input to the program counter 9, the instruction register 4, and each circuit in the microphone processor 1A.

In the present embodiment, basically, the control signal Fc output from the instruction decoder 5 causes the corresponding instruction to be executed in each circuit in the microprocessor 1A, and the program counter 9 outputs the current instruction. Address signal Fa for designating the address of a value obtained by advancing the existing address by 1 or the control signal F from the instruction decoder 5
Address signal Fa that specifies the address related to the command of c
Is supplied to the program memory 2, and from the program memory 2, the next instruction code Cis corresponding to the newly designated address is supplied to the microprocessor 1A.

In this case, in this embodiment, as described above, by inserting a wait cycle for the instruction to be executed, the number of waits for ensuring the time required for instruction execution is the instruction code. When a specific bit of Cis can be set and the number of waits is set in the specific bit of the instruction code Cis, the number of waits is set in the weight counter 7 and the weight counter 7
Outputs a weight signal Fw. The wait signal Fw is input to the instruction register 4, the program counter 9, and each circuit in the microprocessor 1A. Then, according to the input wait signal Fw, the storage of the next instruction code Cis is suspended in the instruction register 4, the output of the next address signal Fa is stopped in the program counter 9, and the output of the current address signal Fa is stopped. The output is continued, and the execution of the current instruction is continued in each circuit in the microprocessor 1A by securing a necessary time corresponding to the number of waits.

In this way, according to the present embodiment,
The number of waits for inserting a wait cycle to secure the time required for instruction execution can be freely set in a specific bit of the instruction code Cis. Therefore, for example, for an instruction that takes a long time to execute, when operating with a high-speed clock Even when the number of waits is set and the waits are inserted, it is possible to easily change the specific bit value of the instruction code Cis and not insert the waits when operating at the low speed clock. After commercializing 1A, an instruction code C is issued for an instruction that is found to require weight insertion.
Weights can also be inserted by simply setting the specific bit value of is.

In the present embodiment, the control signal Fc obtained by decoding and decoding the instruction code Cis stored in the instruction register 4 by the instruction decoder 5 causes
The corresponding instruction is executed in each circuit of the microprocessor 1A, but when the wait counter 7 is set to the number of waits set in the specific bit of the instruction code Cis, the wait counter 7 outputs a predetermined number of waits corresponding to the number of waits. The weight signal is continuously output over time. During this output period, the instruction register 4 suspends the storage of the next instruction code Cis, and the program counter 9 stops the output of the next address signal Fa.
In each circuit in the microprocessor 1A, it becomes possible to secure the necessary processing time corresponding to the number of weights and execute the current instruction with high accuracy and accuracy.

[Second Embodiment] A second embodiment of the present invention will be described with reference to FIG. FIG. 2 is a block diagram showing the configuration of this embodiment.

In the present embodiment, as shown in FIG. 2, a conversion circuit is provided between the instruction register 4 and the weight counter 7 as compared with the first embodiment already described with reference to FIG. 11 is further provided, and in the present embodiment, the type of wait at the time of executing an instruction can be freely set in the specific bit of the instruction code Cis, and the conversion circuit 11 uses the specific bit of the instruction code Cis. It has a function of converting the type of weight set in (1) to the corresponding number of weights based on the conversion table. In this embodiment,
With this function, for example, the type of wait “1 cycle wait” set in the specific bit of the instruction code Cis is converted into the number of waits corresponding to “20 cycle wait” by the conversion circuit 11, A wide range of weight numbers can be associated with bits. The configuration of the other parts of the present embodiment is the same as that of the first embodiment already described, and therefore a duplicate description will not be given.

In the present embodiment, as described above, a wait cycle is inserted for an instruction to be executed, so that a specific bit of the instruction code Cis is given a wait time in order to secure a time required for executing the instruction. The type can be set, and the conversion circuit 11 converts the type of weight into the corresponding number of weights based on the set type of weight. Then, the converted weight number is set in the weight counter 7, and the weight signal Fw is continuously output from the weight counter 7 for the time corresponding to the set weight number. The wait signal Fw causes the instruction register 4 to generate the next instruction code C.
Since the storage of is is suspended, the output of the address signal Fa designating the next address is stopped in the program counter 9, and the output of the current address signal Fa is continued. Therefore, in each circuit in the microprocessor 1B, Execution of the current instruction is continued with a necessary time corresponding to the number of waits. The other operations of this embodiment are the same as those of the first embodiment already described, and therefore, duplicated description will not be given.

As described above, according to the present embodiment, the type of wait that inserts a wait cycle and secures the time required to execute an instruction can be freely set to a specific bit of the instruction code Cis, and the weight to be set is set. Since the type is converted into a weight number by the conversion circuit 11, it becomes possible to set a wider range of weight numbers in the weight counter 7. Therefore, in the present embodiment, for example, for an instruction that takes a long time to execute, even if the number of waits is set when operating at a high-speed clock and a wait is inserted, when operating at a low-speed clock, Instruction code Cis
It is possible to easily change the specific bit value of the instruction and not insert the wait. Also, for the instruction that is found to require the wait insertion after the commercialization of the microprocessor 1B, the specific bit value of the instruction code Cis. With a simple setting of, it is possible to insert a wide range of weight numbers.

In the present embodiment, the instruction code Cis stored in the instruction register 4 is decoded by the instruction decoder 5, and the control signal Fc obtained by the instruction decoder 5 executes the corresponding instruction in each circuit of the microprocessor 1B. Command code Cis to the weight counter 7.
The number of weights obtained by conversion in the conversion circuit 11 is set to the kind of weight set in the specific bit of.
Therefore, the wait counter 7 outputs a wait signal Fw corresponding to a wider number of waits based on the type of wait set in the specific bit of the instruction code Cis. During this output period, the instruction register In 4, the storage of the next instruction code Cis is suspended,
In the program counter 9, since the output of the next address signal Fa is stopped, each circuit of the microprocessor 1B secures a necessary time corresponding to a wide range of wait numbers, so that the current instruction is highly accurate. It will be possible to execute accurately.

[Third Embodiment] A third embodiment of the present invention will be described with reference to FIG. FIG. 3 is a block diagram showing the configuration of this embodiment.

In the present embodiment, as shown in FIG. 3, in contrast to the second embodiment which has already been described with reference to FIG. 2, the instruction decoder 5 sends an instruction based on the instruction code Cis. The conversion coefficient signal Fk related to the conversion coefficient is input to the conversion circuit 11 from the instruction decoder 5 by newly providing a function of creating a conversion coefficient corresponding to the type of the operation and outputting it as the conversion coefficient signal Fk. Is configured to. Then, the conversion circuit 11 uses the instruction code C
It has a function of converting the number of weights based on the type of weight set in the specific bit of is and the conversion coefficient signal Fk input from the instruction decoder 5. The configuration of the other parts of the present embodiment is the same as the second embodiment already described.
Since it is the same as the embodiment described above, duplicate description will not be given.

In the present embodiment, the conversion circuit 11 has a coefficient signal Fk output from the instruction decoder 5 based on the type of weight set in a specific bit of the instruction code Cis stored in the instruction register 4 and the instruction code Cis. The number of weights is converted based on and, and the converted number of weights is set in the weight counter 7. Since the other operations of the present invention are the same as those of the second embodiment already described,
No duplicate explanation will be given.

According to the present embodiment, in addition to the effects obtained in the second embodiment already described, the conversion circuit 11
However, since the number of weights is converted based on the type of weight set in the specific bit of the instruction code Cis stored in the instruction register 4 and the coefficient signal Fk output from the instruction decoder 5 based on the instruction code Cis, It is possible to execute a more precise and accurate instruction by performing a more detailed correspondence according to the type of operation and the clock speed.

[0033]

According to the first aspect of the present invention, the instruction is executed by the control signal output from the instruction decoder which decodes the instruction code. However, the wait number setting means causes the specific bit of the instruction code to execute the instruction. When the wait number is set and set in the wait counter, a wait cycle is inserted by the wait means based on the number of waits set in the wait counter by the wait number setting means to wait for instruction execution. Therefore, the optimum number of weights corresponding to the type of operation and clock speed related to the instruction to be executed can be set at any time independently of the instruction, and depending on the type of operation related to the instruction and the clock speed, It is possible to arbitrarily secure the optimum time for instruction execution and execute instructions with high accuracy, precision and efficiency.

According to the second aspect of the present invention, the instruction is executed by the control signal output from the instruction decoder which decodes the instruction code. However, the wait type setting means causes the specific bit of the instruction code to change when the instruction is executed. The number of weights set as the weight type and converted by the conversion output means to the weight number corresponding to the number of weights set by the weight type setting means, and the number of weights converted and output from the conversion output means by the weight number setting means. But,
When the wait counter is set as the number of waits during instruction execution, the wait means inserts a wait cycle based on the number of waits set in the wait counter by the wait number setting means to wait for instruction execution. , The number of weights is converted into the number of weights by the conversion, the optimum number of weights corresponding to the type of operation and clock speed related to the executed instruction, and the wide number of weights for a specific bit of the instruction code is the conversion instruction. It can be set independently at any time, and in accordance with the type of operation related to the instruction and the clock speed, a wide range of time optimal for instruction execution can be arbitrarily secured, making the instruction more accurate, accurate and efficient. It becomes possible to carry out.

According to the third aspect of the present invention, the instruction is executed by the control signal output from the instruction decoder which decodes the instruction code. However, the wait type setting means causes the specific bit of the instruction code to change when the instruction is executed. The weight is set as a weight type, and the conversion output means converts and outputs the corresponding number of weights based on the weight type set by the weight type setting means and the conversion coefficient detected from the instruction code by the instruction decoder. When the number of weights converted and output from the output means is set in the weight counter by the number of weights setting means as the number of weights at the time of executing the instruction, the weights are set in the weight counter by the number of weights setting means. Depending on the number, a wait cycle is inserted to wait for instruction execution. Therefore, it is possible to set the optimum number of weights corresponding to the type of operation and the clock speed related to the executed instruction and a wide range of specific bits of the instruction code at any time independently of the conversion instruction. ,
It is possible to arbitrarily secure a wide range of time optimum for instruction execution according to the type of operation related to the instruction and the clock speed, and execute the instruction more finely, accurately, and efficiently.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a third exemplary embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional microprocessor.

[Explanation of symbols]

1A, 1B, 1C ··· Microprocessor, 2 ··· Program memory, 4 ·· instruction register, 5 ·· instruction decoder, 7 ·· wait counter, 9 ·· program memory, 11 ·· conversion circuit.

Claims (3)

[Claims] 1. A time required for instruction execution is secured by executing an instruction by a control signal output from an instruction decoder for decoding an instruction code and inserting a wait cycle based on the number of waits corresponding to the instruction. In a microprocessor having a function, a weight number setting means for setting a specific bit of an instruction code as a number of waits when an instruction is executed and setting it in a weight counter, and a weight set in the wait counter by the weight number setting means. A microprocessor having a weight means for weighting instruction execution based on a number. 2. A time required for instruction execution is ensured by executing an instruction by a control signal output from an instruction decoder that decodes an instruction code and inserting a wait cycle based on the number of waits corresponding to the instruction. In a microprocessor having a function, a weight type setting means for setting a specific bit of an instruction code as a weight type at the time of instruction execution, and a weight type set by the weight type setting means are set to the corresponding number of weights. A conversion output means for converting and outputting, and a weight number setting means for setting the number of weights converted and output from the conversion output means to the weight counter as the number of weights at the time of executing the instruction and the weight number setting means for setting the weight counter to the weight counter. Based on the number of waits A microprocessor having: 3. A time required for instruction execution is ensured by executing an instruction by a control signal output from an instruction decoder for decoding an instruction code and inserting a wait cycle based on the number of waits corresponding to the instruction. In a microprocessor having a function, a wait type setting means for setting a specific bit of an instruction code as a wait type at the time of executing an instruction, a wait type set by the wait type setting means, and the instruction decoder Based on the conversion coefficient detected from the instruction code, the conversion output means for converting and outputting the corresponding weight number, and the number of weights converted and output from the conversion output means are set in the weight counter as the number of weights when the instruction is executed. The weight number setting means and the weight counter setting means set the weight counter. And a weight means for weighting instruction execution based on the number of waits to be performed.