JPH06259264A - Clock control circuit - Google Patents

Abstract

PURPOSE:To provide the clock control circuit which can omit an operation (program) for reloading a clock control register before interruption processing and can respond even to the plural and various kinds of interruption processing as well. CONSTITUTION:This circuit is provided with a flip-flop circuit 12 for inputting an interruption request signal 10 outputted from an interruption control circuit 3 and a processing completion time-control signal outputted from a CPU (central processing unit) 1 and for outputting an interruption generate signal for a clock selecting circuit 5 to select a high-speed clock signal from the input of the interruption request signal 10 to the input of the processing completion time control signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock control circuit for a microcomputer device.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing a clock control circuit of a conventional microcomputer apparatus. In the figure, 1 is a central processing unit (hereinafter referred to as CPU), and 2
Is a memory storing a program for operating the CPU 1,
Reference numeral 3 is an interrupt control circuit that causes the CPU 1 to perform interrupt processing in response to an interrupt signal input, 4 is a clock control register that sets the speed of the clock according to the contents of the program stored in the memory 2, and 5 is a clock control register 4. This is a clock selection circuit that selects the clock speed according to the set clock speed and outputs it as an internal clock signal. In the figure, two types of clocks, a high speed clock and a low speed clock, can be selected. Reference numeral 6 is an input / output circuit for inputting / outputting data to / from the outside, 7 is a control signal output from the CPU 1, 8 is a data bus, 9 is an internal clock signal, and the internal clock signal 9 is supplied from the clock selection circuit 5 to C
It is output to each of the PU 1, the memory 2, the interrupt control circuit 3, the clock control register 4, and the input / output circuit 6. Reference numeral 10 is an interrupt request signal output when the interrupt control circuit 3 interrupts the CPU 1, 11 is C
PU1 is a control signal for controlling the interrupt control circuit 3.

Next, the operation will be described. The CPU 1 sequentially executes the programs stored in the memory 2 in synchronization with the internal clock signal 9 output from the clock selection circuit 5. The high-speed clock and the low-speed clock are input to the clock selection circuit 5, and the high-speed clock and the low-speed clock are switched by the selection signal from the clock control register 4 and output as the internal clock signal 9. The clock control register 4 is written by the control signal 7 from the CPU 1 and the data bus 8, and which of the high-speed clock and the low-speed clock is used is set by the CPU 1 according to the contents of the program stored in the memory 2. .

The interrupt control circuit 3 outputs an interrupt request signal 10 to the CPU 1 when an interrupt signal is generated, holds the interrupt signal until the CPU 1 can accept the interrupt request signal 10, vice versa,
Interrupt signal is canceled or interrupt request signal 1
It is possible to prohibit sending 0 to the CPU 1.
The CPU 1 sets the operation of the interrupt control circuit 3 as described above, like the clock control register 4. When the interrupt signal is generated, the interrupt control circuit 3 outputs the interrupt request signal 10 to the CPU 1, and the CPU 1 executes the interrupt process according to the contents programmed in the memory 2 in advance. When the interrupt processing is completed, the CPU 1 outputs a processing completion control signal as the control signal 11 to the interrupt control circuit 3, and sets the interrupt control circuit 3 so that the next interrupt signal can be accepted.

In order to reduce power consumption, a normal user uses a low-speed clock when high-speed processing is not necessary, and uses a high-speed clock when high-speed processing is necessary or when an interrupt occurs. To create a program. When a program is created that switches to the high-speed clock when an interrupt occurs and returns to the low-speed clock after the interrupt processing is completed, the flowchart is as shown in FIG. 7. As shown in FIG. 7, in order to reduce power consumption, indirect processing for switching clocks is necessary in addition to processing directly related to the operation of the microcomputer device, such as processing after the occurrence of an interrupt and other processing. Has become.

[0006]

Since the conventional clock control circuit is constructed as described above, in order to select the clock corresponding to each interrupt signal, FIG.
As shown in, the contents of the clock control register 4 must be rewritten, and the program stored in the memory 2 becomes long. Further, since the interrupt process is started after the clock is switched, there is a problem that the response of the microcomputer device to the interrupt process is delayed.

The present invention has been made in order to solve the above problems. It is possible to omit the operation (program) for rewriting the clock control register before the interrupt processing, and to cope with a plurality of various interrupt processing. Even if it is, it aims at obtaining the clock control circuit which can respond at high speed.

[0008]

A clock control circuit according to a first aspect of the present invention inputs an interrupt request signal output from an interrupt control circuit and a control signal at the time of completion of processing output from a central processing unit, and interrupts the interrupt. A flip-flop circuit that outputs an interrupt generation signal that causes the clock selection circuit to select a high-speed clock signal is provided between the input of the request signal and the input of the processing completion control signal.

A clock control circuit according to a second aspect of the present invention decodes an interrupt selection signal selected from a plurality of interrupt signals, and outputs a signal according to a speed of a high-speed or low-speed internal clock signal designated in advance. Input the interrupt request signal output from the decode circuit and the interrupt control circuit and the processing completion control signal output from the central processing unit, and from the input of the interrupt request signal to the processing completion control signal During this period, the flip-flop circuit that outputs the interrupt generation signal and the signal output of the decode circuit are input, and the interrupt generation signal of the flip-flop circuit is input and the high-speed internal clock signal is specified for the signal output of the decode circuit, and High-speed clock selection circuit while the interrupt generation signal of the flip-flop circuit is generated It is obtained by a clock control signal selection circuit for outputting a selection signal for selecting a clock signal.

According to a third aspect of the present invention, there is provided a clock control circuit, which decodes an interrupt selection signal selected from a plurality of interrupt signals, and outputs the signal in accordance with a speed of an internal clock signal designated in advance. , The interrupt request signal output from the interrupt control circuit and the processing completion control signal output from the central processing unit are input, and an interrupt occurs between the input of the interrupt request signal and the processing completion control signal. The signal output of the decode circuit while the flip-flop circuit that outputs the generated signal and the signal output of the decode circuit are input and the interrupt generation signal of the flip-flop circuit is input and the interrupt generation signal of the flip-flop circuit is generated The clock selection circuit outputs a selection signal for selecting the clock signal according to the Tsu is that a click control signal selection circuit.

[0011]

According to the first aspect of the present invention, a flip-flop circuit receives an interrupt request signal output from an interrupt control circuit when an interrupt process occurs and a process completion control signal output from a central processing unit when an interrupt process ends. ,
From the input of the interrupt request signal to the input of the processing completion control signal, the clock selection circuit outputs an interrupt generation signal for selecting a high-speed clock signal. Therefore, even if the interrupt processing occurs, the operation of rewriting the clock control register before the interrupt processing can be omitted.

According to another aspect of the clock control circuit of the present invention, the decode circuit decodes the interrupt selection signal selected from the plurality of interrupt signals, and decodes the interrupt selection signal according to the speed of the internal clock signal designated in advance as high speed or low speed. And outputs the signal to the clock control signal selection circuit. Also,
The flip-flop circuit inputs an interrupt request signal output from the interrupt control circuit when an interrupt process occurs and a process completion control signal output from the central processing unit at the end of the interrupt process, and inputs the interrupt request signal. The interrupt generation signal is output to the clock control signal selection circuit from the time until the processing completion control signal is input. Further, the clock control signal selection circuit selects the high-speed clock signal to the clock selection circuit while the high-speed internal clock signal is specified for the signal output of the decoding circuit and the interrupt generation signal of the flip-flop circuit is generated. Output a selection signal. Therefore, it is possible to switch the internal clock signal to the high-speed clock only for a specific interrupt signal, and even if the interrupt processing occurs, the operation of rewriting the clock control register before the interrupt processing can be omitted.

According to another aspect of the clock control circuit of the present invention, the decode circuit decodes the interrupt selection signal selected from the plurality of interrupt signals, and the clock control signal is generated according to the speed of the internal clock signal designated in advance. The signal is output to the selection circuit. Further, the flip-flop circuit inputs an interrupt request signal output from the interrupt control circuit when an interrupt process occurs and a process completion control signal output from the central processing unit at the end of the interrupt process, and inputs the interrupt request signal. After that, the interrupt generation signal is output to the clock control signal selection circuit from the time when the processing completion control signal is input. Further, the clock control signal selection circuit outputs a selection signal for causing the clock selection circuit to select the clock signal according to the signal output of the decoding circuit while the interrupt generation signal of the flip-flop circuit is being generated. Therefore, the speed of the internal clock signal can be switched according to the interrupt selection signal, and even if the interrupt processing occurs, the operation of rewriting the clock control register before the interrupt processing can be omitted.

[0014]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. 1 is a block diagram showing a clock control circuit according to an embodiment of the present invention. In FIG.
Is a CPU (central processing unit), 2 is a memory (storage means) that stores a program for operating the CPU 1, 3 is an interrupt control circuit that causes the CPU 1 to perform interrupt processing in response to the input of an interrupt signal, and 4 is stored in the memory 2. A clock control register 5 for setting the speed of the clock according to the contents of the program, a clock selection circuit 5 for selecting and outputting the speed of the internal clock signal 9 according to the speed of the clock set by the clock control register 4, 6 Is an input / output circuit for inputting / outputting data to / from the outside, 7 is a control signal output from the CPU 1, 8 is a data bus, 9 is an internal clock signal, and the internal clock signal 9 is supplied from the clock selection circuit 5 to the CPU 1 , Memory 2, interrupt control circuit 3, clock control register 4, and input / output circuit 6. Reference numeral 10 is an interrupt request signal output when the interrupt control circuit 3 interrupts the CPU 1, and 11 is a control signal for the CPU 1 to control the interrupt control circuit 3. The configuration up to this point is similar to the conventional technique.

An interrupt request signal 10 output from the interrupt control circuit 3 to the CPU 1 is connected to a set input (S) 12, and one of the control signals 11 output from the CPU 1 to the interrupt control circuit 3 is an operation completion. Set control flip-flop (flip-flop circuit) whose time control signal is connected to the reset input (R) and whose output (Q) is connected to the OR circuit 13, and 13 is the output (Q) of the set-reset flip-flop 12 and the clock It is an OR circuit which inputs the output of the control register 4 and outputs it to the clock selection circuit 5. The clock selection circuit 5 is ORed.
A high-speed clock is generated when the input from the circuit 13 is at a high potential level, and a low-speed clock is generated when the input is at a low potential level.

Next, the operation will be described. When the interrupt signal is input to the interrupt control circuit 3, the interrupt control circuit 3 outputs the interrupt request signal 10 to the CPU 1 unless it is in the interrupt disabled state. Since the interrupt request signal 10 is output to the set input (S) of the set / reset flip-flop 12 in addition to the CPU 1, the interrupt / reset signal 10 sets the set / reset flip-flop 12 to the set state, and the output Q has a low potential level ( Hereinafter, a higher potential level (hereinafter referred to as “L”)
"H"). This signal is output to the OR circuit 13 as an interrupt generation signal. Next, the clock selection circuit 5 operates so as to output the low-speed clock when the interrupt generation signal from the OR circuit 13 is “L”, and outputs the high-speed clock when the interrupt generation signal is “H”. Becomes high, the high speed clock is selected. Summarizing the above operation, when the output of the clock control register 4 is set to “L”, the interrupt processing occurs and the interrupt request signal 10 is input to the CPU 1, so that the interrupt request signal 10 is changed. Internal clock signal 9
Will be switched to the high-speed clock.

Next, when the interrupt processing is completed, the CP
U1 outputs a control signal upon completion of processing to the interrupt control circuit 3. Further, the control signal upon completion of this process causes the set / reset flip-flop 12 to be in a reset state and output Q
Becomes'L '. Set reset flip-flop 12
When the output Q of the above becomes "L", it is the reverse of the time when the interrupt processing occurs, and when the output of the clock control register 4 is "L", the output of the OR circuit 13 becomes "L" and the internal clock signal 9 switches to the low speed clock.

FIG. 2 shows a flowchart when the same operation as the operation shown in the flowchart of the prior art is executed. As shown in the figure, it is not necessary to rewrite the clock control register 4, which is an indirect process. In this embodiment,
This has the effect of speeding up the response of the microcomputer device to the interrupt.

Example 2. In the first embodiment described above, the internal clock signal 9 is always switched to the high-speed clock when the interrupt processing occurs. However, when there are a plurality of interrupt signals, only the internal clock signal of a specific interrupt signal is changed. The signal 9 may be configured to switch to the high speed clock. FIG. 3 is a block diagram showing a clock control circuit according to an embodiment of the present invention.
In the figure, 1 to 13 have the same configuration as that of the first embodiment.

Reference numeral 14 is an interrupt selection signal for outputting to the CPU 1 which interrupt processing is occurring among a plurality of interrupt signals, and 15 is for decoding the interrupt selection signal 14 to generate an interrupt requiring a high-speed clock. It is a decoding circuit that outputs'H 'to the OR circuit 13 only when Reference numeral 16 is a clock control signal selection circuit that switches between the output of the clock control register 4 and the output of the OR circuit 13 to the clock selection circuit 5. The clock control signal selection circuit 16 inputs the interrupt generation signal of the set / reset flip-flop 12 and outputs “H” from the OR circuit 13 while the interrupt generation signal is generated from the set / reset flip-flop 12. The clock selection circuit 5 is configured to select a high-speed clock signal.

Next, the operation will be described. This Example 2
Then, the decode circuit 15 and the OR circuit 13 select an interrupt signal requiring a high-speed clock, and the output Q of the set / reset flip-flop 12 is'H 'only during the period in which the interrupt process is executed, as in the first embodiment. 'Becomes
The'H 'output causes the clock control signal selection circuit 16 to select the output of the OR circuit 13, so that the internal clock signal 9 becomes a high-speed clock. Therefore, the internal clock signal 9 can be switched to the high-speed clock only for the specific interrupt signal.

Example 3. In the second embodiment, the two types of high-speed clocks and the low-speed clocks are configured to be switched, but it may be configured to be applicable to three or more types of clocks. FIG. 4 is a block configuration diagram showing a clock control circuit according to an embodiment of the invention of claim 3, and in the figure, 1 to 14 and 16 have the same configuration as that of the second embodiment. Reference numeral 17 is an expansion of the decoding circuit 15 of the second embodiment, which has a plurality of decode outputs corresponding to respective clocks in order to select a clock corresponding to each interrupt signal. The OR circuit 13 takes the logical sum and inputs it to the clock control signal selection circuit 16. As an operation, when one interrupt process occurs, a clock corresponding to the interrupt process is selected by the decode circuit 17 and the OR circuit 13 and the interrupt process is executed as in the second embodiment. The clock control signal selection circuit 16 selects the output of the OR circuit 13, and the internal clock signal 9 is switched to the required clock.

Example 4. In the above Examples 1 to 3, the CPU
1 and the internal clock signal 9 used for the operation of each control register and the like to which the present invention is applied, the clocks for other peripheral circuits such as a timer circuit, a serial I / O circuit, and an A / D conversion circuit are shown. The present invention may be applied to.
FIG. 5 is a block diagram showing a clock control circuit according to another embodiment of the present invention.
2 has the same structure as that of the first embodiment. Reference numeral 18 denotes a timer circuit, which is a clock selection circuit 5b.
It operates by the internal clock signal 9b output from Thus, even if the internal clock signal 9 generated by the clock selection circuit 5 of the first embodiment is applied to other peripheral circuits, a low-speed clock is normally input to reduce power consumption, and when an interrupt occurs. The peripheral circuits can be operated with a high speed clock.

Further, in the third embodiment, a configuration is shown in which three or more kinds of clocks can be applied to the internal clock signal 9 used for the operation of the CPU 1 and each control register, but even in this case, FIG. Peripheral circuit 1 as shown
You may apply three or more types of clocks to 9. A fixed signal, that is, a state in which no clock is input, may be selected as the slowest clock.

[0025]

As described above, according to the first aspect of the invention, the clock selection circuit is caused to select the high-speed clock signal from the input of the interrupt request signal to the input of the processing completion control signal. Since the flip-flop circuit that outputs the interrupt generation signal is provided, even if an interrupt process occurs, the operation of rewriting the clock control register before the interrupt process can be omitted and a high-speed response can be achieved. The clock control circuit can be obtained.

According to the invention of claim 2, a decoding circuit for decoding the interrupt selection signal and outputting the signal in accordance with the speed of the designated internal clock signal, and a control signal upon completion of processing after inputting the interrupt request signal Until a high-speed internal clock signal is specified for the flip-flop circuit that outputs the interrupt generation signal and the decode circuit signal output, and the clock signal is generated while the interrupt generation signal of the flip-flop circuit is generated, Since it is configured to include a clock control signal selection circuit that outputs a selection signal that causes the selection circuit to select a high-speed clock signal, the internal clock signal can be switched to the high-speed clock only for a specific interrupt signal, and the interrupt signal is generated. Even if processing occurs, it is possible to rewrite the clock control register before interrupt processing. It can be omitted, the effect of clock control circuitry capable of response is obtained at high speed.

According to the invention of claim 3, a decode circuit for decoding the interrupt selection signal and outputting the signal in accordance with the speed of the designated internal clock signal, and a control signal at the time of processing completion after inputting the interrupt request signal Until a signal is input, a flip-flop circuit that outputs an interrupt generation signal and, while the interrupt generation signal of the flip-flop circuit is generated, selects a clock signal in the clock selection circuit according to the signal output of the decode circuit Since it is configured to include a clock control signal selection circuit that outputs a selection signal to enable, the speed of the internal clock signal can be switched according to the interrupt selection signal, and the operation of rewriting the clock control register before interrupt processing can be performed. A clock control circuit that can be omitted and can respond at high speed is obtained. There is a result.

[Brief description of drawings]

FIG. 1 is a block diagram showing a clock control circuit according to an embodiment of the present invention.

FIG. 2 is a CPU when interrupt processing occurs according to the invention of claim 1;
3 is a flowchart showing the operation of FIG.

FIG. 3 is a block diagram showing a clock control circuit according to an embodiment of the present invention.

FIG. 4 is a block diagram showing a clock control circuit according to an embodiment of the present invention.

FIG. 5 is a block diagram showing a clock control circuit according to another embodiment of the present invention.

FIG. 6 is a block diagram showing a conventional clock control circuit.

FIG. 7 is a flowchart showing the operation of the CPU when a conventional interrupt process occurs.

[Explanation of symbols]

1 CPU (Central Processing Unit) 2 Memory (Storage Unit) 3 Interrupt Control Circuit 4 Clock Control Register 5 Clock Selection Circuit 9 Internal Clock Signal 10 Interrupt Request Signal 12 Set Reset Flip-Flop (Flip-Flop Circuit) 14 Interrupt Selection Signals 15, 17 Decode circuit 16 Clock control signal selection circuit

Claims (3)

[Claims] 1. Storage means for storing a program for operating a central processing unit, and an interrupt control circuit for outputting an interrupt request signal to the central processing unit in response to input of an interrupt signal to cause the central processing unit to perform interrupt processing. , A clock control register for setting the speed of the clock according to the contents of the program stored in the storage means, and selecting and outputting the speed of the internal clock signal according to the speed of the clock set by the clock control register A clock selection circuit, an interrupt request signal output from the interrupt control circuit, and a processing completion control signal output from the central processing unit are input, the interrupt request signal is input, and then the processing completion control signal is input. Until then, it outputs an interrupt generation signal that causes the clock selection circuit to select a high-speed clock signal. A clock control circuit having a flip-flop circuit for inputting power. 2. A storage means for storing a program for operating a central processing unit, and a plurality of interrupt signals input to the central processing unit together with an interrupt request signal and an interrupt selection signal selected from the plurality of interrupt signals. Output,
An interrupt control circuit for causing the central processing unit to perform an interrupt process, a clock control register for setting a clock speed according to the contents of the program stored in the storage means, and a clock speed set by the clock control register. A clock selection circuit that selects and outputs the speed of the internal clock signal in response to it, and decodes the interrupt selection signal that is output from the interrupt control circuit, and outputs a signal according to the speed of the high-speed or low-speed internal clock signal specified in advance. A decoding circuit, an interrupt request signal output from the interrupt control circuit, and a processing completion control signal output from the central processing unit, the interrupt request signal is input, and then the processing completion control signal is input. Until that time, a flip-flop circuit that outputs an interrupt The signal output of the decode circuit is input, the interrupt generation signal of the flip-flop circuit is input, a high-speed internal clock signal is specified for the signal output of the decode circuit, and the interrupt generation signal of the flip-flop circuit is generated. And a clock control signal selection circuit that outputs a selection signal that causes the clock selection circuit to select a high-speed clock signal. 3. A storage unit storing a program for operating a central processing unit, and a plurality of interrupt signals input to the central processing unit together with an interrupt request signal and an interrupt selection signal selected from the plurality of interrupt signals. An interrupt control circuit for outputting and causing the central processing unit to perform an interrupt process, a clock control register for setting the speed of the clock according to the contents of the program stored in the storage means, and a clock for the clock set by the clock control register. A clock selection circuit that selects and outputs the speed of the internal clock signal according to the speed, and a decode that decodes the interrupt selection signal output from the interrupt control circuit and outputs the signal according to the speed of the internal clock signal specified in advance. Circuit and the interrupt request signal output from the above interrupt control circuit A flip-flop circuit that outputs an interrupt generation signal from the input of the processing completion control signal output from the central processing unit to the input of the interrupt request signal to the input of the processing completion control signal; While the signal output of the decode circuit is input and the interrupt generation signal of the flip-flop circuit is input and the interrupt generation signal of the flip-flop circuit is generated,
A clock control circuit, comprising: a clock control signal selection circuit that outputs a selection signal that causes the clock selection circuit to select a clock signal according to the signal output of the decoding circuit.