JP2626125B2 - Microcomputer - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer having a plurality of built-in oscillation circuits, and more particularly, to a microcomputer that can achieve lower power consumption.

[Conventional technology]

A microcomputer with multiple built-in oscillation circuits
For example, one oscillator circuit (for example, an 8 MHz oscillation circuit) is used for applications that require high-speed operation (for example, various types of control), and the other oscillator circuit (for example, a 32 kHz oscillation circuit) consumes less power than the operating speed. By using it for applications where reduction is prioritized (for example, timing operation using a battery as a power supply), one microcomputer (hereinafter referred to as a microcomputer) can respond to each application. There is something.

Conventionally, this kind of microcomputer is capable of switching a plurality of oscillation circuits by a program. For example, by writing high to the system clock switching flag, the output clock of the oscillation circuit for high-speed operation (hereinafter, referred to as a main clock) is changed to the output clock of the oscillation circuit for low-speed, low-consumption operation (hereinafter, referred to as a subclock). The sub clock is switched to the main clock by writing low to the system clock switching flag.

Also, when operating with the sub-clock, it has a function of stopping the main clock in order to reduce power consumption as much as possible. For example, by writing high to the main clock stop flag, the main clock can be stopped, excess power consumption can be suppressed, and power consumption can be reduced.

FIG. 2 is a block diagram of a microcomputer showing an example of such a prior art.

As shown in FIG. 2, in the conventional microcomputer, the output of the subsystem clock oscillation circuit 1 and the output of the main system clock oscillation circuit 2 are input to a system clock switching timing detection circuit (hereinafter referred to as a detection circuit) 4. . The detection circuit 4 detects a timing at which the subsystem clock and the main system clock can be switched with each other, and outputs the system clock selection signal to the selector 3 in synchronization with the timing. For example, when the system clock selection signal is high, the selector 3 selects the subsystem clock, and when low, the selector 3 selects the main system clock. On the other hand, the system clock switching flag (SCC0) 7 latches the value bit0 of the internal data bus 8 when the output of the AND gate 11 is high, and outputs it to the detection circuit 4. The main system stop flag (SCC1) 6 latches the value bit1 of the internal data bus 8 when the output of the AND gate 11 is high, and outputs it to the main system clock oscillation circuit 2. For example, when high is written to the SCC1 flag 6, the main system clock oscillation circuit 2 stops oscillating. The address decoder 10 receives the contents of the internal address bus 9, decodes the assigned addresses of the SCC0 flag 7 and the SCC1 flag 6, and outputs a high. here,
It is assumed that the SCC0 flag 7 and the SCC1 flag 6 are mapped to different bits of a register called SCC. The WR signal 12 is a flag write signal, and is input to one input terminal of the AND gate 11. When the address decoder 10 and the WR signal 12 are both high, the AND gate 11 outputs the SCC0 flag 7
Data writing to the SCC1 flag 6 is permitted.

 Next, the clock switching operation will be described.

First, the central processing circuit (not shown) in the microcomputer
The address of the SCC0 flag 7 is output to the internal address bus 9 and the data to be written is output to the internal data bus 8. The address decoder 10 decodes the value of the internal address bus 9 and outputs high. Thereafter, the WR signal 12, which is the data write enable signal, is set to high. As a result, the AND gate 11 becomes high, so that the data of the internal data bus 8 is written to the SCC0 flag 7. When high is written to the SCC0 flag 7, the detection circuit 4 outputs a system clock selection signal to the selector 3 in synchronization with the switchable timing of the main system clock and the subsystem clock. As a result, the selector 3 inputs high and selects the subsystem clock.

Next, the stop operation of the main system clock will be described.

First, the central processing unit outputs the address of the SCC0 flag 7 to the internal address bus 9 and outputs data to be written to the internal data bus 8. Next, the address decoder 10 decodes the value of the internal address bus 9. After a while, WR
When the signal 12 goes high, the AND gate 11 goes high, so that the value of the internal data bus 8 is written to the SCC1 flag 6. At this time, when high is written to the SCC1 flag 6, the main system clock oscillation circuit 2 stops oscillation.

As described above, the switching operation of the system clock and the stop of the main system clock oscillation circuit 2 are performed.

On the other hand, when switching from the subsystem clock to the main system clock, first, a low is written to the SCC1 flag 6. Then, after the main system clock oscillation circuit 2 starts oscillating, a sufficient time is taken to write a low to the SCC0 flag 7, and the detection circuit 4 synchronizes with the switchable timing of the main system clock and the subsystem clock. And outputs a system clock selection signal to the selector 3. The selector 3 inputs a row and selects a main system clock.

As described above, it is possible to switch from the subsystem clock to the main system clock.

[Problems to be solved by the invention]

In the above-described conventional microcomputer, when switching the system clock, it is necessary to select the time when the microcomputer does not malfunction.

In other words, the switching is performed when it is guaranteed that both the main system clock and the subsystem clock are high or both low. Therefore, it takes a maximum of one cycle of the sub clock at the time of switching, and it is possible to determine when the switching is performed. Therefore, the main clock must be stopped after the maximum switching time has elapsed.

For example, if 4MHz is used for the main system clock and 32kHz is used for the subsystem clock, the main clock is used for one cycle of the subsystem clock (approximately 30μs when 32kHz is used) from the time of switching to the subclock. Cannot be stopped.

For this reason, for a while after switching to the subsystem clock, the low power consumption mode in which the main system clock is stopped cannot be performed, and the life of the battery during battery backup is shortened. Therefore, when a user creates a program, there is a drawback in that the number of machine cycles must always be kept in mind and the time until the main system clock is stopped must be considered.

Also, if high is erroneously written to the main clock stop flag and the system clock switching flag at the same time while operating with the main system clock, the main system clock stops and the microcomputer itself stops operating. There is a disadvantage that the main clock stop flag and the system clock switching flag cannot be set simultaneously.

It is an object of the present invention to prevent the main system clock from being stopped and to simultaneously set the high to the main system clock stop flag and the system clock switching flag even if high is erroneously written to the main system clock stop flag during operation with the main system clock. It is an object of the present invention to provide a microcomputer capable of stopping the main system clock at the same time as switching to the subsystem lock when switching from the main system clock to the subsystem clock by writing.

[Means for solving the problem]

The microcomputer of the present invention includes a first oscillation circuit that outputs a first clock, a second oscillation circuit that outputs a second clock, and a selection instruction signal that specifies the first or second clock. A timing detection circuit that detects the first and second selection timings based on the detection signal, a selection circuit that selects and outputs the first or second clock based on a detection signal of the timing detection circuit, A stop signal for instructing stop of oscillation of the second oscillation circuit and an AND circuit that receives an output signal of the timing detection circuit as inputs, and the first or second oscillation circuit is stopped by an output of the AND circuit. It is configured as follows.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a microcomputer showing one embodiment of the present invention.

As shown in FIG. 1, in this embodiment, the output clock of the subsystem clock oscillation circuit 1 and the output clock of the main system clock oscillation circuit 2 are controlled by a system clock switching timing detection circuit (hereinafter, referred to as the conventional example).
4 (referred to as a detection circuit). The detection circuit 4 detects a timing at which the main system clock and the subsystem clock can be switched with each other, and outputs a latched value to the selector 3 as a system clock selection signal in synchronization with the timing. The selector 3 selects the main system clock when the system clock selection signal is low, for example, and selects the subsystem clock when the system clock selection signal is high. The SCC0 flag 7 latches the value of the internal data bus 8 when the output of the AND gate 11 is high, and outputs it to the detection circuit 4. Further, the SCC1 flag 6 similarly latches the value of the internal data bus 8 when the output of the AND gate 11 is high, and outputs it to the AND gate 5. On the other hand, the address decoder 10 decodes the addresses of the SCC0 flag 7 and the SCC1 flag 6, and outputs high. The AND gate 5 outputs high when the output of the SCC1 flag 6 is high and the system clock selection signal output from the detection circuit 4 is high. The main system clock oscillation circuit 2 stops oscillation when the output of the AND gate 5 is high. The WR signal 12 is a flag write enable signal and is supplied to the AND gate 11. That is, the AND gate 11 permits the writing of data to the SCC0 flag 7 and the SCC1 flag 6 when the output of the address decoder 10 and the WR signal 12 are both high.

Next, the operation of the microcomputer will be described.

First, the central processing circuit (not shown) outputs the addresses of the SCC0 flag 7 and the SCC1 flag 6 to the internal address bus 9 and outputs the value (data) to be written to the internal data bus 8. Therefore, the address decoder 10 decodes the value of the internal address bus 9 and outputs high.

Thereafter, when the WR signal 12 is made high, the output of the AND gate 11 becomes high, and the SCC0 flag 7 and the SCC1 flag 6 latch the value of the internal data bus 8. At this time, for example, when the high is latched in the SCC0 flag 7 to select the subsystem clock, and the high is also latched in the SCC1 flag 6 to stop the main system clock oscillation circuit 2, the detection circuit 4 Detects a timing at which the main system clock and the subsystem clock can be switched with each other, latches high in synchronization with the timing, and outputs high to the selector 3 and the AND gate 5. As a result, the selector 3 inputs a high signal to select the sub clock, and switches the system clock.

On the other hand, the output of the AND gate 5 becomes high because the system clock selection signal and the SCC1 flag 6 are high, and outputs high to the main system clock oscillation circuit 2. Therefore, the main system clock oscillation circuit 2 inputs high and immediately stops oscillation.

As described above, the operation of switching the system clock and the operation of stopping the main system clock oscillation circuit 2 can be performed simultaneously.

Further, switching from the subsystem clock to the main system clock may be performed in the same manner as in the above-described conventional example, and a description thereof will be omitted.

〔The invention's effect〕

As described above, the microcomputer of the present invention controls the main system clock oscillation circuit by the logical product of the output of the system clock switching timing detection circuit and the output of the main system clock stop flag, and When switching to the system clock, there is an effect that the main system clock can be stopped immediately.

In addition, according to the present invention, even when the main system clock stop flag is erroneously written to high during operation with the main system clock, the logical AND with the switching timing detection circuit output is taken, so that the stop of the main system clock can be prevented. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a block diagram of a microcomputer showing one embodiment of the present invention, and FIG. 2 is a block diagram of a microcomputer showing one example of the prior art. 1 ... Subsystem clock oscillation circuit, 2 ... Main system clock oscillation circuit, 3 ... Selector, 4 ... System clock switching timing detection circuit, 5,11 ... AN
D gate, 6: Main system clock stop flag,
7 System clock switching flag, 8 Internal data bus, 9 Internal address bus, 10 Address decoder, 12 WR signal, 13 System clock.

Claims (2)

(57) [Claims] A first oscillating circuit for outputting a first clock, a second oscillating circuit for outputting a second clock, and a first instruction signal for designating the first or second clock. A timing detection circuit for detecting first and second selection timings, a selection circuit for selecting and outputting the first or second clock based on a detection signal of the timing detection circuit, and the first or second An AND circuit that receives a stop signal for instructing the oscillation circuit to stop oscillating and an output signal of the timing detection circuit, wherein the output of the AND circuit stops the first or second oscillation circuit. Characteristic microcomputer. 2. A system clock switching timing detection circuit for detecting a switching timing of a system clock from a subsystem clock oscillation circuit and a main system clock oscillation circuit based on an output of a system clock switching flag. A microcomputer comprising: an AND gate for calculating an AND of an output of the main system clock stop flag and an output of the main system clock stop flag, wherein the output of the AND gate controls a main system clock oscillation circuit.