JPH0322613A - Data selection circuit - Google Patents

Abstract

PURPOSE:To attain sure switching even when either one of input signals does not come by generating a pulse signal to apply switching when no switching is implemented even after a prescribed time elapses after the level change of a selection switching signal. CONSTITUTION:Output signals of D flip-flops FP3, FF4 and a 1st input signal DI1 are inputted, an output signal of a 3rd D flip-flop FF3 has a change after a prescribed time, an output signal of a 4th D flipflop FF4, that is, a 2nd selection control signal SC2 has no level change, then a pulse signal is generated from a switching control circuit 4, the pulse signal is fed to an input terminal of a sampling clock of the D flip-flop FF4 from an inverter I3 via a gate circuit G6 to change the level of the 2nd selection control signal SC2. Thus, even when one of the input signals DI1, DI2 is not inputted to attain switching.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data selection circuit, and more particularly to a data selection circuit that switches and selects two asynchronous data input signals using a selection switching signal and outputs the selected data. (Prior Art) Conventionally, this type of data selection circuit, as shown in FIG. The flip-flop F F1 and the second selection control signal SC2 are held at an inactive level when they are at an active level, and when the second selection control signal SC2 is at an inactive level, the first input signal DI1 is used as a sampling clock. 1st
A second D-flip-flop FF2 outputs a first selection control signal SCl whose level is obtained by shifting the output signal of the D-flip-flop FF1 by a predetermined time and inverting the output signal of the D-flip-flop FF1.
a first selection control circuit 1 comprising a first selection control circuit 1 and a first input signal D;
A third D-flip-flop FF shifts the output signal of the first D-flip-flop FFl by a predetermined time using I1 as a sampling clock; −
A fourth shifter shifts the output signal of the flip-flop FF by a predetermined time and outputs it as a second selection control signal SC2.
A second selection control circuit 2 includes a D-7 flip-flop FF4, gate circuits 01 to G, and an inverter I4, and receives first and second selection control signals SC. , SC2 selects and outputs one of the first and second input signals DII and DI2. Figure 7 is a timing diagram of the signals of each part to explain the operation of this circuit. First, the output signal Do is input to the input signal DI. Input signal DI from
When switching to 2, the selection switching signal SEL is changed from a low level (hereinafter referred to as "L") to a high level (hereinafter referred to as "H"). After the selection switching signal SEL becomes ゛゜H'', the input signal DIR D-flip-flop 1 on the first falling edge of
FF. output Q becomes "H", and input signal DI. At the next falling edge of , the output Q of the D-flip-flop FF2 (hereinafter simply referred to as FF, the same goes for the others), that is, the first selection control signal SCl, goes to "L", and the output Q of FF goes to "H". I
1, and the output of the gate circuit G1 becomes "L II." Immediately after this, at the rising edge of the input signal DI2, the output Q of the FF4, that is, the second selection control signal SC2 becomes "H", and the output of the gate circuit G2 becomes "H". The output of is the input signal D I 2
This is the inverted signal. Therefore, the output signal D. is the input signal DI
This is the inverted signal of 2. That is, when the selection switching signal SEL changes from "L" to "H", the input signal DI. When two falling edges of DI. When one rising edge of is detected, a signal that is an inversion of the input signal DI2 begins to be output. Conversely, the output signal D. from the input signal DI z to the input signal DI. When switching to , change the selection switching signal SEL from "H" to "L". After the selection switching signal SEL becomes “L”, the input signal DI
．． At the first falling edge of FF, the output Q of FF1 becomes "L", and at the next falling edge of input signal DIl, the output Q of FF becomes "L". Immediately after this input signal DI. At the rising edge of FF. output Q, that is, selection control signal SC2
becomes “L”, and the output of gate circuit G2 becomes “L”.
It becomes II. When the selection control signal SC2 becomes "L", the FF2 is released from the set state and the next input signal DI. At the falling edge of , the output Q of FF2, that is, the selection control signal SCl goes “H”.
Therefore, the output of the gate circuit G1 receives the input signal DI. is output. Therefore, the input signal DI1 is output as the output signal Do. That is, when the selection switching signal SEL changes from "H" to "LI+", two falling edges of the input signal DI. are detected, counting from the time when the level of the selection switching signal SEL changes,
And counting from this time, the input signal DI. When one rising edge of input signal DI.
When one falling edge of is detected, the input signal DI1 starts to be output. That is, when the selection switching signal SES rises, the gate circuit GK is first brought into an inactive state, and then the gate circuit G2 is brought into an active state. The minimum time required for this is from the fall of the input signal DI, to the time when the input signal DI
This is the time until the first rise of 2. Conversely, when the selection switching signal SEL falls, the gate circuit G2 is first brought into an inactive state, and then the gate G1 is brought into an active state. The minimum time required for this is the input signal DI. After the rise of the input signal DI.
This is the time until the first falling edge of .

[Problem to be solved by the invention]

The conventional data selection circuit described above includes selection control circuit 1.2.
Since the input signals DI. and DI. , D.I. The disadvantage is that switching cannot be performed if one of the two is no longer input. An object of the present invention is to provide a data selection circuit that can perform a switching operation even if one of the input signals is no longer input. [Means for Solving the Problems] A data selection circuit of the present invention includes a first flip-flop circuit that shifts a selection switching signal by a predetermined time using a first input signal as a sampling clock, and a second selection control signal. is at the active level, it holds the inactive level and this second
When the selection control signal is at an inactive level, the output signal of the first flip-flop circuit is shifted by a predetermined time using the first input signal as a sampling clock, and the first selection control signal is set to an inverted level. The second output
a first selection control circuit comprising a flip-flop circuit, and a third flip-flop circuit that shifts the output signal of the first flip-flop circuit by a predetermined time using the first input signal as a sampling clock; and a fourth flip-flop circuit that shifts the output signal of the third flip-flop circuit by a predetermined time using the second input signal as a sampling clock and outputs the shifted signal as the second selection control signal. a selection control circuit;
a switching circuit that selects and outputs one of the first and second input signals according to the first and second selection control signals; and a predetermined level change after a level change in the output signal of the third flip-flop circuit. and a switching control circuit that generates a pulse signal to change the level of the second selection control signal when there is no change in the level of the second selection control signal for a period of time. [Example] Next, an example of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a first embodiment of the present invention. This embodiment is different from the conventional data selection circuit shown in FIG.
-Flip-flop FF,,FF. The output signal of DI. is input and there is a level change in the output signal of the third D-flip-flop FF, and after a predetermined period of time, the output signal of the fourth D-flip-flop FF. A switching control circuit 4 is provided which generates a pulse signal when there is no level change in the output signal of the output signal S02, that is, the second selection control signal S02.
- The second selection control signal SC2 is applied to the sampling clock input terminal of the flip-flop FF4 to change its level. Next, the operation of this embodiment will be explained.

FIG. 2 is a timing diagram of each part signal to explain the operation of this embodiment. First, when the input signals DI1 and DI are both input normally, the D-flip-flop FF, (hereinafter simply FF
3, the same goes for the others) goes from a low level (hereinafter referred to as "L") to a high level (hereinafter referred to as "H").
After the level of Q changes from "H" to "S", FF. Since the output Q of F, that is, the second selection control signal SC2 changes from "L" to "H", the output of gate circuit G4 remains "H".
The output Q of F5 remains "H", the output of the gate circuit G remains "L", and the input signal DI. is not input, and the counter 41 does not perform a counting operation. Therefore, no pulse signal is output from the switching control circuit 4, and the selection control circuit 1.2 and the switching circuit 3 operate in the same manner as in the prior art. Next, the output signal D. from input signal DI2 to input signal DI
．． , and if the input signal DI2 stops coming midway through, first change the selection switching signal SEL from "H" to "L".
At the first falling edge of the input signal DIs after the input signal DI becomes ”, the output Q of the FF becomes “L”, and the input signal DI
．． At the next falling edge of , the output Q of FF becomes "L". At the falling edge of the output Q of this FF, the output of the gate circuit G4 becomes "L", and the input signal DI. At the next falling edge of , the output Q of the FF becomes "L I1." While the output Q of the FF is "L", the input signal DI is output from the gate circuit G5. When 16 rising edges of the input signal DIt are input to the counter 41, the carry output CA of the counter 41 outputs a pulse signal that becomes "H", and at the falling edge of this pulse signal, the output Q of FFa, that is, selection control. The signal S C 2 is “L”
”, and the output Q of FF4, which is outputting a signal to the set terminal S of FF2, changes from “L” to “H”. Therefore, the output of gate circuit G2 becomes “L”, and the input signal DI from gate circuit G1 changes from “L” to “H”. That is, when the selection switching signal SEL becomes "L" and the input signal DI2 does not come, the selection switching signal (SQL) is output.
Counting after the level of input signal DI. When three are detected, the reset state of the counter 41 is released,
From this point on, the input signal DI. When 16 rising edges of G. are detected, the gate circuit G. , e2 become inactive and active, respectively, and the input signal DI1 is output as the output signal Do. Therefore, even if the input signal DI2 stops coming midway through, the input signal OI. The input signal can be switched by using the rising edge of . FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

This second embodiment changes the gate circuit G4 of the switching control circuit 4 in the first embodiment from the NAND type to the EXCLUS type.
It has been changed to an IVE-OR type. FIGS. 4 and 5 are timing diagrams of signals of each part to explain the operation of this second embodiment. In FIG. 4, the selection switching signal SEL changes from "L" to "H" to "
An example is shown in which the input signal DI2 does not come when the input signal DI2 changes from "H" to "L". In FIG. 5, the selection switching signal SEL changes from "H" to "L" to "L". H” and “
An example is shown in which the input signal D I z does not come when the selection change signal changes from "L" to "H". If the switching operation is not performed even after a predetermined period of time has elapsed since then, a pulse signal is generated to perform the switching operation, thereby ensuring the switching operation even if one of the input signals stops coming. There is an effect that can be done.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is a timing diagram of signals of each part to explain the operation of the embodiment shown in FIG. 1, and FIG. A circuit diagram showing the second embodiment, FIGS. 4 and 5 are timing diagrams of signals of each part to explain the operation of the embodiment shown in FIG.
The figure is a circuit diagram showing an example of a conventional data selection circuit, and FIG. 7 is a timing diagram of various signals for explaining the operation of the data selection circuit shown in FIG. 6. 1, 2... Selection control circuit, 3... Switching circuit, 4, 4A... Switching control circuit, F Fl ~FF,... D-flip-flop, G. ~G7...Gate circuit, ■1 ■5...Inverter.

Claims (1)

[Claims] a first flip-flop circuit that shifts a selection switching signal by a predetermined time using a first input signal as a sampling clock; and a second selection control signal that maintains an inactive level when the second selection control signal is at an active level; A first selection control signal that shifts the output signal of the first flip-flop circuit by a predetermined time using the first input signal as a sampling clock when the signal is at an inactive level, and outputs a first selection control signal having an inverted level. a first selection control circuit comprising two flip-flop circuits; and a third flip-flop circuit that shifts the output signal of the first flip-flop circuit by a predetermined time using the first input signal as a sampling clock. and a fourth flip-flop circuit that shifts the output signal of the third flip-flop circuit by a predetermined time using the second input signal as a sampling clock and outputs the shifted signal as the second selection control signal. a switching circuit that selects and outputs one of the first and second input signals according to the first and second selection control signals; and an output signal of the third flip-flop circuit; and a switching control circuit that generates a pulse signal to change the level of the second selection control signal when there is no change in the level of the second selection control signal for a predetermined period of time after a level change occurs. data selection circuit.