JPH0535613A - Runaway preventing circuit for microcomputer - Google Patents

Abstract

PURPOSE:To prevent a runaway even if the fluctuation of a power supply voltage, etc., is generated. CONSTITUTION:A first program counter 1 for designating the address of a memory 5 is provided, a second program counter 2 for outputting a counted value being always more by N than that of a first program counter 1 is provided, a selector 3 for selecting and outputting alternately the outputs of the first and the second program counters 1, 2 is provided, an address register for decoding the output of the selector 3 and setting it as the address input of a memory 5 is provided, so that the memory outputs data by the value of the address register, a first instruction latch 7 for latching the output of the memory 5 conforming to the value of a first program 1 in the outputs of the memory is provided, a second instruction latch 6 for latching the output of the memory 5 conforming to the value of a second program counter 2 and constituting a shift register of N stages is provided, and a comparator for comparing the values of a first instruction latch 7 with a second instruction latch 6 is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a runaway prevention circuit for a microcomputer, and more particularly to a read only memory (R).
The present invention relates to a circuit for preventing runaway due to misreading of OM data.

[0002]

2. Description of the Related Art As shown in FIG. 4, a conventional microcomputer has a program counter 1 for designating an address of a memory (ROM) 5 and an address decoder (DEC) for inputting and decoding the output of the program counter 1.
4 and a memory (ROM) 5 for outputting instruction data in accordance with the address decoded by the address decoder 4.
And the data of the memory (ROM) 5 with the clock pulse (C
The instruction latch 7 latches at the timing K1) and outputs data to the instruction decoder 4.

Next, the operation will be described with reference to FIG. First, the program counter 1 (PC1) outputs an address for reading the memory (ROM) 5. This address is decoded by the decoder (DEC) 4 and input to the memory (ROM) 5. In this memory (ROM) 5, the precharge signal (PR
E) After the end, data according to the address is output.

Next, the instruction latch 7 latches the data in the memory (ROM) 5 at the timing of CK1 and outputs it to the instruction decoder 4.

Therefore, in the conventional configuration, the data is dynamically held until the instruction latch 7 latches it at the timing of CK1 after the end of the precharge signal (PRE).

[0006]

The configuration of the conventional microcomputer has the following drawbacks because the output of the memory (ROM) 5 is latched only once and the instruction is decoded.

This will be described with reference to the timing chart of FIG. 5. In a conventional microcomputer using the dynamic ROM 14, the precharge signal (PRE) becomes "L" after the address (PC1) is determined. When the precharge is completed, the output according to the address is output from the memory 5.

The output of this memory 5 is C by an instruction latch 7.
Latch at the timing of K1. Therefore, after the precharge is completed, it is dynamically held during the latch clock (CK1) of the instruction latch 7.

Therefore, if the power supply voltage fluctuates or the like during the dynamic holding, the data changes and the wrong data is latched. Due to this, an instruction different from the expected instruction was executed, causing a runaway.

An object of the present invention is to solve the above-mentioned problems and to provide a runaway prevention circuit for a microcomputer which prevents runaway even if a change in power supply voltage occurs.

[0011]

The runaway prevention circuit of the present invention has a first instruction latch for latching the contents of the memory output at the first time and the contents of the memory output for the second time. A second instruction latch for latching the
The values of the second instruction latch are compared with each other, and the instruction is executed only when the values match.

[0012]

1 is a block diagram showing a runaway prevention circuit for a microcomputer according to a first embodiment of the present invention.

FIG. 3 is a timing diagram showing the operation of FIG.

In FIG. 1, the runaway prevention circuit of the present embodiment comprises a memory (ROM) 5, a decoder (DEC) 4,
Selector (SEL) 3 and program counters 1 and 2
, Instruction latches 6 and 7, and a comparator 8.

That is, the configuration of the runaway prevention circuit of the microcomputer of the present embodiment is the first one for designating the address of the memory 5 in the runaway prevention circuit of the microcomputer using the dynamic holding type read only memory 5. Program counter 1 and a second program counter 1 that constantly outputs a count value larger than the first program counter 1 by N.
Program counter 2 and a selector 3 which alternately selects and outputs the outputs of the first and second program counters 1 and 2, and an output of the selector 3 is decoded and used as an address input of the memory 5. An address register, the memory outputs data according to the value of the address register, and the memory 5 according to the value of the first program counter 1 among the outputs of the memory.
A first instruction latch 7 for latching the output of the memory 5 and a second instruction latch 6 for latching the output of the memory 5 according to the value of the second program counter 2 and forming an N-stage shift register; And a comparator 8 for comparing the values of the first and second instruction latches 7 and 6, and the instruction is executed only when the outputs of the comparator 8 match.

1 and 2, the runaway prevention circuit according to the present embodiment has a program counter 1 and a program counter 2.
However, it counts at the same cycle as the instruction execution cycle,
In addition, the program counter 2 counts a value that is two counts more than the program counter 1. Further, the program counter 2 is out of phase with the program counter 1 by 1/2 cycle.

The outputs of the program counters 1 and 2 are alternately selected by the selector 3.

The output of the selector 3 is decoded by the decoder 4 and input to the memory (ROM) 5 as an address. Therefore, the memory 5 reads data at twice the speed of the instruction execution cycle.

As for the output of the memory 5, the data according to the program counter 1 is latched in the instruction latch 7 by the clock of CK1, and the data according to the program counter 2 is latched in the instruction latch 6 by the clock of CK2. . Here, the instruction latch 6 is composed of two stages of shift registers, and the previous data is output to the output.

Next, the comparator 8 compares the data in the instruction latch 6 and the instruction latch 7 at the timing of STB.

The instruction is executed only when the comparison results match.

However, immediately after the value of the program counter is switched due to a jump or an interrupt, the data in the instruction latch 6 is old, so that the instruction is executed without making a comparison.

FIG. 2 is a block diagram showing a runaway prevention circuit for a microcomputer according to a second embodiment of the present invention.

In FIG. 2, the runaway prevention circuit of this embodiment is provided with a memory (ROM) 5, a decoder 4, and an adder 9.
, A program counter 1, instruction latches 6 and 7, and a comparator 8.

In FIG. 2, the present embodiment uses only one program counter 1 instead of using two program counters in FIG. 1, and thereafter uses an adder 9 instead of the selector 3, The program counter 1 and a counter that is two more than that are counted. Others are the same as the description of FIG. 1 described above.

Further, in FIGS. 1 and 2, when the comparator 8 outputs a mismatch signal, it is possible to judge that a runaway has occurred and reset the system.

[0027]

As described above, according to the present invention, the reading from the memory is performed twice at different timings, the values are compared, and the instruction is executed only when the values match. Even if the data in the memory changes due to fluctuations and the wrong data is latched, the probability that the same data will be changed twice at different timings will be very low, and the instruction will be executed as it is and there will be no runaway. is there.

[Brief description of drawings]

FIG. 1 is a block diagram showing a runaway prevention circuit of a microcomputer according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a runaway prevention circuit of a microcomputer according to a second embodiment of the present invention.

FIG. 3 is a timing chart showing signal waveforms in various parts of the embodiment shown in FIG.

FIG. 4 is a block diagram showing a conventional runaway prevention circuit.

5 is a timing diagram showing signal waveforms of the circuit shown in FIG.

[Explanation of symbols]

 1, 2 Program counter 3 Selector 4 Decoder 5 Read-only memory (ROM) 6, 7 Instruction latch 8 Comparator 9 Adder

Claims (1)

Claim: What is claimed is: 1. A first instruction latch for latching the contents of the memory output at the first time, and a second instruction latch for latching the contents of the memory output at the second time. And the values of the first and second instruction latches are compared with each other, and the instruction is executed only when the values match each other.