JPH05120005A - Processor having repeat instruction of preceding instruction - Google Patents

Abstract

PURPOSE:To provide a processor having the repeat instruction of a preceding instruction, which can be executed without inserting a wasteful cycle at the time of operating the operating repeat instruction. CONSTITUTION:A processor having a decoder 700 inputting and decoding instruction data and outputting it, and a storage part 100 inputting and storing the output of the decoder 700 is provided with a control part 180 outputting a control signal for repeatedly outputting prescribed instruction data which is former than n-th data for the prescribed number of times when the decoder 700 decodes that n-th instruction data is the repeat instruction. When the decoder 700 decodes that n-th instruction data is the repeat instruction, the storage part 100 substitutes n-th instruction data with prescribed instruction data which is former than n-th data, and repeatedly outputs prescribed instruction data former as than n-th data for prescribed number of times.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor having a repeat instruction of a previous instruction.

In a processor operating in one instruction / clock cycle, when the same instruction is executed continuously, generally, there is a meaning of saving the instruction memory instead of describing the instruction by the number of times of repetition. Supports repeat instructions that only repeat.

In this case, there is a demand for a processor that can execute a repeat instruction without inserting a wasteful cycle.

[0004]

2. Description of the Related Art FIG. 6 is a block diagram showing the configuration of a conventional circuit. FIG. 7 is a diagram for explaining the operation of the conventional example.

In FIG. 6, reference numeral 1 denotes an adder for adding +1 each time the output of a program counter (hereinafter referred to as PC) 3 is input, and outputting the same.
In (2), the output (count number) of the adder 1 is selected and temporarily stored in the PC 3 in addition to the PC 3, and then the count number is output as a signal indicating the address of the instruction memory 4. In the instruction memory 4, the data stored at this address is read and output by the address signal from the PC 3.

In the SEL 5, normally, the data input from the above-mentioned instruction memory 4 is selected and output and added to the instruction register (hereinafter referred to as IR) 6. I
At R6, the data normally input from the instruction memory 4 via the SEL 5 is temporarily stored. Then, in the decoder 7, I
The data temporarily stored in R6 is read and input, and the content of this data is decoded.

In the IR 10, normally, the contents (data) decoded by the decoder 7 are read out, input through the SEL 9 and temporarily stored. Then, the data temporarily stored in the IR 10 is read out and sent as an execution command to a circuit in the subsequent stage, for example, a gate control unit (not shown).

Now, in the decoder 7, as shown in FIG.
When the data (n) corresponding to the count number of 3 is n is a repeat instruction and the number indicated by a repeat counter (hereinafter referred to as RPC, not shown), for example, decoding of repeating three (n + 1) instructions is decoded, The repeat command (REP) is output from the decoder 7, and SEL2, SEL5 and SE are output.
Add to L9.

At this time, the clock cycle is n + 2 in PC3, and the repeat instruction (R
When (EP) is input, the input of SEL2 is switched to the (a) side, and is temporarily stopped at the stage of n + 2 so that the output of PC3 does not proceed. That is, the output (count number) of PC3 is fed back via SEL2 and added to PC3 again, and this feedback operation is repeated by a repeat command (REP).
Repeat until the end (in this case, for example, 3 times). This is shown in FIG. 7 (1).

Similarly for SEL5, input SEL5 (a)
By switching to the side, the (n + 1) data output from the IR6 is fed back through the SEL5, added to the IR6 again, and the (n + 1) data is output three times (in this case) repeatedly. This is shown in FIG. 7 (2).

At this time, the IR10 temporarily stores the repeat command (REP) of (n), and even if the repeat command (REP) of (n) is sent to the circuit (not shown) in the subsequent stage, the content to be executed remains. Therefore, the SEL 9 is switched to the (b) side and a signal indicating no processing ('NOP') 8 is added to the IR 10. Then, in the next three consecutive clock cycles, (n +
Repeatedly input the data of 1) three times and temporarily store it.
The program command is sent to a circuit in the subsequent stage, for example, a gate control unit (not shown) or the like to execute the program command. (N + 1)
After the data of No. has been repeated three times, the normal command data is returned and the data of (n + 2), (n + 3), ... Are input / output.

On the other hand, in the RPC (not shown), each time the decoder 7 decodes (n + 1) data and outputs it, the count number is decremented by 1, and when the count number becomes 1, the repeat instruction (n) ( REP) output is stopped. When the output of this repeat command (REP) is stopped, SEL
In 2 and 5, the input is switched from (a) side to (b) side, and SE
At L9, the (b) side is switched to the (a) side so that normal data transfer is performed. This is shown in FIGS. 7 (3) and 7 (4).

[0013]

However, in the circuit described above, when the decoder 7 decodes the repeat instruction, the instruction following the repeat instruction is repeated, so that the repeat instruction is not processed (NOP) at the time of executing the instruction, which is wasteful. There was a problem that an execution cycle could be created.

Therefore, an object of the present invention is to provide a processor having a repeat instruction of a previous instruction which can be executed without inserting a wasteful cycle when the repeat instruction operates.

[0015]

The above problems can be solved by the structure of the circuit shown in FIG. That is, in FIG. 1, a decoder 700 that inputs command data, decodes it, and then outputs it
And the storage unit 100 that receives and stores the output of the decoder 700.
In the processor having and 180 is a decoder 700
When it is decoded that the nth instruction data is an instruction to repeat, the control unit that outputs a control signal for repeatedly outputting the predetermined instruction data before the nth from the storage unit 100 a predetermined number of times. is there.

When the decoder 700 decodes that the n-th instruction data is an instruction to repeat,
The control signal output from the control unit 180 replaces the nth instruction data in the storage unit 100 with the predetermined instruction data before the nth, and repeatedly outputs the predetermined instruction data before the nth a predetermined number of times. To configure.

[0017]

In FIG. 1, when the decoder 700 decodes that the nth instruction data is a repetitive instruction instructing to repeat the (n-1) th instruction data,
The control signal output from the control unit 180 replaces the n-th instruction data with the (n-1) -th predetermined instruction data in the storage unit 100, and (n
The -1) th instruction data is read from the storage unit 100 and output.

When the number of times of repeat instruction is m,
The remaining (m-1) th instruction data is read from the storage unit 100 and output. As a result, the instruction data can be executed without inserting a wasteful cycle during the operation of the repeated instruction.

[0019]

FIG. 2 is a block diagram showing a circuit configuration of an embodiment of the present invention. FIG. 3 is a block diagram showing the configuration of the SEL control circuit of the embodiment.

FIG. 4 is a view (No. 1) for explaining the operation of the embodiment. FIG. 5 is a diagram (part 2) for explaining the operation of the embodiment. The same reference numerals denote the same objects throughout the drawings.

In FIG. 2, when the decoder 7 decodes data other than the repeat instruction, the circuit operation is the same as that described in the prior art, and therefore the description thereof is omitted.

Next, when the decoder 7 decodes that the nth data, that is, the data (n) is a repeat instruction,
A repeat command (REP) is output from the decoder 7 and applied to the set terminal (S) of the SR flip-flop circuit (hereinafter referred to as SR-FF) 16 of the SEL control circuit 18 shown in FIG. If the repeat instruction count is 3, for example, this repeat count 3 is set in the RPC 13.

Then, in the comparing section 15 shown in FIG.
Compare the output of and the number '1'. Since the output of RPC13 is (in this case) first "3" and they are not equal,
The comparison unit 15 outputs "0". (When the output of the RPC 13 becomes "1", they become equal, and the comparing unit 15 outputs "1"). (This output is called COMP). The output (COMP) of the comparison section 15 is added to the SEL control section 17 which will be described later, and is also added to the reset (R) terminal of the SR-FF 16 described above.

Then, the output (EXREP
(1) is output (see Table 1). The output of the comparator 15 (COMP) and the output of the SR-FF16 (EX
REP) is added to the SEL control unit 17, and the SEL control unit 17
The logical operation as shown in (a), (b) or (a) to (c) of is performed. SEL2, SEL of the outputs obtained by the logical operation in the SEL control unit 17
5, add to SEL9 and SEL12.

[0025]

[Table 1]

[0026]

[Table 2]

In Table 2, for example (a), that is, EXRE
When performing the logical operation of P ・ (Inv) COMP, EX
REP is '1' and COMP is '0', so COMP is reversed (I
nv) COMP becomes '1', which is the logical product of both, EXREP
(Inv) COMP = '1'. Also, in (b), (Inv) {EX
REP. (Inv) COMP} is an inversion of the above (a), and therefore becomes “0”.

(A), (b) or (a), (b), (c) of
Among these, only one is "1", and the input of SEL corresponding to the operation result of "1" is set to be selected. In the case described above, since (a) is "1" and (b) is "0", the SEL2 shown in FIG.
(a) Select the input by switching. As a result, in the next clock cycle, the PC3 outputs the count number of (n + 2) by the feedback loop via the (a) input of the SEL2. This is shown in (1) of FIG.

Further, since (a) and (b) in Table 2 are set by the same logical operation formulas as (a) and (b) described above,
The SEL5 also selects and selects the (a) input, and the IR6 outputs (n + 1) data by the feedback loop via the (a) input of the SEL5 in the next clock cycle. This is shown in (2) of FIG.

Next, in the case of Table 2, (a) is as described above.
Since it is set by the same logical operation formula as (a), (a) becomes '1' and SEL9 also selects (a) input by switching.
Then, in the IR10, for example, the instruction data of one clock cycle before the instruction data (n), that is, the instruction data of (n-1) is read and output, and the feedback loop via the (a) input of SEL9 Re-input the data of -1) into IR10 and store it. Then, even in the next clock cycle, the (n-1) instruction data is read and output. This is shown in (3) of FIG. The output of IR10 is sent to a circuit such as a gate control unit (not shown) in the subsequent stage.

For reference, (b) in Table 2, that is, (I
nv) {EXREP. (Inv) COMP + REP.COMP} logical operation, in this case (RPC = 3), from Table 1, EXREP is '1', COMP is '0', and REP is decoder 7 Becomes "1" only for the first clock cycle when the command repeatedly decodes (Inv) {EXREP ・ (Inv) COMP + REP ・ COMP}
Will be '0'. In addition, (c) in Table 2, that is, REP COMP
Similarly becomes "0".

Next, (a) in Table 1, that is, (REP + EXREP)
・ When the logical operation of (Inv) (COMP) is performed, the EXR
Since EP is "1" and COMP is "0", COMP is inverted (In
v) COMP becomes '1'. REP is '1' only for the first clock cycle when the decoder 7 decodes the repeated instruction.
Therefore, after all, (REP + EXREP) ・ (Inv) (COMP) ＝
It becomes "1". In addition, (b) of the above is "0" because it is the inversion of the above (a). With this output signal, the SEL 12 shown in FIG. 3 switches and selects (1) input which is "1".

As a result, the value ('2') obtained by subtracting '1' from the output value ('3') of the RPC 13 by the subtracter 11 shown in FIG. 3 is S.
Since it is added to RPC13 via EL12, RPC13 outputs "2" in the next clock cycle and the comparator
Add to 15. The comparator 15 compares the input "2" with a preset value "1", but since the two are not equal, the comparator 15
SR-F outputs "0" as output (COMP) from 15
Add to the R terminal of F16. In the SR-FF16, since COMP'0 'is input, the next clock cycle (output of RPC =
In 2), "1" is output as (EXREP). (See Table 1).

The above-mentioned COMP and EXREP are connected to the SEL control unit 17
In addition to the above, the SEL control unit 17 performs the logical operations of to in Table 2 in the same manner as described above. In this case, as shown in Table 1, when the output of RPC13 = 2, the values of COMP and EXREP are RPC.
Since the output of 13 is the same as when 3 = RPC13
In the same way as when the output of = 3, all of (a) are "1". As a result, SEL2, 5, 9, and 12 switch and select (a) input.

As a result, the PC 3 outputs an n + 2 address signal and the IR 6 outputs (n + 1) data. Also, IR
10 reads (n-1) data and outputs it, and adds it to a circuit (not shown) in the subsequent stage (see FIG. 4).

Next, in the SEL12 shown in FIG. 3, since (a) input is switched and selected, in the next clock cycle, R
Value obtained by subtracting "1" from subtracter 11 from the output ('2') of PC13
('1') is added to the RPC 13 via the SEL 12, and this value ('1') is output from the RPC 13 to the comparison unit 15. Comparison section 1
At 5, the input ('1') from the RPC 13 is compared with the preset value '1', and since they are equal, '1' is output as COMP. (See Table 1).

This COMP output and the output of the decoder 7 (RE
When the output of P and RPC13 is "2" and "1", REP
= '0') is added to SR-FF16,
As shown in Table 1, SR-FF16 outputs "0" as EXREP. The EXREP value and the COMP value are added to the SEL control unit 17, and the SEL control unit 17 performs the logical operation shown in Table 2 to.

In Table 2, (a), that is, EXREP. (I
nv) COMP is "0" when the output of RPC13 = "1" as described above, and (Inv) COMP is "0" because COMP is "1", and EXREP ・ (Inv) COMP is "0". 'Becomes. Therefore, (a) is inverted to (b), that is, (Inv) {EXREP
・ (Inv) COMP} becomes '1'.

As a result, the SE signal shown in FIG.
L2 selects (b) input to switch to normal operation.
That is, the output (n + 2 address signal) of PC3 is added with "1" by the adder 1 and the value (n
+3) is output and stored in addition to the instruction memory 4. (See (1) in FIG. 4).

Since (a) and (b) in (1) and (b) are the same logical operation expressions as in (a) and (b), respectively, (b) becomes "1", and the signal of FIG. SEL5 shown in
Also (b) Selects the input by switching and returns to normal operation. That is, the (n + 2) data stored in the instruction memory 4 one clock cycle before is read and added to the IR 6 via the SEL 5. (See (2) in FIG. 4).

Since (a) in (a) is the same as (a) above, (a) becomes "0". Next, in (b), that is,
(Inv) {EXREP. (Inv) COMP + REP.COMP} is '1' because EXREP and REP are '0' and COMP is '1' as described above. As a result, SEL9
(B) Selects the input and returns to normal operation. That is,
In the decoder 7, the instruction data (n next to the repeat instruction (n)
The output obtained by decoding +1) is I through SEL9.
Input to R10 and memorize. Then, at the next clock cycle, (n + 1) instruction data is read out and added to the circuit (not shown) in the subsequent stage to be executed. (See (3) in Figure 4).

In addition, (a) in Table 2, that is, (REP + EXREP).
(Inv) COMP is "0" for REP and EXREP as described above, CO
Since MP is "1", it becomes "0". For this reason, (b) which is the reverse of (a) becomes '1'. Therefore, the SEL12 shown in FIG. 3 switches and selects the input (b) by the signal of and returns to the normal operation.

The instruction data (n-1) repeated by the above-mentioned repeat instruction may be either a single instruction data or a plurality of instruction data. As a result, the instruction data can be executed without inserting a wasteful cycle during the operation of the repeat instruction, and the processor can perform higher-speed processing.

When the decoder 7 shown in FIG. 2 decodes the repeat instruction and the number of repetitions (instructions) is one,
In Table 2 (a), that is, EXREP. (Inv) COMP is "0" because EXREP is "0" and COMP is "1" from Table 1. Therefore, (b) in which (a) is inverted becomes '1'. As a result, and the signals of and, SEL2 and S
EL5 performs the normal operation by (b) switching and selecting the input.

Further, in (b), that is, (Inv) {EXREP. (In
v) COMP + REP · COMP} is '0' because EXREP is '0', COMP is '1', and REP is '1' only in the first clock cycle when the decoder 7 decodes the repeat instruction.
Becomes (C), that is, REP / COMP becomes '1'.
As a result, the SEL 9 switches (c) the input by the signal of, and selects the signal representing the no processing ('NOP') 8 by IR10.
To be added to In this case, IR10 outputs a signal of no processing ('NOP') for one clock cycle. (See Figure 5).

For reference, when the logical operation of Table 2 is performed, (a), that is, (REP + EXREP). (Inv) COMP becomes "0" when the above-mentioned value is used. Therefore, of (a)
(B) that is the reverse of, that is, (Inv) {(REP + EXREP) ・ (In
v) COMP} becomes '1'. Therefore, the SEL 12 switches and selects the input (b) by the signal of, and continues the normal operation.

[0047]

As described above, according to the present invention, it is possible to execute instruction data without inserting a wasteful cycle during the operation of a repetitive instruction, and it is possible to perform higher speed processing in a processor. Become.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention,

FIG. 2 is a block diagram showing a circuit configuration of an embodiment of the present invention,

FIG. 3 is a block diagram showing a configuration of a SEL control circuit according to an embodiment,

FIG. 4 is a diagram (part 1) for explaining the operation of the embodiment;

FIG. 5 is a diagram (part 2) for explaining the operation of the embodiment;

FIG. 6 is a block diagram showing a circuit configuration of a conventional example,

FIG. 7 is a diagram for explaining the operation of the conventional example.

[Explanation of symbols]

 100 is a storage unit, 180 is a control unit, and 700 is a decoder.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Hiroki Ichimura 3-28-1 Joto, Oyama-shi, Tochigi Prefecture Fujitsu Digital Technology Limited (72) Tatsuya Nagasawa 3-28-1 Joto, Oyama-shi, Tochigi Prefecture Issue within Fujitsu Digital Technology Limited

Claims (1)

[Claims] 1. A decoder having a decoder (700) for inputting and decoding instruction data and outputting the decoded data, and a storage section (100) for inputting and storing the output of the decoder (700). ), When decoding that the n-th instruction data is an instruction to repeat, it outputs a control signal for repeatedly outputting the predetermined instruction data before the n-th instruction from the storage unit (100) a predetermined number of times. Output control unit (180)
When the decoder (700) decodes that the n-th instruction data is an instruction to repeat, the control unit (180)
By the control signal of the output of
A repeat command of a previous command, characterized in that the predetermined command data before the n-th is replaced with the predetermined command data before the n-th, and the predetermined command data before the n-th is repeatedly output a predetermined number of times. A processor with.