JPS58142447A - Data processor - Google Patents

Abstract

PURPOSE:To attain the stage of a preceding controller efficiently, by performing smoothly the conflict control relating to addresses of a preceding storage system instruction and a succeeding instruction. CONSTITUTION:From the type of an instruction from a signal line 114 and an operand length from a signal line 104, the memory access length of the respective types is produced at a length producing circuit 6 in an instruction code of a decoder 5. A memory access length produced in this circuit 6 is inputted to one input of a 4-input address adder 7 via a signal line 109. The other inputs of the adder 7 are the same as those of a 3-input adder 3, and the output of the adder 7 is inputted to an operand storage conflict OSC detection circuit 4 and transmitted to a stage control circuit 8 via a signal line 111. This circuit 8 performs the control of stage progress and suppression depending on the state of each stage.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device that performs advanced proactive control, and particularly to a proactive control device that smoothly performs conflict control regarding the addresses of a preceding store-related instruction and a subsequent instruction.

BACKGROUND OF THE INVENTION Generally, in data processing apparatuses that perform advance control, instructions are processed in several steps. For example, the command is (1)
Decode stage (hereinafter abbreviated as M and D stages) that reads instructions, decodes them, and calculates operand addresses.
, +2) Association stage (hereinafter abbreviated as LA stage) that continuously outputs operands, (3) Load stage (hereinafter abbreviated as L stage) that transfers operands, (4) Execution stage that executes instructions. The processing is divided into four stages, such as the processing stage (hereinafter abbreviated as E stage).

On the other hand, in a data processing device that has a dedicated preceding control unit, the preceding control unit processes instructions, decoding, calculation of operand addresses, and successive operands, and performs operations such as addition, subtraction, multiplication, division, store, and load operations. The actual calculation is performed by the arithmetic unit.

That is, as described above, the advance control device is involved in the A and L stages, and the arithmetic unit is involved in the E stage. In this case, the normal instruction processing stages 70.-- are as shown in FIG. 1, and are controlled so that each instruction A, B, C, . . . is effectively processed in one cycle.

FIG. 2(a) shows a normal instruction processing stage flow when a store instruction ST and a load instruction are consecutive. Now consider the case where the 8T instruction and the L instruction access the same address in the storage device t, as shown in Fig. 2 f+. Fig. 2 (c)
In the figure, the shaded portions of the 2nd to 6th bytes indicate data that is rearranged by the ST instruction, and the shaded portions of the 4th to 7th bytes indicate data that is successively output by the L instruction. As shown in FIG. 2(a), a request to store the store instruction 8T to the storage device is issued at the E stage, but a request for successive operands for the load instruction is issued at the D stage by the preceding control device. In other words, when the ST instruction and the L instruction are consecutive, the load instruction successively outputs the operands that were not replaced by the preceding store instruction ST and loads the contents of the storage device into the general-purpose register, and the L instruction is executed correctly. Not done. For this reason, conventionally, in data processing devices that have advance control, the match/mismatch between the store address of the preceding store-related instruction and the operand continuation address of the subsequent instruction has been detected (Opera
detecting rutE3torm Conflict (hereinafter abbreviated as OSC) and controlling the stage of the preceding control device;
It ensures that the command is processed correctly. FIG. 2(b) shows the instruction processing stage flow in this case.

However, the conventional processing device detects the O20 detection range only within the basic unit boundary (for example, 8-byte boundary) of the device, and therefore does not cover the basic unit boundary. Therefore, as shown in Figure 8 (←), when S,\door data is stored across the basic unit boundary, it is assumed that O20 occurs, and as shown in Figure 8 (A), The preceding control device was always reset, and the overlap of each stage of the preceding control was stopped to process instructions. Therefore, an instruction that successively outputs operands following a store instruction must be executed after reading the instruction, which is a factor that significantly degrades performance.

OBJECT OF THE INVENTION An object of the present invention is to eliminate the above-mentioned problems, and to provide a data processing device having a proactive control device that performs advanced proactive control, without resetting the advance control device and from reading an instruction. There is no opening (08C)
The object of the present invention is to detect and smoothly control the stage of the preceding control device based on the detection result.

For the purpose described above, in the present invention, the preceding control device is provided with an instruction/guess generation circuit specific to an instruction that accesses memory and a circuit that generates the last address of the memory to be accessed, and a circuit that generates the last address of the operand of the subsequent instruction. It is determined accurately whether or not nt is within the range that can be obtained by the preceding store instruction, thereby smoothly controlling the stages of the preceding control device.

Examples of the invention Hereinafter, one embodiment of the present invention will be explained in detail.

FIG. 4 is a block diagram of one embodiment of the present invention.

In FIG. 4, an instruction buffer register (not shown)
The instruction extracted from is set in the instruction register l. 101 is the signal line on which the instruction code is carried, 102 is the signal L on which the index register address is carried, 10B is the signal line on which the base register address is carried, 104 is the operand length of the SS format instruction, the signal m on which the mask value of the mask instruction is carried, and 105 is the display. This is the signal line on which the component rides. Depending on the type of instruction, the contents of the general-purpose register 2 at the address indicated by the signals k102 and 10B are output one after another, and are input to the eight-person address adder 8 via the signals 5hoe and 1o7 as the contents of the index register and base register, respectively. . The 8-person address adder 8 adds the index register, pace register, and displacement, and sends the result to each address register and O8C detection circuit number via signal line 108.

Next, a feature of the present invention is a length generation circuit for instructions that access memory 6.4 address adder 7, O8C
The detection circuit 4 and the like will be explained.

The decoder 5 decodes the instruction code on the signal line 101,
Information identifying each type of instruction that accesses the memory is input to the instruction-specific length generation circuit 6 via signal #114. The length generation circuit 6 determines the type of instruction input via the signal @114 and the type of instruction input via the signal #104.
- This circuit generates a memory access length specific to each type of instruction based on the operand length and mask information input. Here, the types of instructions include fixed-length memory operand instructions (instructions that process memory operands of a length determined by the instruction, such as 2, 4, and 8 bytes), and variable-length memory operand instructions (88 bytes).
(format instructions, etc.), or mask-based memory operand instructions (instructions that process as many items as tllll+number of masks). The memory access length generated by the length generation circuit 6 is input to one of the four-person address adders 7 via a signal #109. The other eight inputs of the four-person address adder 7 are the same as the eight-person address adder 8. That is, the four-person address adder 7 is provided to generate the last address of an instruction that accesses the memory. The result of the 4-person address adder 7 is input to the O8C detection circuit 4 via the signal line 110, and used together with the result of the 8-person address adder 8 for O8C detection of the instruction following the store instruction. The signal line 111 is a signal line that sends the O8C detection result to the stage control circuit 8, and the stage control circuit 8 controls the advancement and inhibition of stages depending on the state of each stage.

Figure 5 shows the O8C detection circuit 4 in more detail.
It is a table diagram. Registers 20, 21 and 22 are registers that hold the results of the 8-person address adder 8 corresponding to each stage, and 0 means the stage. Registers 80, 81 and 82 are registers that hold the results of the 1-person address adder 7 corresponding to each stage, where 0 indicates the stage and L.

L', L' means length. Comparator 40.60
゜60 and? 0 is a circuit that compares the operand successive address of the instruction in the D stage and the write address of the instruction in the A stage, and similarly comparators 41, 51, 61
and 71 are circuits that compare the operand read address of the instruction in the D stage and the write address of the instruction in the L stage. That is, the comparator 40 compares (D) and (A
), the comparator 41 compares (D) and (L), and compares! 60n (D) ((A)+I; )
G17) Size ratio! , the comparison a51 compares the magnitude of (D) and ((L) 10, and the comparator 60 compares ((D)+L) and ((A
)), comparator 61 compares ((D)+L) and ((L)), comparator 70 compares ((D)+L)
Comparing the size of and ((A) half white, the comparator 71 is ((D) +
This is a circuit for detecting a comparison in magnitude between L) and ((L)+B).

Here, () indicates the contents of each register. Comparator 40.
50, 60.70 are input to the magnitude comparison logic circuit 80 via signal lines 401, 402, 408, 404, and similarly, the detection results of comparators 41, 51, 61.71 are input to signal #i! 405.406.40? , 408
is input to another magnitude comparison logic circuit 81.

The magnitude comparison logic circuit 80 is a circuit that determines the magnitude relationship between the addresses of the D stage and the A stage, and ((A) )<
((D) )<((A) Juhaku or ((A))<((D)+L)<((A) When there is a half-white relationship, that is, a store instruction in the A stage is transferred to the D stage. When destroying an operand of a certain operand successive instruction, the stage control circuit 8 is notified of this via the signal [111.As a result, the stage control circuit 8 uses the D stage VC until the store instruction preceding the certain instruction is completed. Similarly, the magnitude comparison logic circuit 81 is a circuit that determines the magnitude relationship between the addresses of the D stage and the L stage, and ((L))<((D))<((L)+L). Or ((L)) < ((D) + L) < ((L) When the relationship is 10, that is, the store instruction in the L stage is
When destroying the operand of the operand successive instruction in the stage, this fact is transmitted to the stage control circuit 8 via the signal line 111. In this case as well, the stage control circuit 8 causes the instruction in the D stage to wait until the preceding store instruction is completed.

6 is a diagram showing an example of the relationship between memory addresses detected by comparators 40 and 50 in FIG. 5 and instructions, and FIG. 7 is a diagram showing an example of the relationship between memory addresses detected by comparators 60 and 70 in FIG. FIG. 3 is a diagram showing an example of the relationship between commands.

In this embodiment, when the store instruction 8T and the load instruction O8C are detected, the stage is as shown in FIG. 8, and the instructions can be processed without resetting the advance control # device.

In this embodiment, the input/continuation address register is also used, but it is conceivable that the write address register and the continuation address register may be separated to simplify control.

As described in detail, the present invention provides the following effects.

■ Performance is improved because a long store instruction that is stored across a basic unit boundary only inhibits the stages of the advance controller without having to wait from rereading the instruction.

■ Conventionally, advance control was always prohibited for SS format instructions because it was difficult to detect 08C, but in the present invention, precedence control is prohibited only when necessary (the preceding store instruction destroys the operand of the subsequent operand successive instruction). Since this is accurately detected by hardware, it is only necessary to prohibit advance control (only when O8C is detected), which improves performance.

[Brief explanation of the drawing]

Figure 1 shows the normal instruction processing step using advance control.)
Figure 2 is a diagram showing the operation when detecting the match/mismatch between the store address of the preceding store instruction and the operand continuation address of the subsequent load instruction, and Figure 8 is a diagram showing the basic unit boundary. FIG. 4 is a diagram showing a simple embodiment of the present invention, and FIG. 5 is a diagram showing a specific configuration example of the O8C detection circuit in FIG. 4. , FIG. 6 and FIG. 7 are diagrams showing an example of the relationship between memory addresses and instruction sequences, and FIG. 8 is a diagram showing an instruction processing stage 70 according to the present invention. 1...Instruction register, 2...General purpose register, 8...
・8 person address adder, 4...08C detection circuit,
5... Instruction decoder, 6... Memory access length generation circuit, 7... 4-person address adder, 8
...stage control circuit, 20.21.22, 80.
81. H-...address register corresponding to each stage,
40.41゜50, 51.60.61.70.71...
・Comparator, 80.81...m circuit of magnitude comparison theory.

Claims (1)

[Claims] (1) A storage device that stores instructions and data, a pre-control device that outputs instructions one after another from the storage device, performs decoding, calculation of operand addresses, pre-reading of operands, etc., and executes calculations of instructions commanded by the pre-control device. In the data processing device, the preceding control device includes means for inputting the operation code, length, and mask value of the instruction to generate the length of the instruction to access the memory, and a length specific to the generated instruction. means for generating the last address to access memory by;
A data processing device comprising means for detecting a conflict between a preceding store instruction and a subsequent operand successive instruction using said means, and controlling a stage of a preceding control device based on the detection result.