JPS60238934A - Precedence controlling device - Google Patents

Abstract

PURPOSE:To reduce the loss cycle in operand supply, by providing a means which stops the operand supply when a destructive overlap is detected. CONSTITUTION:Operands designated for every instruction by a variable-length operand instruction are supplied in such order as the process at an arithmetic section becomes easier. When the termination of the operand supply of the variable-length operand instruction is detected by a precedence controlling section, the operand supply of the succeeding instruction is immediately executed. When a destructive overlap of operands occurs, the overlap is detected by an overlap detecting means 202 and it is informed to the arithmetic section that the operand supply is disable at the precedence controlling section. As a result, the operand supply can be switched to that of the arithmetic section with a less loss cycle, since the prefetch of the precedence controlling section is stopped.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a pipeline type information processing device, and in particular, it is possible to specify an arbitrary operand length using an instruction word or a register specified by the instruction word. This paper relates to operand prefetching methods for variable-length operand instructions.

(Prior Art) In a conventional advance control device, when an instruction decoder identifies a variable-length operand instruction, the advance control section informs the operation section of the operand length specified by the variable-length operand instruction. Only the first word is supplied regardless, and the arithmetic unit sends a memory request for supplying the remaining operands as necessary. Further, as discussed above, the operand supply for the instruction following the variable-length operand instruction is performed by a start instruction from the arithmetic unit.

Therefore, there is a need to improve the loss cycle between when a memory request is sent from the arithmetic unit and when operand data is returned to the arithmetic unit, and to improve the instruction execution speed in order to determine whether or not it is necessary to supply operands. I didn't like it because of the fact that In addition, by notifying the preceding control section of the end of the variable-length operand instruction, the supply of operands for the subsequent instruction is started, resulting in a loss equal to the number of pipeline stages between the preceding control section and the calculating section. There was a drawback that a cycle occurred.

(Objective of the Invention) An object of the present invention is to provide a variable-length operand instruction to a preceding control device so that operands specified for each instruction are sequentially transmitted for the necessary length in an order that facilitates processing in an arithmetic unit. The preceding control unit detects the end of the operand supply for the variable-length operand instruction and immediately executes the operand supply for the subsequent instruction. If possible, the above-mentioned drawbacks are eliminated by immediately notifying the calculation unit of the above-mentioned impossible state, stopping the preemption of the advance control unit, and making it possible to switch to operand supply to the calculation unit with a few loss cycles. An object of the present invention is to provide a preceding control device configured to effectively supply operands.

(Structure of the Invention) The advance control device according to the present invention is capable of detecting the continuous supply of operands of an instruction to supply operands and the end of the supply of operands of the above-mentioned instructions by multiple memory accesses in pipelined information processing. It is something.

The advance control device according to the present invention includes a duplication detection means, a supply stop means, and a notification means.

The duplication detection means is for detecting destructive duplication of operands.

The supply stop means is for stopping operand supply when a destructive duplication is detected by the duplication detection means.

The notification means is for notifying the arithmetic unit of the detected information.

(real male side) Next, the present invention will be described in detail with reference to the drawings.

3- FIG. 1 is a block diagram of the configuration of an embodiment of the advance control device according to the present invention. In FIG. 1, lot is an instruction register, 110 is an instruction decoding block, 130 is an operand supply start instruction block, and 150.155.156
, 157 , 261. 262 , 263.

264 are registers, 230, 271, 272 are selector circuits, 270 is a counter circuit, 201
202 is an operand address generation circuit, 260 is an operand length read block, and 290 is a branch circuit.

In FIG. 1, an instruction register 101 is a register that holds an instruction to be decoded, and an instruction decoding block 110 develops information necessary for extracting an operand and sends it to a decoding information register group 150. Address generation control information 1
Reference numeral 20 is input from the decoding register group 150 in the first cycle of the operand address generation stage to generate address information, and is control information for the operand address generation circuit 201.

This control information is specified corresponding to instruction code 4- of instruction register 101 and sent to control information register 156.

Operan V supply type instruction information 121 instruction register 1
In the case of a fixed-length operand instruction that is specified corresponding to an instruction code of 01 and requires multiple memory accesses to supply operands, a certain b is an instruction word, or any operand in the register specified by the instruction word. In the case of a variable-length operand instruction that specifies the length, the control information specifies the address generation control procedure from the second cycle of the operand address generation stage and the method of monitoring and controlling the end of operand supply for variable-length instructions. register 15
Sent to 5. The instructions stored in the instruction register 101 are of a fixed length operand instruction type where operand supply ends with one memory access, a fixed length operand instruction type where operand supply ends with multiple memory accesses, and a variable length operand type. It is either - or -. Instruction identification information 122 for identifying the given instruction is stored in the control information register 155.
It is also sent to the start instruction block 130 of the operand generation stage of the subsequent instruction.

Control information for the second cycle and subsequent cycles of the operand address generation stage is given to the memory 250 in advance.

Operand supply type instruction information @121 is instruction identification information 1
When the control information register 155 is set as valid information by 22 and activated, the information given in advance by the predicted control information of the next cycle is set in the control information register 155 and the self-running method is adopted. Operand supply of instructions is continuously controlled. When the end of operand supply is detected, the contents of memory 250 are invalidated and free running is stopped. The contents of the memory 250 are
It is composed of address generation control information for the second cycle and subsequent cycles of the operand address generation stage, control information 251 for the operand address generation circuit 202, and control information 252 for monitoring the end of operand supply of the variable length operand instruction type.

No end detection circuit is used for the end monitoring control information 252,
It also has a function of directly reporting completion to the operand supply start instruction block 130 of the subsequent instruction. The operand address generation circuit 202 is composed of an address generation circuit including registers, and the instruction of the operation mode in the block and the instruction of setting the register can be arbitrarily set by the control information register 261.

When the operand address generation control information 250, O, and termination monitoring control information @252 are valid information, these pieces of information are set in the control information registers 261 and 2fi2, respectively. When the instruction held in the instruction register 101 is identified as being of the variable length operand instruction type by the instruction identification information 122, the instruction word, a certain b, is the operand length specified by the register specified by the instruction word. is read by the operand length read block 260 and set as valid information in the operand length register 263.4 L/'l''17-264. Under the control of the control information register 262, the counter 270 sends out a memory request for operand supply. Each time the operand length register 263.$ or 264 is set, the effective operand length is counted down and the operand length register 263.$ or 264 is repeatedly set to the input selector 271 of the counter 270.
, 272 are provided to arbitrarily set the calculation mode. If the end address of the operand is required, the control information register 261 is used and the contents of the operand length registers 264 and 264 are stored in advance on the signal line 50.
2, operand address generation circuit 20 via 503
2 and hold it.

When the counter 270 detects the end of operand supply according to the instruction of the control information register 262, this detection signal is reported to the subsequent instruction start instruction block 130 via the signal line 501, and the operand address of the subsequent instruction is generated. Used to instruct loading into the stage. The operand supply start instruction block 130 of the subsequent instruction 8- monitors the information of the operand address generation stage, and if the above stage is already vacant or the above stage definitely ends in the above cycle, the instruction A grant indication is issued so that subsequent instructions residing in the decoding stage can proceed to the operand generation stage in the next cycle.

The address information generated by the operand address generation circuits 201 and 202 is selected by the selector 230 and sent to an address exchange section (not shown). When the information in the control information register 261 is valid, the selector 230 selects the operand address generation circuit 202.

When a fixed-length operand instruction that completes operand supply with one memory access is set in the instruction register 101, the information necessary for fetching the operand is developed by the instruction decoding block 110, and the decoding register group 150
will be sent to.

During the cono cycle [b, the address generation control information 120 of the above instruction is read out via the signal line 161, and
2 to the control information register 156. Since the instruction type is identified by the instruction identification information 122, the operand supply type instruction information 121 is invalidated.
A setting instruction for flip-flop 157 is sent via signal line 163.

In the subsequent instruction start instruction block 130, the instruction preceding the above instruction is placed in the operand address generation stage b.
lyh has already ended b, or if the above cycle is reached and the end is certain, a signal instructing the instruction to take in the operand address generation stage of the above instruction is sent via signal lines 164 and 165. Ru. In the next cycle, the information of the above instruction taken into the operand address generation stage by the instructions on the signal lines 164 and 165 is applied to the operand address generation circuit 20 via the signal lines 301 and 302, and is sent to the output signal line 303. It is selected by the output signal selector 230 of and sent to the address conversion section (not shown) via the signal line 310.

In the above cycle, when a subsequent instruction start instruction signal is reported to the subsequent instruction start instruction block 130 via the signal line 304, a signal is sent to the operand address generation stage capture instruction signal lines 164 and 165, and the operand address of the above instruction is The generation stage ends. When a fixed-length operand instruction whose operand supply is completed by multiple memory accesses is set in the instruction register 101, the instruction decoding block 110 expands the information necessary for fetching the operand and sends it to the decoding register group 150. In the cycle fsLx, the address generation control information 120 of the instruction is read out via the signal line 161 and sent to the control information register 156 via the signal line 162. Since the instruction type is identified by the instruction identification information 122, the operand supply type instruction information 121 is sent to the control information register 155 as valid information via the signal line 166.
will be sent to. A reset signal is sent to the flip-flop 157 via the signal line 163 based on the instruction identification information.

11- As already explained, if the instruction to take in the operand address generation stage of the above instruction is sent via the signal lines 164 and 165, the information of the above instruction taken into the operand address generation stage in the next cycle will be transferred to the operand address generation stage. An output signal is sent from the address generation circuit 201 via signal lines 301 and 302, and an output signal on the output signal line 303 is selected by the selector 230 and sent to the address exchange unit (not shown) via the signal line 310. Ru. At the same time, the output signal line 305 of the operand address generation circuit 201
The above output signal is sent to the operand address generation circuit 202. In the above cycle, the control information register 15
With the valid information set to 5, the signal lines 251 and 25
Control information is read from signal lines 306 and 2, respectively.
Control information register 261 via 307 and 308;
262, 155.

In the above command, the counter control information among the termination monitoring control information on the signal line 252 is ignored, and the termination is detected based on the operand supply termination information. In the next cycle, the operand address generation circuit 202 is used to obtain operand address information in response to a control signal sent from the control information register 12-ta 261 via the signal line 309.

At this time, the output signal line 311 is selected by the selector 230, and is sent to the address conversion unit (not shown) via the signal line 310, and is also returned to the operand address generation circuit 202 via the signal line 315. In the next cycle, according to the information set in the control information register 155 via the signal line 308, the signal lines 251, 2
Control information is read out via 52, and the same operation as in the previous cycle is performed. By repeating the above operations, the necessary operands are continuously supplied. During the final operand address generation cycle in the above instruction, operand supply end information is issued from the control information register 262 and transmitted to the subsequent instruction start instruction block 13 via the signal line 312.
0, and the operand address generation stage is added.

Then, an instruction signal is sent on the signal lines 164 and 165, and the information stored in the memory zsoVc in the above cycle is invalidated, and the operand address generation stage of the above instruction is completed. When the variable length operand instruction is set in the instruction register 10, the instruction decoding block 110 expands the information necessary for fetching the operand and sends it to the explanation register group 150. In the above cycle, the address generation control information 120 of the above instruction is read out via the signal line 161 and sent to the control information 1/register 156 via the signal line 162.

As already explained, since the instruction type is identified in the instruction identification information 122, the operand supply type instruction information 12
1 is sent to control register 155 via signal line 166 as valid information. A reset signal for the flip-flop 157 is sent out via the signal line 163 based on the instruction identification information.

The operand length read by the operand length read block 260 is transmitted to the signal line 312 according to the instruction identification information.
, 313 to the operand length registers 263, 264 as valid information. As already explained, when the instruction to take in the operand address generation stage of the above instruction is sent via the signal lines 164 and 165, the information of the above instruction taken into the operand address generation stage in the next cycle is signal line 301,
302 to the operand address generation circuit 201. The output signal line 303 is selected by the selector 230, and its contents are sent to an address converter (not shown) via a signal line 310. At the same time, the output of the operand address generation circuit 201 is also sent to the operand address generation circuit 202 via the signal line 305. In the above cycle, the control information 251 , 252 is read out based on the valid information set in the control information register 155 and sent to the control information registers 261 , 262 , 155 via the signal lines 306 , 307 , 308 . In the next cycle, a control signal is sent from the control information register 61 to the operand address generation circuit 202 via the signal line 309.
2, obtains the operand address information and selects the selector 230.
The output signal line 311 is selected.

15- The output signal of the selector 230 is sent to an address conversion section (not shown) via the signal line 310.

At the same time, this signal is returned to operand address generation circuit 202 via signal line 315. At some point, the control information sent from the control information register 262 is transmitted to the signal line 316.
via selectors 271, 272, counter 270,
and is sent to the operand length registers 263 and 264, and these are controlled to continuously monitor whether or not the operand supply ends.

Since the calculation mode in the counter 270 can be arbitrarily set by the control information register 262,
In this embodiment, the operand supply unit is used as the calculation number, and the point in time when the contents of the counter 270 become zero or negative is the point in time when the end is detected. In this cycle, the control information 251 and 252 are read out via the signal line 308, and the operation is the same as in the previous cycle. By repeating this operation, the necessary operands are continuously supplied. In a specific cycle, when the content of the counter 270 becomes zero or negative and a termination condition is detected, the condition is reported to the subsequent instruction operand supply start instruction block 130 via the signal line 501. , operand address generation stage capture instruction signals 164 and 165 are sent, and the information in the memory 250 in the above cycle is invalidated. This completes the operand address generation stage of the above instruction.

In a variable length operand instruction using two operands, the above method is executed by repeating a specific pattern consisting of supplying the two operands, and the counter 2 flag is set to 0.
If a condition is detected in which the supply of one of the operands ends, the information on the end of the supply of operands on the signal line 312 is used.

The end detection information on the signal line 501 is invalidated. at the same time,
The end detection information 501 activates the branch circuit 290 to change the pattern of supplying control information to only one operand, thereby making it possible to supply operands continuously.

Since memory access is performed in units of words, destructive duplication of operands may occur in some instructions, making it impossible for the advance control section to supply operands. In order to detect the above information, means for checking and testing the positional relationship of the operands is provided inside the address generation circuit 202. Although there is a register in the address generation circuit 202, the start address of both operands and the subsequent address necessary for the duplication test are set in a separate register to the one used for address calculation and used for comparison. A means of redundant testing will be provided. The timing of use of the duplication test means uses a detection instruction existing within the control information 251. If the preceding control unit determines that preemption is not possible by the duplication test means, the determination is reported via the signal line 604, and the control information 250 becomes invalid. The above control information is reported to the arithmetic unit via a signal line 604. The arithmetic unit performs a test as necessary before executing an arithmetic operation, and when a signal is sent on the signal line 604, the arithmetic unit cancels the memory refresher of the advance control unit and updates the operand address generation circuit 202. Control information is set using the signal line 605 to instruct memory access using the start address A left internally.

That is, a memory request is sent and an instruction is executed under the control of the arithmetic unit.

For some instructions, the maximum operand length that will be used in the preceding control part is known, but the operand length of the instruction actually used is determined by the calculation block and the maximum operand length that will be used in the calculation block. Some require memory requests after preprocessing. Take the signal line 6 from the calculation section above.
01.

The address and arguments, the request sending procedure, and the number of requests are set in the address generation circuit 202 via the registers 155 and 603.
By setting information effective for processing in 63 and 264 and returning memory access control to the full advance control unit, operands can be supplied continuously and at high speed.

(Effects of the Invention) As described above, the present invention continuously supplies the required length of operands specified by variable-length operand instructions, and detects the end of operand supply for the instruction by advance control. This has a great effect in that it becomes possible to continuously and efficiently supply operands to any instruction.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the advance control device according to the present invention. 101...Instruction register 110...Instruction decoding block 120.251...Operand address generation control information 121...Operand supply type instruction information 122...
・Instruction identification information 252...Operand supply end monitoring control information 130・
...Operand supply start instruction block 150.155,
156, 157, 261, 262, 263, 264...
・Register 21, IQ') 20- 230.271, 272...Selector circuit 270...
・Counter circuit 201.202...operand address generation circuit 26
0... Operand length read block 290... Branch circuits 161-166, 301-316, 501-503.6
01-605...Signal line patent applicant NEC Corporation agent Patent attorney Hisashi Inoro 22-

Claims (1)

[Claims] Destructive duplication of operands is prevented in a preceding control device capable of continuously supplying operands of instructions for supplying operands by multiple memory accesses in pipelined information processing, and detecting the end of the supply of operands of said instructions. a duplication detection means for detecting the same; a supply stop means for stopping operand supply when the duplication detection means detects a destructive duplication; and a notification means for notifying the arithmetic unit of the detected information. An advance control device characterized by being configured.