JPH01284943A - Information processor - Google Patents

Abstract

PURPOSE:To cope with the continuation of write commands via the fixed hardware regardless of the continuation degree of the write commands by securing a function to eliminate a case where an answer is waited for from a memory. CONSTITUTION:A write command given to a main memory 2 from a CPU 1 as a macroinstruction, is sent to the memory 2. Then the virtual address of said write command is converted into a real address by an address converting circuit 8. Thus the data are written into the real address as long as a page of a real memory corresponding to the page of said virtual address is included in a memory bank 6. In case the page of the real memory does not exist, the circuit 8 transmits a missing page signal to the CPU 1. Receiving this page signal, the CPU 1 sends a page operation command signal to a page operation mechanism 10 after confirming the missing page via a mission page confirming part 9.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to an information processing device that improves the processing speed of microinstructions.

(Prior Art) Conventionally, there is a virtual memory system equipped with a cache mechanism as an information processing device that executes microinstructions.

Conventionally, an instruction execution control method when executing a write command in such an information processing apparatus is as follows.

In other words, when a write command to the main memory is issued as a microinstruction from the microprogram memory of a central processing unit (hereinafter referred to as CPU), there is no need to write to the cache, so the write command is sent along with the write command regardless of whether it is a write hit or a miss. The virtual address is transferred to address translation circuitry in main memory. Then, address translation is performed to determine which real memory location the virtual memory location indicated by the virtual address corresponds to.

As a result, if a real memory page corresponding to a block called a page on virtual memory that includes the virtual address exists in the memory bank, data is written to that real address.

Conversely, if there is no page in real memory that corresponds to the page in virtual memory, the address translation circuit
A missing page signal is output to notify the user of this fact. When the CPU receives this, it controls the main memory, prepares the page on the real memory in the memory bank, and restarts from the write command.

By the way, in devices that use this type of control method,
In response to a write command, the CPU can leave the processing to the main memory as long as it sends the write data, so it can execute the subsequent microinstruction, but in such a case, a missing page will be notified in response to the write command. When the CPU executes the subsequent microinstruction, the data necessary to restart the write command may have already been lost from the register, making it impossible to restart from the second write command. There is a problem.

The solution to this problem is to focus on the characteristic of the store-through method, in which a copy of a page in the cache's virtual memory always exists in the main memory as a page in real memory. There is a method to terminate the write command by waiting for a response from the main memory only in the case of a hit.Also, there is a method to terminate the write command without waiting for a response from the main memory. Possible methods include terminating execution and making subsequent microinstructions executable.

However, the former method of checking cache hits and misses is not very versatile, and the store-through method is limited to writing to the cache memory, so it always applies to the memory bank of the main storage device as well. However, writing to the main memory does not necessarily result in the same write to the cache memory, so the cache hit rate of write commands is relatively low. The problem with the former method is that the more successive write commands there are, the more noticeable the reduction in processing speed becomes.

Furthermore, in the latter case, in which a register for saving restart information is provided, although a decrease in processing speed can be avoided, there is a problem in that the amount of hardware must be increased depending on the degree of continuity of write commands.

(Problems to be Solved by the Invention) As described above, the conventional method has a weakness in that λ=l is caused by consecutive write commands.

The present invention has been made in view of the above-mentioned problems of the prior art, and an object of the present invention is to increase the number of consecutive write commands without requiring an increase in hardware depending on the degree of consecutive write commands. The object of the present invention is to provide an information processing device that can be strengthened.

[Structure of the invention]

(Means for Solving the Problems) The information processing apparatus of the present invention provides for a middle-page portion of a write address of a processed write command immediately preceding a write command to be processed during execution of a write command to a main storage device. a comparator that compares the contents of the write address register with the color portion of page t1 at the write address of the write command to be processed, and outputs a match detection signal indicating a match between the two; a comparison signal gate circuit that allows a match detection signal from the comparator to pass only when there is no page operation in a memory bank of the main storage device between the processed write command and the target write command; and the comparison signal gate. The comparison signal is manually inputted via a circuit, and a microinstruction execution clock control circuit is provided that controls the execution of microinstructions by the CPU based on whether or not the coincidence detection signal is inputted manually.

(Function) According to the present invention, it is detected whether or not a write command to be processed accesses the same page as a processed write command that precedes it, and a link between the write command to be processed and the processed write command is detected. By checking the presence or absence of a page operation in , it is determined whether the page of the write command to be processed exists in the memory bank, and based on this, the execution of microinstructions by the CPU is controlled.

Therefore, since it functions to reduce the number of cases of waiting for a response from the storage device, a certain amount of hardware is used to handle the succession of write commands regardless of the degree of succession of the write commands.

(Example) Examples of the present invention will be described below with reference to the drawings.

First, FIG. 1 is a block diagram showing an embodiment of an information processing apparatus according to the present invention, and in this figure, 1 is a CPU;
2 is a main storage device, 3 is an input/output control device, and 4 is a system bus, and the CPU accesses the main storage device 2 through the input/output device 3.

This CPUI has a cache mechanism 5, the main storage device 2 has a memory panchromator and a memory control section 7, and the memory control section 7 includes an address conversion circuit 8.

In the information processing device shown in this figure, when writing to the cache memory of the cache mechanism 5 is assumed, similar writing is performed to the memory panchromatic memory of the main storage device 2; This is a store-through method in which writing is not necessarily performed when writing is required.

Therefore, the main memory 2 is sent from the CPU as a microinstruction.
When a write command is issued to , the write command is sent to the main storage device 2 and the address conversion circuit 8
The virtual address of the write command is converted into a real address.

As a result, if a page on real storage corresponding to the page at the virtual address exists in the memory panchromatic memory, data is written to that real address.

Conversely, if the page in real storage does not exist, the address translation circuit 8 sends a missing page signal to the CPUI. Upon receiving this, the CPUI checks it in its missing page confirmation section 9, and generates a page operation command signal from the missing page confirmation section 9. 1
Reference numeral 0 denotes a page operation mechanism consisting of system software, and when a page operation command signal is generated, the page operation mechanism 10 causes the memory control section 7 of the main storage device 2 to prepare the page on the real memory in the memory panchromatic memory. after that,
The CPUI sends the write data to the main storage device 2, and this ends the write command.

Now, the details of the CPUI will be explained. The hardware explained below is shown in (h) in Figures 2 to 4.
) It operates with timing determined by the reference clock CLK shown in FIG.

Reference numeral 11 denotes a microprogram memory, and this microprogram memory 11 stores a plurality of microinstructions including write commands (in (a) of FIGS. 2 to 4).
A, B, C, . . . ) are stored therein, and write commands are generated from this microprogram memory 11.

12 is an address calculation section, and 13 is an address register. The address calculation unit 12 calculates virtual addresses associated with memory commands such as write commands and read commands. The address register 13 holds the colored part of the page 11 which is the upper part of the virtual address.

14 is a command register, 15 is a command decode circuit, and 16 is a logic gate. The command register 14 holds microinstructions from the microprogram memory 11, and its output is supplied to a command decode circuit 15, which decodes the microinstructions and converts them into write commands. In some cases, a write command signal as shown in FIGS. 2 to 4 (b) that becomes logic "1" at the generation timing of the next microinstruction of the microinstruction in question is output.

In the example shown in the figure, microinstruction A is a write command. Logic gate] 6 receives the reference clock and the write command signal, and performs a logical product of the two.

17 is a write address register, and 18 is a comparator.

The write address register 17 is composed of, for example, a shift register, and uses the clock from the logic gate 16 as a write clock to take in the page unit part, which is the upper part of the virtual address from the address register 13, and has taken in the previous page part. Output data. The page unit data of the virtual address from the address register 13 and the page unit data represented by the output signal from the write address register 17 are input to the comparator 18 .

Therefore, in this comparator 18, the page unit part of the virtual address in the currently executed write command to be processed is compared with the page unit part of the virtual address in the processed write command immediately preceding the write command. . As a result, a comparison signal as shown in FIGS. 2 to 4 (d), which becomes logic "1" when they are the same, is output. When this comparison signal is logic "1", it is a coincidence detection signal.

19 is a logic gate, and 20 is a flip-flop. Here, the page operation mechanism 10 generates a page operation notification signal that becomes logic "1" from that time until the subsequent write command is completed when a page operation is performed with a read command between two successive write commands. Set the output function to H. One logic gate has a command decode circuit 1
5, a page operation notification signal from the page operation mechanism 10, and an output signal from the terminal Q of the flip-flop 20. ” and the output signal from the terminal Q of the flip-flop 20 is logic “1”.
” (that is, set state) and the output signal of the command decode circuit 15 is logic “0” (state in which the microinstruction being executed is not a write command), an output signal of logic “1” is generated. do. The output signal from the logic gate 19 and the open terminal CKI::reference clock signal are respectively input to the flip-flop 20 through its terminals. Therefore, this flip-flop 2
0 means that if there is no page operation between the currently being processed write command and the previous processed write command, the output signal from the terminal Q is logic "0".
(i.e. reset state) ((e) in Figures 2 to 4).
)reference).

21, 22, and 23 are logic gates, 24 is a flip-flop, and 25 is a microinstruction execution clock control unit.

The inverted signal of the comparison signal from the comparator 18 and the output signal from the terminal Q of the flip-flop 20 are input to the logic gate 21, and this logic gate 21 calculates the logical sum of both signals. When the output signal from the terminal Q of the flip-flop 20 is logic "1", a logic "1" is output regardless of the output of the comparator 18, and when the output signal from the terminal Q of the flip-flop 20 is logic "0", the comparison is made. vessel 18
The output of appears as the output signal. In other words, this logic gate 21 allows the coincidence detection signal from the comparator 18 to pass only when there is no page operation between the write command to be processed and the processed write command.

The logic gate 22 receives the output signal of the logic gate 21 and the logic "1" when there is a cache miss from the cache mechanism 5.
A cache notification signal as shown in FIGS. 2 to 4 (c) is input.

The logic gate 22 takes the logical product of both signals, that is, it outputs a logic "0" when a match detection signal is input from the comparison signal 18 and when there is a cash hit, and determines whether there is the page operation. Alternatively, when the comparison result in the comparator 18 is a mismatch and a cache miss, a logic "1" is output.

The logic gate 23 receives an output signal from the terminal Q of the flip-flop 24, an output signal from the logic gate 22, and an inverted signal of the write operation end signal which becomes logic "1" upon completion of the write operation from the main memory device 2. It has been entered. This logic gate 23 outputs logic "1" when the output of logic gate 22 is logic "1" and there is no human power for the write operation path r signal, and otherwise outputs logic "0". When there is no operation and a match detection signal is output from the comparator 18, when there is a cache hit, and when the write operation is completed in the main memory device 2, the output is logic "0".
become.

The flip-flop 24 has a logic gate 2 on its terminal.
The basic clock signal is inputted to the same terminal CK, and the output from the terminal Q is manually inputted to the microinstruction execution clock control section 25. This micro-instruction execution clock control section 25 generates an enable signal that allows generation of the micro-instruction execution clock when all its inputs are logic "0".

Therefore, the microinstruction execution clock control unit 25 generates an enable signal if the other inputs are logic "0" when the flip-flop 24 is in the reset state.

Next, the operation of the information processing apparatus of this embodiment configured as described above will be explained with reference to the time charts of FIGS. 2 to 4. Note that these figures show the case where microinstruction A is a write command, and FIG. If the signal is output, FIG. 3 shows the microinstruction A. If there is no page operation between the microinstruction A and the preceding write command, and if the comparator 18 does not output a match detection signal, FIG. The cases in which there is a page operation between instruction A and the preceding write command are shown.

First, if there is no page operation between microinstruction A and the preceding write command, the flip-flop 20 is in the reset state before microinstruction A is issued because the page operation notification signal is logic rOJ. In addition, when there is a page operation, the page operation notification signal is logic "1", so the flip-flop 20 is in the set state.

Then, when a microinstruction is issued from the microprogram memory 11, before the next microinstruction B is issued, its virtual address is calculated in the address:1 arithmetic unit, and this is set in the address register 13, and the virtual address is set in the command register 14. Microinstruction A is set to .

Command register 1 at the timing of the next microinstruction B
4 outputs microinstruction A, which is decoded by command decoding circuit 15. Since microinstruction A is a write command, the write command signal is set to logic "1". Therefore, the terminal C of the write address register 17
Since the basic clock is input to K, this write address register 17 takes in the page unit part of the virtual address output from the address register 13, and at the same time receives the virtual address in the write command that precedes the previously taken microinstruction A. Output the page unit part of. For this reason,
The comparator 18 compares the page unit data between the processed write command and the write command of the microinstruction A currently being executed, and outputs the result.

Here, there is no page operation and the comparator 18 detects a match (
When the number i is output, as shown in FIG. Since the output from the terminal Q of the flip-flop 24 becomes logic "0", the microinstruction execution clock continues to be output.

However, even if there is no page operation, if match detection No. 15 is not output from the comparator 18, control of the microinstruction execution clock is left to the hits and misses of the cache, and if this is the cache hit, the flip-flop Since the output from terminal Q of 24 becomes logic "0", the micro-instruction execution clock continues to be output, but
In the case of a cache miss, as shown in FIG. 3, the output of the logic gate 22 becomes logic "1", so the output of the logic gate 23 and the output from the terminal Q of the flip-flop 24 become logic "1". , the output of the microinstruction execution clock is stopped, execution of the microinstruction C is prohibited, and a response from the main memory device 2 is awaited. In this case, the write operation end signal is output from the main memory device 2 eventually, so the output of the logic gate 2B becomes logic "0".
The output of the terminal Q of the flip-flop 24 also becomes logic "0", and the output of the microinstruction execution clock is restarted.

If there is a page operation between microinstruction A and the previous write command, flip-flop 2
Since the output of terminal Q of 0 is logic "1", the fourth
Even if a match detection signal is output from the comparator 18 as shown in the figure,
The output of logic gate 21 becomes a logic "1" and control is left to cache hits and misses, and the rest is the same as in FIG.

In this way, according to this embodiment, even if there is a cache miss, there is no page operation between microinstruction A and the preceding write command, and write access to the same page as that processed command is possible. Since it has a function to determine whether or not a page exists in the main memory device 2 by seeing that the page is present, it is possible to improve the processing speed even when the cache hit rate is low. can. Particularly, when write commands are consecutive, it is possible to eliminate more wasteful delay time, which is extremely effective.

In the above embodiment, a case has been described in which the present invention is applied to a store-through type information processing apparatus in which the effects thereof are noticeable, but the present invention can also be applied to other types of information processing apparatus.

〔Effect of the invention〕

As explained above, according to the present invention, it is detected whether a write command to be processed accesses the same page as the processed write command that precedes it, and the write command to be processed and the processed write command are By checking the presence or absence of a page operation in between, it is determined whether the page of the write command to be processed exists in the memory bank, and based on this, the enable/disable of the transmission of the microinstruction execution clock is controlled. By doing so, it functions to reduce the number of cases of waiting for a response from the storage device, so it has the effect of being able to handle a series of write commands with a certain amount of hardware regardless of the degree of continuity of the write commands. play.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment in which the information processing apparatus of the present invention is applied to a virtual memory type device that has a store-through type cache mechanism, and FIG. 2 shows its operation. Figure 3 is a time chart when there is no page operation between the command and the processed write command and a match detection signal is output from the comparator. FIG. 4 is a time chart for the case where no match detection signal is output from the comparator, and FIG. 4 is a time chart for the case where there is a page operation between the write command to be processed and the processed write command. DESCRIPTION OF SYMBOLS 1...CPU (central processing unit), 2...Main memory (storage device), 6...Memory bank, 17...Write address register, 18...Comparator, 21...
Logic gate (comparison signal gate circuit), 22.23...
Logic gate, 24...Flip-flop, 25...
Microinstruction execution clock control unit. Furthermore, the logic gate 22
23, the flip-flop 24 and the microinstruction execution clock control section 25 constitute a microinstruction execution clock control circuit. Applicant's agent Mr. Sato

Claims (1)

[Scope of Claims] 1. In an information processing device comprising a main storage device having an address translation circuit that converts a virtual address into a real address, and a CPU having a store-through type cache memory, writing to the main storage device is provided. When a command is executed, there is a write address register that stores the page unit at the write address of the processed write command that precedes the current write command to be processed, and the contents of the write address register and the write address of the write command to be processed. a comparator that compares the page units and outputs a match detection signal indicating a match; and a comparator that compares the page units and outputs a match detection signal indicating a match between the two; a comparison signal gate circuit that allows a match detection signal from the comparator to pass when the page is manipulated, and blocks the match detection signal from the comparator from passing when the page is manipulated; a micro-instruction execution clock control circuit to which the coincidence detection signal is input, and which controls the execution of micro-instructions by the CPU based on whether or not the coincidence detection signal is input; Device.