JPH0519172B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a microprogram control method, and more particularly to a branch control method for microinstructions that involve branching in an information processing device that employs a microprogram control method. .

[Background of the invention]

In an information processing device that uses a microprogram control method, when high-speed processing of microinstructions (hereinafter simply referred to as instructions) is required, preprocessing and instruction execution during instruction execution such as instruction reading and instruction decoding are required. Pipeline processing is used to perform these independently.

If it is possible to perform preprocessing in the execution of one instruction and execution of one instruction in the same machine cycle by such pipeline processing, the time required for preprocessing can be made to appear to be zero. However, in a device that uses an inexpensive, low-speed storage element for microprogram (storage) control memory and a high-speed theoretical element for the arithmetic processing section, the instruction execution cycle is The instruction read cycle is longer than the previous one. For this reason, the time it takes to read an instruction after the execution of one instruction ends and the start of execution of the next instruction appears, and extra time is required for the execution of the instruction.

As one method for solving this problem, a method is known in which a plurality of instructions are simultaneously read from the control memory. According to this method, even if the read cycle of one instruction is longer than the execution cycle of one instruction, as long as one control memory access is possible in the execution cycle of multiple instructions, it is invalid for instruction execution. Cycles can be prevented from occurring. However, the number of instructions to be read at the same time is determined depending on the machine cycle, access time of control memory, capacity of the instruction read register, etc., but here, we will consider the case where two instructions, which are consecutive execution units, are read at the same time. . An example is shown in FIG. In this example, a set of instructions A and B, which are consecutive execution units, are read from the control memory in machine cycles 1 and 2, and instruction A is executed in the third cycle and instruction B is executed in the fourth cycle. After that, the set of instructions C and D is read out, overlapping with the execution of instructions A and B, and then the execution of instruction C and the instruction D are executed.
By executing , invalid cycles in the instruction execution cycle can be eliminated.

In this method, instruction prefetching is performed in anticipation of a case in which instructions will be executed sequentially, so when a branch occurs due to a branch instruction, high-speed execution becomes a problem. This is because if the instruction to be executed after branch condition determination is not subject to prefetching, the instruction execution cycle is interrupted (occurrence of invalid cycles) and effective performance is degraded. Processing when a branch occurs will be described below based on the example shown in FIG.

FIG. 5 shows its flow chart, and FIG. 6 shows its time chart. Instruction A is a two-way branch instruction, and branching is performed based on condition determination of this instruction. After determining the branch condition, when the condition is met, reading of the next set of instructions E and F on the side where the condition is met is started, but since the read cycle is longer than one machine cycle, instruction E is started after execution of instruction A. Until then, one machine cycle of invalid cycles occurs. Conversely, when the condition is not met, reading of sets C and D is started at the next instruction in the order in which the condition is not met. At this time, the reading of instructions C and D ends after one machine cycle or more, just as when the conditions are satisfied, but since instruction B, which was read at the same time as instruction A, can be executed, it appears that No invalid cycles occur. Furthermore, when instruction B is a branch instruction, similarly, one machine cycle is invalidated only when the branch instruction is established. In this way, a branch in which an invalid cycle occurs when a branch is taken is hereinafter referred to as a dummy branch.

As a solution to this problem, for example, a delayed branching method can be adopted. In this method, after the branch condition is established, a certain cycle of operations is performed on both the branch taken side and the branch untaken side, and then an operation-end branch is performed.

FIG. 7 shows an example in which the delayed branching method is adopted for the branching shown in FIG. 5. Moreover, the time chart of FIG. 7 is shown in FIG. The difference between FIG. 7 and FIG. 5 is that after the branch of instruction A is established, the operation of instruction B is executed and the branch is taken. This is to execute instruction B in common regardless of whether the branch is taken or not, and to always effectively utilize the prefetched instruction B. Therefore, the operations are actually distinguished after instructions C and E, respectively. However, due to the operation of the microprogram execution procedure, the instruction B
If is an operation unrelated to the branch condition, a series of instructions can be executed without invalid cycles even when a branch is taken. However, in the example shown in FIG. 7, if instruction B is a branch instruction and the branch is taken, an invalid cycle occurs as in FIG. 5. This is because instruction E is not subject to prefetching.

As mentioned above, 2
In a microprogram control system in which instructions are read simultaneously, the following problems occur when branch instructions are executed.

First, when performing the dummy branch shown in Figure 5, there is a problem that the prefetched instruction becomes invalid when the branch is taken, and the effective performance at the time of the branch is taken is reduced.However, the actions immediately after the branch instruction are independent of each other. Become.

On the other hand, if the delayed branch shown in FIG. 7 is possible, it is possible to eliminate the occurrence of invalid cycles even when the branch is established, but there is a problem that a common operation of a certain number of cycles is executed even after the branch is taken. This is a major programming constraint.

As described above, each of the above two branching methods has its own advantages and disadvantages, and it is desirable that they can be selectively used depending on programming. However, the hardware that controls instruction execution is fixed to one or the other in order to simplify the control theory, and there is a problem in that the above-mentioned branch method cannot be freely selected for each branch instruction.

An example of related technology is Nikkei Computer, ``32-bit Super Micro Expanding into General-purpose Mini Computers,'' p. 77, May 27, 1985 issue.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to solve such conventional problems and to improve a branching method when a branch of a conditional branch instruction is established in a microprogram control system in which two instructions, which are consecutive execution units, are read simultaneously. It is an object of the present invention to provide a microprogram control method that improves the degree of freedom when executing branch instructions.

[Summary of the invention]

In order to achieve the above object, a microprogram control device of the present invention includes a first register that holds a plurality of microinstructions read in one access unit from a control memory storing microinstructions, and It has means for selecting one micro-instruction from the micro-instructions, and a second register for holding the one micro-instruction selected by the selecting means. In a microprogram control method in which the next multiple instructions are read from the control memory and executed sequentially according to the specification of the microinstruction held in the register No. 2, a branch method identification flag is provided in the field of the microinstruction, and the If the microinstruction held in the second register has a branch, the microinstruction held in the second register is determined based on the branch determination result of the microinstruction held in the second register and the branch method identification flag. After the execution of , a plurality of instructions held in the first register to be executed sequentially are executed.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a diagram showing an example of the configuration of microinstructions used in the present invention.

The microinstruction 20 treats two instructions, which are consecutive execution units, as one word. Each field within one word is an even number (EVEN) field 21,
It is divided into an odd number (ODD) field 22 and a common (COMMON) field 23. The control memory is read word by word, and then the instruction specified in the EVEN field 21 (EVEN instruction) is executed in one machine cycle, and the instruction specified in the ODD field 22 (ODD instruction) is executed in one machine cycle. This is done sequentially in one machine cycle. EVEN field 21, ODD field 2
2 specifies the operation of the microinstruction, and each is independent. COMMON field 23 is
This field is valid for either the EVEN field 21 or the ODD field 22, and this field 23 contains the valid flag E, branch control flags B0 and B1, branch conditions, and branch destination address (not shown). Here, E="0"
When , it indicates that COMMON field 23 is valid for EVEN command, and when E="1",
Indicates that it is valid for ODD instructions. Also, BO=
When it is “0”, a dummy branch is executed after the branch condition is met,
When BO="1", it indicates that a delayed branch is executed after the branch condition is met, and when B1="0", after the branch condition is not met, the next instruction is invalidated, and B1
="1" indicates that the next instruction is valid after the branch condition is not met.

FIG. 1 is a block diagram of a microprogram control device showing one embodiment of the present invention.

Register 2 is an address register (hereinafter referred to as address register) that physically holds the address of a one-word instruction (microinstruction). After the instructions (two instructions) pass through the error detection/correction circuit (ECC circuit) 8, they are loaded into the data buffer register (CSDR) 3. The one-word instruction loaded into the data buffer register 3 is first loaded with the field 21 necessary for the execution of the EVEN instruction into the data register (MPDR) 4 and executed by the instruction execution circuit 9, and then executed by the instruction execution circuit 9. Upon completion, the fields 22 necessary for executing the ODD instruction are loaded into the data register 4 and executed in the same manner. The data line 103 sends the next instruction address of one word of the branch field held in the data register 4 to the address register 2 when the EVEN instruction is loaded into the data register 4. Therefore, reading of the next instruction of one word is started at the time when the EVEN instruction is loaded into the data register 4. Data lines 105 and 106 are connected to the instructions held in the data buffer register 3, respectively.
COMMON in COMMON field 23
Field valid flag E, branch control flag B0,
This is shown in the value of B1. The line 107 is a signal line that is set to "1" when the instruction held in the data register 4 is an instruction having a branch, and the branch condition is satisfied. The line 108 is the AND of the AND circuit 5.
When the condition is met, it indicates "1", and the line 109 is
Indicates "1" when the AND condition of the AND circuit 6 is satisfied. The line 110 is a signal line that indicates "1" when the AND condition of the AND circuit 5 or 6 is satisfied, and disables the instruction execution circuit 9 from executing the ODD instruction.

Next, a description will be given of a case where a branching condition is satisfied regarding the branching control method that is a feature of the present invention.

First, in FIG. 1, when the EVEN instruction among the one-word instructions loaded into the data buffer register 3 has a branch, the signal line 104 indicates "0". Further, if the branch control flag indicates a dummy branch, the signal line 105 indicates "0". Then, the EVEN instruction loaded from the data buffer register 3 to the data register 4 is executed by the instruction execution circuit 9, and when a branch is established as a result, the signal line 107 becomes "1". From the above, AND circuit 5
output becomes "1", and the execution of the ODD instruction becomes dummy due to the signal line 108 and the signal line 110.

As a result, a dummy branch operation is performed when the condition shown in FIG. 6 is satisfied. On the other hand, if the branch control flag indicates a delayed branch, the signal line 105 indicates "1", and even if a branch is established as a result of execution of the EVEN instruction, the output of the AND circuit 5 and the AND circuit 6
The output becomes "0" and the ODD instruction is executed. As a result, the delayed branch operation when the condition shown in FIG. 7 is satisfied is performed.

Next, there is a case where the ODD instruction among the one-word instructions loaded into the data buffer register 3 has a branch. , all become dummy branches. Furthermore, even when the branch condition is not met, the output of the AND circuit 6 is controlled under the same conditions as when the branch condition is met. however,
When the branch condition is not satisfied, the input line 10 of the AND circuit 6
The opposite value of 7 is input to the AND condition. As a result,
When the branch condition is not satisfied, the ODD instruction is suppressed or executed according to the AND condition of the AND circuit 6.

In this way, in this embodiment, branch control for instructions with branches can be specified for each branch instruction, so an inexpensive and slow memory element is used for control memory, and a high-speed theoretical element is used for the arithmetic processing section. The degree of freedom in microprogramming is improved in such devices, and the overall performance of the microprogram is improved by using dummy branches and delayed branches according to the program configuration. Furthermore, it becomes easy to add a fault correction function, which increases the access time to the control memory, and improves reliability.

In this embodiment, we have explained the branch control method when two consecutive instructions are simultaneously read from the control memory, but this branch control method is also applicable to the case where two or more instructions are simultaneously read from the control memory. be. However, in this case, in order to enable execution control of multiple instructions read simultaneously, a plurality of corresponding branch control flags are required.

〔Effect of the invention〕

As explained above, according to the present invention, in a microprogram control system in which two instructions, which are consecutive execution units, are read simultaneously, the branching method when a branch of a conditional branch instruction is taken can be controlled by the microprogram. , the degree of freedom when executing branch instructions can be improved.

[Brief explanation of drawings]

Figure 1 is a schematic configuration diagram of a microprogram control device showing an embodiment of the present invention, Figure 2 is a diagram of the configuration of a microinstruction according to this embodiment, and Figure 3 shows that the machine cycle is determined by the instruction read time. Figure 4 is a time chart when two instructions are read simultaneously. Figures 5 and 7 are flowcharts when executing a branch instruction. Figures 6 and 8 are flowcharts when executing a branch instruction. It is a time chart. 1: Control memory, 2 to 4: Registers, 5, 6:
AND circuit, 7: OR circuit, 8: error detection/correction circuit, 9: instruction execution circuit.

Claims (1)

[Claims] 1. A control memory storing a plurality of microinstructions including an even instruction field, an odd instruction field, and a common branch field; a first register holding one microinstruction read out in one access unit from the control memory; means for sequentially selecting one of an even instruction field and an odd instruction field of the one microinstruction held in the register; a second register holding the instruction field selected by the selecting means; instruction execution means for executing the instruction field held in the second register; and means for reading one microinstruction of the next one access unit from the control memory according to the specification of the instruction field held in the second register; A microprogram control device comprising a branch method identification flag is provided in the common field of the microinstruction, and when the instruction field held in the second register is an even instruction field and has a branch function, Based on the branch determination result of the even instruction field and the branch method identification flag of the one microinstruction held in the first register, it is determined whether or not the odd instruction field held in the first register can be executed. A microprogram control method characterized by: