JPH0412860B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] Regarding the ring level that defines the access protection level for each logical space unit, the read instruction and the ring level to which the instruction belongs are stored in the instruction buffer register, and at the same time the pipeline This enables prefetching of the branch destination for consecutive branch instructions, and speeds up instruction execution by prefetching the branch destination instruction in parallel with the operand access latency and calculation time of the instruction before the branch instruction. It makes it possible to

[Industrial application field]

The present invention relates to a ring level control method, and more particularly, to a ring level control method for an information processing device that performs access protection in logical space units using a so-called ring level, and that executes instructions through pipeline processing. It is.

[Conventional technology and problems]

For example, a so-called ring is used as a method to protect data in the main memory so that an application processing program executed in an information processing device does not destroy the operating system etc. by executing instructions. A level-based access protection method is used. In ring level access protection, for example, the protection level is defined by 3 bits corresponding to a segment of logical space, and when the execution ring level is a larger value than the reference ring level, instruction reading,
Data writing is now prohibited.
The execution ring level is the program state word (PSW)
The ring level stored and referenced in the segment table is defined in advance for each entry in the segment table.

For example, when branching from one segment to another, whether the ring level currently set in the PSW for reading an instruction is a ring level that allows control to be transferred to the branch destination. If the check does not pass, a program interrupt is generated.

FIG. 3 is a diagram for explaining the problems of the conventional method.

Assume that an instruction 1, a branch instruction B1 that follows it, and a branch instruction B2 that follows it are processed by pipeline processing. Each instruction consists of a D cycle for decoding the instruction and an A cycle for calculating the address.
, a T cycle and a B cycle for performing memory access, an E cycle for performing an operation, and a W cycle for writing the operation result. Furthermore, prior to these cycles,
Cycle to fetch instructions, T cycle, B
There is an R cycle that sets the cycle and instructions into the instruction buffer.

When the instruction is a branch instruction, an instruction buffer is prepared for prefetching the branch instruction when the branch condition is satisfied and the branch is successful. However, the conventional system does not provide a buffer for reading an instruction and storing the ring level to which the instruction belongs. Therefore, although there is an advantage that the amount of hardware related to ring-level storage is small, there is a problem that prefetching of instructions is limited and instruction execution performance is degraded.

That is, for example, as shown in FIG. 3, it is assumed that the E cycle of instruction 1 requires several cycles to be repeated. In this case, the branch instruction B1 waits in B cycles until the end of execution (EU END) of the instruction I1 is notified. After the D cycle of the branch instruction B1, for example, when the branch is successful, the instruction is prefetched, but at this time, the ring level to which the instruction belongs is also read, and 1 for the ring level is read.
It is set to a unique buffer.

The buffer for this ring level is branch instruction B.
It will not be released until the result of 1 is confirmed. Therefore, after branch instruction B1, there is branch instruction B2,
When branches occur continuously, the branch destination instruction related to the subsequent branch instruction B2 cannot be read ahead and accessed because there is no ring level buffer, resulting in a waiting time.

The length of this latency increases in proportion to the length of operand access time and operation latency. Furthermore, if there is no instruction to be prefetched in the local buffer storage (LBS), which is a so-called cache memory, the access time will increase.

[Means for solving problems]

The present invention aims to solve the above-mentioned problems and provides a means for processing ring level information in a pipeline manner to enhance the effect of prefetching branch instructions.

FIG. 1 shows a basic configuration diagram of the present invention.

In FIG. 1, 10A, 10B, and 10C are instruction work registers (IWR) where fetched instructions are stored, 12 is an instruction buffer register where prefetched instructions are saved, and 13 is an instruction and ring register corresponding to each cycle. Pipeline with level tags, 14 to 18 are selectors, 20 to 2
4 is a tag that holds OP code and operand information,
30 to 34 are tags that hold ring level information corresponding to each cycle, and RL represents the ring level.

The instruction read from the local buffer storage LBS is set into a free one of the instruction working registers 10A-10C along with the ring level RL. This instruction and ring level RL
is sent to the pipeline 13 via the selector 15
The data is sequentially sent to tags 20 to 24 and tags 30 to 34, and used for processing commands and checking the ring level RL.

If there is a waiting time in the processing of the preceding instruction, the prefetched instruction is set in one of the instruction buffer registers 12 through the selector 14. The instruction at the branch destination upon successful branching is also prepared in this instruction buffer register 12. In the case of the present invention, ring level RL information to which the stored instruction belongs is stored in each instruction buffer register 12 along with the instruction.

The ring level RL information sent to the pipeline 13 via the selector 15 is sequentially sent to the tags 30 to 34, and the selector 17 selects the ring level RL or the calculation result (ARC12).
One of the ring levels RL is selected. The selector 16 is a circuit that selects the resulting ring level RL when a load PSW command or an interrupt occurs. The selector 18 is a circuit that selects the designated ring level RL (TLR) when executing an instruction that designates transfer across spaces, and uses the designated ring level RL (TLR) to access the storage device SU.

[Effect]

According to the invention, the ring level to which each instruction belongs
The RL is stored with each of its prefetched instructions and flows into the pipeline 13 with each of those instructions. Therefore, it is not possible to prefetch an instruction because the ring level buffer is full, and it is possible to shorten the overall waiting time in executing an instruction.

〔Example〕

FIG. 2 is a diagram for explaining the operation in one embodiment of the present invention.

The instruction execution environment in FIG. 2 is similar to the conventional example shown in FIG. That is, instruction I1 is followed by branch instruction B1 and branch instruction B2. When the E cycle of instruction I1 takes several cycles, the subsequent branch instruction B1 is forced to wait for B cycles. Regarding branch instruction B1, when the branch condition is satisfied and the branch is successful, the prefetch of the branch destination instruction is started after the D cycle of branch instruction B1, and register 12-, which is one of the instruction buffer registers, is read ahead. It is stored in 1. Ring level RL information to which this instruction belongs is also stored in the same buffer register 12-1.

On the other hand, branch instruction B2 following branch instruction B1 is also processed in the pipeline, and while branch instruction B1 is waiting for processing in cycle B,
Waits at the previous T cycle. Prefetching of the branch destination instruction for branch instruction B2 can begin after the D cycle of branch instruction B2, and is performed in parallel to the operand access latency and operation time for the preceding instruction. The ring level RL information of the instruction at this branch destination is stored in a buffer register 12-2 different from the buffer register 12-1.
It is set together with the branch destination instruction, and there is no conflict on the buffer with the ring level RL information to which the branch destination instruction of the preceding instruction belongs, so there is no need for the waiting time associated with instruction prefetching. becomes.

Note that the instruction to read ahead is a local buffer.
If it is not in the storage LBS, it can be processed in parallel to the calculation time.

〔Effect of the invention〕

As described above, according to the present invention, since there is no conflict regarding the ring level RL information to which the prefetched instruction belongs, it is possible to prefetch the branch destination in a branch instruction, and the execution performance of the instruction is improved.

[Brief explanation of drawings]

FIG. 1 is a basic configuration diagram of the present invention, FIG. 2 is a diagram for explaining the operation of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of a conventional system. In the figure, 10A, 10B, 10C are instruction work registers, 12 is an instruction buffer register, 13 is a pipeline, 14 to 18 are selectors, 20 to 24 are tags, 30 to 34 are tags that hold ring level information, RL represents the ring level, respectively.

Claims (1)

[Claims] 1. In an information processing device that performs pipeline processing, which accesses operands and instructions independently, has a ring level for access protection in logical space units, and performs pipeline processing: means 1 for storing in an instruction buffer register the ring level to which the instruction belongs together with the instruction;
2, and means 30 to 34 for simultaneously flowing the ring level to which the selected instruction belongs to the pipeline 13 in accordance with the selected instruction, and reducing the operand access latency and operation time of the instruction preceding the branch instruction. A ring level control method characterized by prefetching branch destination instructions in parallel.