JPS6043750A - Microprogram controller - Google Patents

Abstract

PURPOSE:To reduce a memory capacity and to increase an executing speed by using plural microinstructions MI and a jump address to form the MI of a word. CONSTITUTION:The two MIs which are written to the 1st and 2nd MI parts MI-1 and MI-2 within a word 28 read out of a storing memory 21 are latched by a latch circuit 22 by a latch clock 36. A selecting circuit 25 selects these two MIs individually in response to the logic state of a division output 34, then supplied to a microprogram executing circuit 23 to be executed. While a jump address part JA within a word 28 is supplied to an OR circuit 24 to obtain an OR with the executed result 38 of the circuit 23. An address 39 thus obtained is latched by the circuit 22 by the clock 36, then supplied to the memory 21 as an execution address 41. Then an address to receive the next address is designated.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a microprogram control device used in an information processing device, and particularly to a microprogram control device used in an information processing device, and particularly to a microprogram control device for quickly accessing a memory storing individual microinstructions. The present invention relates to a microprogram control device equipped with means for controlling the microprogram.

[Prior art]

Inside the CPU (central processing unit), there is a control unit for controlling the operations of the AL[J (arithmetic circuit) and registers disposed therein. A control unit that is equipped with a memory for storing a microprogram (microprogram storage memory) and is controlled by the microprogram,
Here, it will be referred to as a microprogram controller.

Now, in the microprogram control device, microinstructions (microinstructions) read from the microprogram storage memory are supplied to a microprogram execution circuit, where the instructions are decoded and executed. At this time,
The address to be accessed next (hereinafter referred to as the execution address) is determined.

This execution address is supplied to the microprogram execution circuit and specifies the next microinstruction to be read.

FIG. 1 shows the format of a one-word microinstruction used in a conventional microprogram controller. Three types of microinstructions are used in this device. These microinstructions are provided with a type section T for determining their respective types. The microinstruction 11 shown by Δ in the same figure is composed of the type part T and the operand part ○P, and is used when performing calculations between registers. The microinstruction 12 shown in FIG. 2B is composed of a type part T1, an operand part OP, and a jump address part JA, and is used when executing a conditional branch.

In addition, microinstruction]3 shown in C in the same figure is
It consists of a type part T and a jump address 813jΔ, and is used when executing an unconditional branch.

The relationship between these microinstructions 11 to 13 and the execution address to be accessed is as follows.

In the case of t 1' microinstruction 11,
The address obtained by adding +1 to the address currently being executed becomes the execution address. In the case of the microinstruction 12, the address is different depending on whether the condition specified by the condition feed is satisfied or not. That is, when it is satisfied, the jump destination address JA becomes the execution address, and when it is not satisfied, the address obtained by adding +1 to the address currently being executed becomes the execution address. Finally, in the case of microinstruction 13, the jump destination address JA becomes the execution address, and the program jumps to this address unconditionally.

By the way, in a CPU using a microprogram, the operating speed of the device depends on the execution speed of the microprogram. In other words, increasing the execution speed of the microprogram is an important factor in improving the performance of the CPU. However, in the conventional microprogram control device, as already explained, the execution end is determined by adding 1 to the address currently being executed. Therefore, calculation time is required for this purpose, which poses a problem in improving performance.

Note that FIG. 2 shows a one-word microinstruction for a microprogram control device proposed to solve these problems. This microinstruction 15 is composed of an operand section ○P and a jump destination address section JA. The operation of this proposed device will be explained based on FIG. It is assumed that the microinstructions are executed along the flow shown on the left side of the figure. The right side of the figure represents the configuration of each of the microinstructions Δ to D.

Now 51 n word W. When the microinstruction A of , is executed, the microinstruction B of the next word W , , + 1 is executed by the microprogram execution circuit (not shown) according to the jump destination address and the jump destination address (n+1) indicated by I5JΔ. is man-powered. Microinstruction B is a conditional branch instruction, and the condition does not hold in the jump destination address part JΔ (
The execution address (n+2) in case No) is written.

Therefore, if the condition does not hold, this word W n +
2 microinstruction C is read out,
executed.

Microinstruction C has destination address n+
Since 3 has been written, the next word W
n + 2 microinstructions E will be read.

Meanwhile, Ward W. If the condition shown in +1 microinstruction B is satisfied (YES), the value m obtained by ORing the execution result of the microprogram with the jump destination address (n+1) becomes the execution address. Therefore, in this case, the microinstruction D of word W of 'fJi, m is read out and executed. Then, in the next step, the microinstruction F of the next word W□1 is read out and executed.

According to the proposed microprogram control device, there is no need for additional operations to add execution addresses, so the effective speed becomes extremely high. However, the destination address JA of the microinstruction is sufficient to access all addresses in this case. Therefore, there are disadvantages in that a large number of bits are required for the jump address JA, and a large capacity memory is required to store the microinstructions. The object of the present invention is to provide a microprogram control device that does not require a large capacity memory for storing microinstructions and has a high execution speed.

[Structure of the invention]

In the present invention, one word of microinstructions is composed of a plurality of microinstructions and one jump address (NEXT ΔDDR-ESS), and these microinstructions are sequentially executed by a microprogram execution circuit. Then, the execution result of the last microinstruction of one word and the jump destination address are logically summed to determine the address to be accessed next (execution address).

〔Example〕

The present invention will be described in detail below with reference to Examples.

FIG. 4 shows the microprogram control device of this embodiment. This device includes a storage memory 21 that stores a microprogram, a latch circuit 22 that latches read microinstructions, and a microprogram execution circuit 2 that executes the microprogram.
In addition to general elements or circuits such as 3, an OR circuit 24, a microinstruction selection circuit 25,
It also includes a microinstruction instruction section 26 for instructing microinstructions.

FIG. 5 shows the structure of one word of microinstruction (hereinafter simply referred to as a word) stored in the storage memory 21 of this device. The word 28 is composed of two microinstruction sections Ml-LMI-2, a first and a second microinstruction section, and one jump address section JΔ. An independent microinstruction is written in each microinstruction section.

Now, the clock generation circuit 29 in the microinstruction instruction unit 26 is designed to output a clock signal 31 for executing each microinstruction. An execution lock 32 (FIG. 6a) which inverts the logic of this clock signal 31 serves as a clock for both the microprogram execution circuit 23 and the D-type flip-flop circuit 33. As a result, a frequency-divided output 34 is obtained from the output terminal F of the D-type flip-flop circuit 33, which repeatedly rises and falls in synchronization with the rising edge of the lock 32, as shown in FIG. Further, a latte clock 36 (FIG. 6C) having the same period as the frequency-divided output 34 is created from a NAND circuit 35 which NANDs the frequency-divided output 34 and the clock signal 31.

The first and second microinstruction sections Ml-1 in the word 28 read from the storage memory 21
, M-2 are latched into the latch circuit 22 by the latch clocker 36.

The selection circuit 25, depending on the logic state of the frequency division output 34,
Select one of these two types of microinstructions. These are then sequentially supplied to the microprogram execution circuit 23 for execution.

On the other hand, the jump destination address section JA in the word 28 is input to the OR circuit 24. The OR circuit 24 performs a logical OR between the execution result 38 of the microprogram execution circuit 23 and the jump destination address. Then, the address 39 obtained as a result is latched by the latch circuit 22 using the latch clock 36. Then, this is set as the execution address 41 in the storage memory 21. and specify the address to be accessed next.

The specific operation of this microprogram control device will be explained using FIG. 7 compared with FIG. 3. In this embodiment, one word includes two microinstructions, so microinstruction Δ is first executed by the nth word Wl, and then the next microinstruction B is executed. This word■1
．． ．． The next word W +1 is in the jump destination address part JΔ.
+ 1 address (n + 1) is written. Therefore, if the condition is not satisfied (NO) in microinstruction B (conditional branch instruction), an all-O data is output as the execution result 38, and the address (n + 1) becomes the execution address 41 as it is. . In this case, the (n+1)th word W, .

is read out from the storage memory 21. The selection circuit 25 first supplies the microinstruction C to the microprogram execution circuit 23 according to the instruction from the frequency division output 34, and causes it to be executed. Next, when the frequency division output 34 is inverted, the next microinstruction E is supplied to the microprogram execution circuit 23 and executed. The same applies below.

On the other hand, the condition is met in microinstruction B (Y
ES), predetermined data is output as the execution result 38, is logically summed with address n, and becomes address m.
is determined. In this case, the nth word W7 is read from the storage memory 21 and microinstructions D and F are executed in this order.

The same applies below.

Although the case where two microinstructions are incorporated into one word has been described above, it is also possible to incorporate three or more microinstructions into one word. FIG. 8 shows the words obtained by (iii) for the first to nth microinstruction sections M-1 to M-I-n.

Only one jump destination address section JΔ is arranged after the n-th microinstruction section M I-n. A microprogram control device using such a microprogram uses, for example, a ring count to selectively execute individual microinstructions within each word. Then, the next word is accessed using the address as it is shown in the jump destination nutless section JA or the address processed by logical sum as the execution address.

〔Effect of the invention〕

As explained above, according to the present invention, multiple microinstructions and one jump address are incorporated in one word, so not only can the total memory capacity for storing microinstructions be reduced, but also Since there is no need to perform address addition processing, the execution speed of the apparent microprogram is increased. Therefore, even if an inexpensive memory with a slow access time is used, the execution speed is not reduced.

[Brief explanation of the drawing]

Figures 1 and 2 are configuration diagrams showing the configuration of conventionally used microinstructions, and Figure 3 is an explanatory diagram illustrating the flow of a microprogram using the microinstructions configured as shown in Figure 21. , FIGS. 4 to 7 are only for explaining one embodiment of the present invention,
Figure 4 is a block diagram of the microprogram control device, Figure 5 is a configuration diagram showing the word configuration, Figure 6 is a waveform diagram of various signals output from the microinstruction instruction section, and Figure 7 is the flow of the microprogram. FIG. 8 is a block diagram showing the structure of a word incorporating n micro-instructions. 21...Storage memory, 23...Microprogram execution circuit, 24...
...Order circuit, 25...Selection circuit, JΔ...Jump address, MI...Micro instruction, W...
word. Applicant Fuji Serotox Co., Ltd. Representative Patent Attorney Ume Yamauchi Wholesale

Claims (1)

[Claims] A storage means for storing a microprogram in which n microinstructions and one jump address are incorporated in one word, and execution of the jump address and the previously executed microinstruction in the word read from the storage means. address determining means for logically ORing the result and determining the address of the next word to be read from the storage means; microinstruction selecting means for sequentially and alternatively selecting each microinstruction in the read word; 1. A microprogram control device comprising: microprogram execution means for executing microinstructions.