JPH04148236A - Central processing unit - Google Patents

Abstract

PURPOSE:To attain the high speed processing by providing two instruction code queue circuits so as to leave an instruction code at the time of non-branch and the instruction code at the time of branch stored even at the time of the execution of a branch instruction in a program, and executing the instruction code by selecting one of these. CONSTITUTION:At the time of the non-branch, the instruction code stored in a first instruction code queue circuit 11 is transferred to an instruction decode circuit 2, and at the time of the branch, the instruction code stored in a second instruction code queue circuit 21 is transferred to the instruction decode circuit 2, and the branch instruction is executed. Thus, program address information shown by a first instruction code look-ahead pointer circuit 12 shows the address information after branch, and the instruction code after branch is stored in the first instruction code queue circuit 11, and after the lapse of definite time, the first instruction code look-ahead pointer circuit 12 and the instruction code queue circuit 11 are used again, and a system returns to usual operation. Thus, access time to an external address/data bus can be neglected in appearance, and the high-speed processing can be realized.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a central processing unit in a computer system, and in particular, to speeding up processing even when there is a branch instruction in the processing program of the central processing unit. It relates to a central processing unit that can.

[Conventional technology]

Typically, a computer system includes a central processing unit 6 that executes arithmetic functions and control functions for various devices as a computer system, and a main memory that stores instruction codes and data for the computer system, as shown in FIG. 7, and an input/output device 8 that controls data input/output to the outside of the computer system.
Consists of spiky bones. In the aforementioned computer system, the conventional central processing unit 6 is shown in the block diagram of FIG. 3. The conventional central processing unit shown in FIG. Circuit 1 and
An instruction decode circuit 2 that decodes instruction codes for the central processing unit; a timing/control circuit 3 that executes various timings and controls of various circuits based on the instruction decoded by the instruction decode circuit 2; A program counter 4 manages sequential access and operation of instruction codes to be processed, a general-purpose register group 5 serves as a storage area for processing results within the central processing unit, and a group of general-purpose registers 5 is placed before the instruction decode circuit 2. An instruction code queue (Queue) circuit 11 that stores -times according to the processing order, and an instruction code prefetch pointer circuit 12 that operates in relation to the address actually indicated by the program counter 4.
Consists of spiky bones. The arithmetic logic circuit 1, the instruction code queue circuit 11, and the general-purpose register group 5 are each connected to an internal data bus 102 of the central processing unit, and the internal data bus 102 is connected to the It is connected to an external data bus 1002 shown in FIG. The program counter 4, instruction code prefetch pointer circuit 12, and general-purpose register group 5 are each connected to an internal address bus 101 of the central processing unit, and the internal address bus is connected to an address bus buffer (not shown).
through the external address bus 1001 shown in FIG.
connected to. Further, the output of the instruction code/queue circuit 11 is connected to the instruction decode circuit 2, and the timing/control circuit 3 generates various timing/control signals based on the instruction decode signal 104 output from the instruction decode circuit 2. , are connected to an external control bus 1003 shown in FIG. 2 through an internal control bus 103 and a control bus buffer (not shown).

Next, the actual operation will be explained. The output of the program counter 4 is supplied to the main memory device 7 through the internal address bus 101, and the program read control signal from the timing/control circuit 3 is supplied to the main memory device 7 through the internal control bus 103. According to the above address information and read control, the corresponding instruction code is read from the main memory 7, temporarily stored in the instruction code queue circuit 11, and then transferred to the instruction decode circuit 2. The instruction is decoded by the instruction decode circuit 2, an operation corresponding to the instruction is determined, and the information is sent to the timing/control circuit 3 as an instruction decode signal 104.
is input to. The timing/control circuit 3 controls the actual operations of various circuits according to the instruction decode signal 104. For example, when it becomes necessary to read data from the main memory 7, the timing/control circuit 3 , supplies 11 address information and a data read control signal to the data, and reads the required data from the main memory 7 into the central processing unit 6. Further, when arithmetic processing is required, data necessary for the arithmetic processing is set in the arithmetic logic circuit 1, and the required processing and the timing of the processing are controlled. Here, the period of operation of the central processing unit 6 in response to one instruction is generally referred to as a machine cycle. As described above, by sequentially executing machine cycle operations according to the program, the central processing unit executes the requested program operations stored in the main storage device.

Here, when the instruction code queue circuit 11 has sufficient capacity, the operation of the instruction code prefetch pointer circuit 12 reads out an instruction code earlier than the currently executed instruction code from the main storage device 7. Instruction code/
It continues to be stored in the queue circuit 11. By this operation, when the instruction code of the central processing unit is executed, the external address bus 10
The access time to 01 and external data bus 1002 is apparently negligible, and faster processing is possible than when this instruction code prefetch operation is not performed.

[Problem to be solved by the invention]

In the conventional central processing unit described above, the instruction code prefetch operation performed to speed up processing is a simple prefetch from the address of the program currently being executed.

Therefore, when executing a program in which a branch instruction is inserted, the instruction code
After clearing the instruction code stored in the queue circuit, it is necessary to read the instruction code from the program address at the time of branching and store it again, which takes time and makes it difficult for programs that have many branch instructions. When executed, there was a drawback that the advantage of speeding up processing by employing an instruction code queue circuit could not be taken advantage of.

[Means to solve the problem]

The central processing unit of the present invention includes: an arithmetic logic circuit that performs arithmetic processing using a composite program having a branch program between normal non-branch programs; a main storage device that stores instruction codes and data of the composite program; First and second instruction code prefetch pointer circuits that prefetch the instruction code of a program to be executed in advance from the main memory, and the instruction codes are temporarily stored by read signals from the first and second instruction code prefetch pointer circuits, respectively. first and second instruction codes, a queue circuit, and when a branch program is detected by monitoring instruction codes transferred from the main storage device, the second instruction code prefetch pointer circuit and the second instruction; code·
It has an instruction code check circuit that operates a queue circuit to temporarily store branch programs and RAM.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. 1st
The central processing unit of the embodiment shown in the figure includes an arithmetic logic circuit 1 that executes arithmetic operations, logical operations, etc., an instruction decoding circuit 2 that decodes a program for the central processing unit, and an instruction decoding circuit 2 that decodes instructions by the instruction decoding circuit 2. a timing/control circuit 3 that controls various timings and various circuits, a program counter 4 that manages sequential access and operation of programs stored in the main memory, and storage of processing results in the central processing unit. The area includes a group of general-purpose registers 5, an instruction code queue (Queue) circuit 11.21 that is placed before the instruction decode circuit 2 and temporarily stores instruction codes, and an area related to the address actually indicated by the program counter. Operating instruction code prefetch pointer circuit 12゜22 and instruction code queue times F! @1
Instruction code check circuit 13 provided in the input section of 1
It consists of The arithmetic logic circuit 1, the instruction code/queue circuit 11, 21, and the general-purpose register group 5 are each connected to an internal data bus 102 of the central processing unit, and the internal data bus 102 is connected to a data bus buffer (not shown).
The external data bus 1002 is connected to the external data bus 1002 through the external data bus 1002 . Program counter 4 and instruction code prefetch pointer circuit 12
．． 22 and general purpose register group 5 are each connected to an internal address bus 101 of the central processing unit, which in turn is connected to an external address bus through an address bus buffer (not shown). Further, the output of the instruction code/queue circuit 11.21 is connected to the instruction decode circuit 2, and the timing/control circuit 3 outputs various timing/control signals based on the instruction decode signal 104 output from the instruction decode circuit 2. The control bus 1003 is generated and connected to the external control bus 1003 shown in FIG. 2 through an internal control bus 103 and a control bus buffer (not shown).

Next, the operation of this embodiment will be explained. The state in which only the first instruction code queue circuit 11 and the first instruction code prefetch pointer circuit 12 are operating is a state in which no branch instruction appears in the program, as in the conventional example. In this case, no output instructions are particularly sent to the second instruction code queue circuit 21 and the second instruction code prefetch pointer circuit 22.

Next, the operation when a branch instruction appears in a program will be explained. The instruction code check circuit 13 always monitors the instruction code input to the first instruction code queue circuit 11, and checks whether a branch instruction appears in the instruction code. If a branch instruction appears in the instruction code, according to the program address information to be branched by that branch instruction,
The second instruction code prefetch pointer circuit 22 operates,
The instruction code is read from the main memory 7 and stored in the instruction code queue circuit 21. This branch instruction is transferred to the instruction decode circuit 2, and the operation of the branch program is determined. That is, during normal non-branching, the instruction code stored in the first instruction code queue circuit 11 is transferred to the instruction decoding circuit 2 and the normal program is executed, and when branching, the instruction code stored in the first instruction code queue circuit 11 is transferred to the instruction decode circuit 2, and the normal program is executed.
The instruction code stored in the queue circuit 21 is transferred to the instruction decode circuit 2 and the branch instruction is executed. next,
If there is no branch after the above operation, a steady operation is executed until the next branch instruction appears. On the other hand, at the time of branching, the instruction code stored in the second instruction code queue circuit 21 is executed. During this time, the program address information indicated by the first instruction code look-ahead pointer circuit 12 comes to indicate the address information after the branch, and the first instruction code
The instruction code after the branch is stored in the queue circuit 11, and after a certain period of time, the first instruction code look-ahead pointer circuit 12 and the instruction code queue circuit 11 are used again, returning to normal operation.

As explained above, the above-mentioned operations are repeatedly executed every time a branch instruction appears in the program, so the time required to access the external address/data bus can be ignored, and high-speed processing is possible.

〔Effect of the invention〕

As explained above, by providing two instruction code queue circuits, the present invention stores the non-branch instruction code and the branch instruction code even when executing a branch instruction in a program. , you can select one and execute its instruction code. Therefore, even when a program having a large number of branch instructions is executed, the processing speed can be increased.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
Block diagrams of the computer systems of the conventional example and the present example,
FIG. 3 is a block diagram of a conventional central processing unit. 1... Arithmetic processing circuit, 2... Instruction decoding circuit, 3
... timing control circuit, 4 ... program counter, 5 ... general-purpose register group, 6 ... central processing unit,
7... Main storage device, 8... Input/output device, 11.21
...Instruction code queue circuit, 12.22...Instruction code prefetch pointer circuit, 13...Instruction code
Check circuit, 101...internal address bus, 102
...Internal data bus χ, 103...Internal control bus, 104...Instruction decode signal, 1001...
External address bus, 2...external data bus, 3...external control bus.

Claims (1)

[Scope of Claims] 1. an arithmetic logic circuit that performs arithmetic processing using a composite program that has a branch program between ordinary non-branch programs; a main memory that stores instruction codes and data of the composite program; First and second instruction code prefetch pointer circuits that prefetch the instruction code of a program to be executed in advance from the main memory, and the instruction codes are temporarily stored by read signals from the first and second instruction code prefetch pointer circuits, respectively. first and second instruction code queue circuits, and when a branch program is detected by monitoring instruction codes transferred from the main memory, the second instruction code prefetch pointer circuit and the second instruction; A central processing unit comprising: an instruction code check circuit that operates a code queue circuit to temporarily store a branch program. 2. When the instruction code check circuit detects the instruction code of the branch program, the instruction code check circuit detects the instruction code of the branch program.
The operation of transferring the instruction code of the non-branch program stored in the queue circuit to the instruction decoding circuit is switched to instruction decode the instruction code of the branch program stored in the second instruction code queue circuit. 2. The central processing unit according to claim 1, wherein the central processing unit transmits the data to a circuit.