JPS60238937A - Precedence controlling device - Google Patents

Abstract

PURPOSE:To efficiently perform operand supply, by continuously suppying operands designated by a variable-length operand instruction by a necessary length and, at the same time, detecting the operand supply of the instruction through precedence control. CONSTITUTION:Operand starting address implementing means 201 and 202 implement the operand starting address of an instruction prefetched by an instruction prefetching instruction. The type of the prefetched instruction is identified by an instruction type identifying means and, if it is identified as a instruction for executing operand supply as the results of execution of accessing of plural memories, the order of the operand supply is designated by an operand supplying order type designating means 121. Then start of the operand supply of the succeeding instruction is designated in accordance with a judged result obtained by calculating the moment when the continuous operand supply is terminated and instruction type.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a pipeline type information processing device, and in particular, to specifying an arbitrary operand length using an instruction word or a register specified by the instruction word. This paper relates to an operand prefetching method for variable-length operand instructions that allows for variable-length operand instructions.

(Prior Art) In a conventional advance control device, when an instruction decoder identifies a variable-length operand instruction, the advance control section informs the operation section of the operand length specified by the variable-length operand instruction. Only the first word is supplied regardless, and the arithmetic unit sends out a memory request for supplying the remaining operands as necessary. The operand supply for the instruction following the arrived variable length operand instruction was performed by a start instruction from the arithmetic unit.

Therefore, the memory request is sent from the calculation unit LJcff
This is undesirable from the viewpoint of the loss cycle between L and O when operand data is returned to the arithmetic unit, and the need to improve the instruction execution speed in order to judge whether or not it is necessary to supply operands. Ta. In addition, by notifying the preceding control section of the end of the variable-length operand instruction, the supply of operands for the subsequent instruction is started, resulting in a loss equal to the number of pipeline stages between the preceding control section and the calculating section. There was a drawback that a cycle occurred.

(Objective of the Invention) An object of the present invention is to provide a variable-length operand instruction to a preceding control device so that operands specified for each instruction are sequentially transmitted for the necessary length in an order that facilitates processing in an arithmetic unit. The preceding control unit detects the end of operand supply for a variable-length operand instruction and immediately executes operand supply for a subsequent instruction, thereby eliminating the above disadvantages.
An object of the present invention is to provide a advance control device configured to effectively supply operands.

(Structure of the Invention) The advance control device according to the present invention is capable of detecting the continuous supply of operands of instructions for supplying operands through multiple memory accesses in pipelined information processing, and the end of the supply of operands of the above-mentioned instructions. It is something.

The advance control device according to the present invention includes operand start address generation means, instruction type identification means, reading means, operand supply order type designation means, control means, determination means, and next operand supply instruction means. 3-

The operand start address generation means is for generating an operand start address of an instruction prefetched by an instruction prefetch instruction.

The instruction type identification means is for identifying the type of the prefetched instruction.

The successive output means is for reading out the operand length by a command word or an indirect instruction from a command word.

The operand supply order type indicating means is for specifying the type of operand supply order when the instruction type identification means identifies an instruction that executes operand supply as a result of executing multiple memory accesses. be.

The control means is for controlling the generation of continuous operand addresses in accordance with the designation by the operand supply order type designation means.

The determining means is for calculating and determining the point in time when the continuous supply of operands by the control means ends.

The next operand supply instruction means is for instructing the start of operand supply for a subsequent instruction according to the result of the determination and the type of instruction.

(Actual flow side) Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram of the configuration of an embodiment of the advance control device according to the present invention. In FIG. 1, 101 is an instruction register, 110 is an instruction decoding block, 130 is an operand supply start instruction block, 150, 155, 15
6.157. , 261.262.263.

264 are registers, 230.271, 272 respectively
270 is a selector circuit, 270 is a counter circuit, and 20 is a selector circuit, respectively.
1. 202 is an operand address generation circuit, 260 operand length read block, and 290 is a branch circuit.

In FIG. 1, an instruction register 101 is a register that holds an instruction to be decoded, and an instruction decoding block 110 expands the information necessary to extract an operand and sends it to a decoding information register group 150. Address generation control information 1
Reference numeral 20 is input from the decoding register group 150 in the first cycle of the operand address generation stage to generate address information, and is control information for the operand address generation circuit 201.

This control information is designated corresponding to the instruction code of the instruction register 101 and sent to the control information register 156.

Operand supply type instruction information 121 instruction register 1
In the case of a fixed-length operand instruction that is specified corresponding to an instruction code of 01 and requires multiple memory accesses to supply operands, a certain b is an instruction word, and a certain h is an arbitrary register specified by the instruction word. In the case of a variable-length operand instruction that specifies an operand length of Control information register 15
Sent to 5. The instructions stored in the instruction register 101 are of a fixed length operand instruction type where operand supply ends with one memory access, a fixed length operand instruction type where operand supply ends with multiple memory accesses, and a variable length operand type. Chill with either. The control information register 155 includes instruction identification information 122 for identifying whether a given instruction is A-shifted or not.
It is also sent to the start instruction block 130 of the operand generation stage of the subsequent instruction.

Control information for the second and subsequent cycles of the operand address generation stage is given to the memory 250 in advance.

Operand supply type instruction information 121 is instruction identification information 1
When the control information register 155 is set as valid information by 22 and activated, the information given in advance by the predicted control information of the next cycle is set in the control information register 155 -7= and a self-running method is adopted. Therefore, the operand supply of the above instruction is continuously controlled. When the end of operand supply is detected, the contents of memory 250 are invalidated and free running is stopped. The contents of the memory 250 are composed of address generation control information for the second cycle and subsequent cycles of the operand address generation stage, control information 251 for the operand address generation circuit 202, and control information 252 for monitoring the end of operand supply for variable length operand instruction types. Persevere.

No end detection circuit is used for the end monitoring control information 252,
It also has a function that can directly report completion to the operand supply start instruction block 130 of the subsequent instruction. The operand address generation circuit 202 is composed of an address generation circuit including registers, and instructions for the operation mode in the block and instructions for setting the registers can be arbitrarily set by the control information register 261.

When the operand address generation control information 250 and the termination monitoring control information 252 are valid information, these pieces of information are stored in the control information registers 261 and 262, respectively.
is set to When the instruction held in the instruction register 101 is identified as being of the variable length operand instruction type according to the instruction identification information 122, the operand length specified by the instruction word or the register specified by the instruction word is the operand length specified by the instruction word or the register specified by the instruction word. It is read by the long read block 260, and the operand length register 263, a certain b, is set to 264 as valid information. Each time the counter 270 sends a memory request for operand supply under the control of the control information register 262, the effective operand length set in the operand length register 263 or 264 is counted down, and the valid operand length is set in the operand length register 263 or 264. Set repeatedly. The input selectors 271 and 272 of the counter 270 are
This is provided to arbitrarily set the calculation mode.

If the end address of the operand is required, use the control information register 261 and write the operand length register 2.
64. The contents of 264 are set in advance to the signal lines 502 and 50.
3 to the operand address generation circuit 202 and held there.

When the counter 270 detects the end of operand supply according to the instruction of the control information register 262, this detection signal is reported to the subsequent instruction start instruction block 130 via the signal line 501, and the operand address generation stage of the subsequent instruction is Used to instruct import into. The operand supply start instruction block 130 for the subsequent instruction monitors the information of the operand address generation stage, and if the stage is already vacant or the stage is definitely completed in the above cycle, the instruction decoding, A permission indication is issued to allow subsequent instructions present in the stage to proceed to the operand generation stage in the next cycle.

Address information generated by the operand address generation circuits 201 and 202 is selected by a selector 230 and sent to an address exchange section (not shown).

When the information in the constraint information register 261 is valid, the selector 230 selects the operand address generation circuit 202.

When a fixed-length operand instruction that completes operand supply with one memory access is set in the instruction register 101, the information necessary for fetching the operand is developed by the instruction decoding block 110, and the decoding register group 150
will be sent to.

In the cono cycle, the address generation control information 120 of the above instruction is read out via the signal line 161, and
2 to the control information register 156. Since the instruction type is identified by the instruction identification information 122, the operand supply type instruction information 121 becomes invalid, and a setting instruction for the flip 70 knob 157 is sent out via the signal line 163.

In the subsequent instruction start instruction block 130, A indicates whether the instruction preceding the above instruction has already finished in the operand address generation stage (8 indicates that the instruction that precedes the above instruction has already finished in the operand address generation stage (8 is the case where the completion is certain in the above cycle). In this case, a signal instructing the above instruction to be taken into the operand address generation stage is sent via signal lines 164 and 165.In the next cycle, the instruction signal on the signal lines 164 and 165 causes the above instruction to be taken into the operand address generation stage. Instruction information is applied to the operand address generation circuit 20 via signal lines 301 and 302, selected by the output signal selector 230 on the output signal line 303, and sent to the address conversion section (not shown) via the signal line 310. sent to.

In the above cycle, when the subsequent instruction start instruction signal is reported to the subsequent instruction start instruction block 130 via the signal line 304, a signal is sent to the operand address generation stage capture instruction signal lines 164 and 165, The operand address generation stage ends. When a fixed-length operand instruction whose operand supply is completed by multiple memory accesses is set in the instruction register 101, the instruction decoding block 110 expands the information necessary for fetching the operand and sends it to the decoding register group 150. In the above cycle, 12- the address generation control information 120 of the above instruction is sent to the signal line 161.
and sent to the control information register 156 via the signal line 162. Since the instruction type is identified by the instruction identification information 122, the operand supply type instruction information 121 is sent to the control information register 155 as valid information via the signal line 166. A reset signal is sent to the flip-flop 157 via the instruction identification information signal line 163.

As already explained, when the instruction to take in the operand address generation stage of the above instruction is sent via the signal lines 164 and 165, the information of the above instruction taken into the operand address generation stage in the next cycle is the operand address. The output signal is sent from the generation circuit 201 via signal lines 301 and 302, and the output signal on the output signal line 303 is selected by the selector 230 and sent to the address exchange unit (not shown) via the signal line 310. Ru. At the same time, the output signal on the output signal line 305 of the operand address generation circuit 201 is sent to the operand address generation circuit 202. In the above cycle, the control information register 155
According to the valid information set in the signal lines 251, . 25
Control information is read from signal lines 306 and 2, respectively.
Control information register 261 via 307 and 308;
262, 155.

In the above command, the counter control information among the termination monitoring control information on the signal line 252 is ignored, and the termination is detected based on the operand supply termination information. In the next cycle, the operand address generation circuit 202 is used to obtain operand address information in response to a control signal sent from the control information register 261 via the signal line 309.

At this time, the output signal line 31N is selected by the selector 230, and is sent to the address conversion unit (not shown) via the signal line 310, and is also returned to the operand address generation circuit 202 via the signal line 315. . In the next cycle, according to the information set in the control information register 155 via the signal line 308, the signal lines 251, 2
Control information is read out via 52, and the same operation as in the previous cycle is performed. By repeating the above operations, the necessary table operands are continuously supplied. During the final operand address generation cycle in the above instruction, operand supply end information is issued from the control information register 262, and is sent to the signal lines 164, 16 via the signal line 31.2.
The operand address generation stage of the instruction is completed by sending an instruction signal on 5, invalidating the information stored in memory 250 during the cycle. When the variable length operand instruction is set in the instruction register 10, the instruction decoding block 110 expands the information necessary for fetching the operand and sends it to the explanation register group 150. In the above cycle, the address generation control information 120 of the above instruction is read out via the signal line 161 and sent to the control information register 156 via the signal line 162.

As described above, since the instruction type is identified in the instruction identification information 122, the operand supply echo instruction information 121 is sent to the control register 155 as valid information via the signal line 166. A reset signal for the flip-flop 157 is sent out via the signal line 163 based on the instruction identification information. The operand length read by the operand length read block 260 is sent to the operand length registers 263, 264 as valid information via the signal lines 312, 313 according to the instruction identification information.
sent to. As already explained, the instruction to take in the operand address generation stage of the above instruction is sent to the signal line 164.
. The output signal line 303 is selected by the selector 230, and its contents are sent to an address converter (not shown) via a signal line 310. At the same time, the output of the operand address generation circuit 201 is sent to the operand address generation circuit 202 via the signal line 305.
It is also sent to In the above cycle, the control information 251 and 252 are read out based on the valid information set in the 16-control information register 155, and the signal line 306 is read out.
, 307 , 308 to the control information register 261
, 262 , 155 . bL in next cycle
At n, a control signal is sent from the control information register 261 to the operand address generation circuit 202 via the signal line 309, the operand address generation circuit 202 obtains operand address information, and the output signal line 311 is selected by the selector 230. The output signal of the selector 230 is sent to an address converter (not shown) via a signal line 310. At the same time, this signal is returned to operand address generation circuit 202 via signal line 315.

In other words, the control information sent from the control information register 262 is transmitted via the signal line 316 to the selectors 271, 272,
counter 270 and operand length register 2
63 and 264, and these are controlled to continuously monitor whether or not the operand supply is completed.

Since the calculation mode in the counter 270 can be arbitrarily set by the control information register 262,
In this embodiment, the operand supply unit is used as the operation number, and the point in time when the content of the A1 counter 27o becomes zero or negative is the point in time when the end is detected. In this cycle, control information 251 and 252 are read out by the signal line 308,
Works the same as the previous cycle. By repeating this operation, the necessary operands are continuously supplied. In a specific cycle A, when the contents of the counter 270 become zero or negative and an end condition is detected, the above condition is reported to the subsequent instruction operand supply start instruction block 130 via the signal line 501, and the operand Address generation stage capture instruction signals 164 and 165 are sent out, and the information in the memory 250 in the above cycle is invalidated. This completes the operand address generation stage of the above instruction.

In a variable length operand instruction using two operands, the above method is performed by repeating a specific pattern consisting of supplying the two operands, and the counter 270
If a condition is detected in which the supply of one operand ends, the end detection information on the signal line 501 is invalidated by the operand supply end information on the signal line 312. At the same time, the end detection information 501 activates the branch circuit 290 to change the control information to a Luha turn that supplies only one operand, thereby making it possible to continuously supply operands.

Since memory access is performed in units of words, destructive duplication of operands may occur in some instructions, and the advance control section may not be able to supply operands. In order to detect the above information, means for calculating the operand length is provided inside the address generation circuit 202. Although there is a register in the address generation circuit 202, the start address of both operands and the subsequent address necessary for the duplication test are set in a different register from the one used for address calculation and compared. A means of redundant testing will be provided. Use of redundant test measures
19- The mink uses the detection instructions present within the control information 251. If the preceding control unit determines that preemption is not possible by the duplication test means, the determination is reported via the signal line 604, and the control information 250 is invalidated. The above control information is reported to the arithmetic unit via a signal line 604.

The calculation unit performs tests as necessary before executing calculations, and when a signal is sent onto the signal line 604,
The arithmetic unit cancels the memory request of the preceding control unit, and uses the signal line 605 to set control information in order to instruct memory access using the start address left inside the operand address generation circuit 202. .

That is, a memory request is sent and an instruction is executed under the control of the arithmetic unit.

For some instructions, the maximum operand length that will be used in the preceding control section is known, but the operand length of the instruction actually used is determined by the operation block and the operation block. There are two types: one that requires a memory request after preprocessing, and one that requires a memory request after preprocessing. In the above, the signal line 601°60 from the calculation unit
2 sets the address, argument, request sending procedure, and request count in the address generation circuit 202 via the registers 155 and 263;
, 264 and return control of memory access to the preceding control unit, it becomes possible to supply operands continuously and at high speed.

(Effects of the Invention) As described above, the present invention continuously supplies the required length of operands specified by variable-length operand instructions, and detects the end of operand supply for the instruction by advance control. This has the great effect of making it possible to supply this operand continuously and efficiently in any instruction.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the advance control device according to the present invention. 101...Instruction register 110...Instruction decoding block 120, 251...Operand address generation control information 121...Operand supply type instruction information 122...
・Instruction identification information 252...Operand supply end monitoring control information 130・
...Operand supply start instruction block 150.155,
156, 157, 261, 262, 263, 264...
・Registers 230, 271, 272...Selector circuit 270
...Counter circuit 201.202...Operand address generation circuit 26
0... Operand length read block 290... Branch circuits 161-166, 301-316, 501-503
, 601-605...Signal line patent applicant NEC Corporation representative Patent attorney Hisashi Inoro 23-

Claims (1)

[Claims] In a preemptive control device capable of detecting the continuous supply of operands of an instruction for supplying operands by multiple memory accesses in pipelined information processing and the end of the supply of operands of the instruction, the prefetching by an instruction prefetch instruction is performed. operand start address generation means for generating an operand start address of a prefetched instruction; instruction type identification means for identifying the type of the prefetched instruction; and an operand for specifying the type of order of operand supply when the instruction type identification means identifies the instruction to execute operand supply as a result of executing a plurality of memory accesses. supply order type designation means; control means for controlling generation of continuous operand addresses performed in accordance with the specification by the operand supply order type designation means; and calculation of a point in time at which continuous operand supply by the control means ends. and a next operand supply instruction means for instructing the start of operand supply for a subsequent instruction according to the type of the instruction based on the result of the determination. Preceding control device.