JPS6212534B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an instruction control device for an arithmetic processing device equipped with a plurality of independent arithmetic circuits, and in particular, when a subsequent instruction starts executing an operation, Compare the output operand register number of the preceding instruction with the input operand register number of the subsequent instruction,
Inspecting register interference in an instruction control device configured to detect failures for a matching circuit that inspects register interference to determine whether the subsequent instruction uses the arithmetic result of the preceding instruction when processing the subsequent instruction in parallel at the same time as the preceding instruction. The present invention relates to a fault detection method for matching circuits.

[Prior art and problems]

2. Description of the Related Art Ultrahigh-speed arithmetic processing devices, particularly vector processing devices, include an instruction control device that includes a plurality of arithmetic circuits and performs parallel processing of vector instructions between the respective arithmetic circuits. This instruction control device is equipped with a matching circuit that compares operand register numbers between a previously executed arithmetic instruction group and a subsequent unexecuted instruction to check for register interference. The matching circuit is designed to send out a matching signal when the output operand that is the result of the operation of the preceding instruction is used as the input operand of the succeeding instruction because the operand register numbers of the two match. When the match signal is sent, the start of the calculation of the subsequent instruction is awaited, and the calculation result of the preceding instruction is output as an output operand before the calculation of the subsequent instruction is started. However, if the output operand of the operation result of the preceding instruction is not used as the input operand of the subsequent instruction, the operand register numbers of the two do not match, so the matching signal of the matching circuit cannot be obtained, and the operation of the subsequent instruction is immediately performed. is started. In this way, processing performance is improved by performing parallel processing when a subsequent instruction calculates an operand that does not require the use of the calculation result of the preceding instruction.

However, even though the output operand of the operation result of the preceding instruction is used as the input operand of the subsequent instruction, if the matching circuit fails and no match signal is sent out, the operation result of the preceding instruction will be used as the output operand. The operation of the subsequent instruction will begin immediately before it is output. In this case, the chain of oprandos cannot be processed correctly, resulting in an erroneous result, but conventionally there has been no suitable method for testing matching circuits.

[Purpose of the invention]

The present invention is based on the above considerations, and includes:
It is an object of the present invention to provide a failure detection method for a coincidence circuit that inspects register interference in an instruction control device that can detect failures of a coincidence circuit that inspects register interference by adding a simple configuration.

[Structure of the invention]

For this purpose, the failure detection method of the matching circuit for checking register interference in the instruction control device of the present invention is as follows.
The output operand register number of the preceding instruction during execution of an arithmetic processing unit equipped with multiple independent arithmetic circuits is compared with the input operand register number of the subsequent instruction before execution of the operation, and if they match, Execute the subsequent instruction after the preceding instruction outputs an output operand, and if there is no match, check for register interference in order to execute the subsequent instruction even before the preceding instruction outputs the output operand. In an instruction control device equipped with a circuit, a preceding register stores an output operand register number of the preceding instruction during execution of an operation, a succeeding register stores an input operand register number of the succeeding instruction, the contents of the preceding register and the above. It includes a comparison circuit that compares the contents of a subsequent register with the contents of a subsequent register, and a failure detection circuit, and the failure detection circuit detects a match when the subsequent instruction starts executing an operation, and the preceding instruction detects an output operand. The present invention is characterized in that it is configured to send out a failure detection signal of the coincidence circuit on the condition that it has not yet output.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing one embodiment of the present invention, and FIGS. 2 and 3 are time charts showing an example of the operation of one embodiment of the present invention. In Figure 1, QR is a subsequent instruction information register, 1 is a pre-operation instruction management section, and 2 is a
and 3 are a calculation instruction management unit, 4 is a failure detection unit, 5 is an instruction transmission control circuit, 6 and 7 are write start flags,
8 and 9 are inverters, 10 to 15 are matching circuits, 16 to 21 are AND gates, 22 and 2
3 is an OR gate, 24, 25, AR and MR are registers, 26 is a delay register, 27 and 28
is a timing circuit, OP is an instruction code, R1 is an output operand register number, R2 is a first operand register number, and R3 is a second operand register number.

In Figure 1, subsequent instruction information register QR
When the instruction information is sent, the instruction code is
OP, output operand register number R1, first
The operand register number R2 and the second operand register number R3 are respectively stored, and the stored instruction code OP and output operand register number R1 are sent to the instruction transmission control circuit 5, and the first operand register number R2 and the second operand register number R3 are respectively stored. Register number R2 is sent to match circuits 10, 12 and register 24, and second operand register number R3 is sent to match circuits 11, 1.
3 and is sent to register 24. The command transmission control circuit 5 checks all conditions for transmitting a command, such as whether the arithmetic circuit is vacant or there is register interference, and if the conditions are met, transmits the command. When execution starts, the output operand register number R1 being executed is sent from the instruction generation control circuit 5 to the registers AR, MR, R1 and the timing circuit 27. The in-operation instruction management unit 2 manages management information during addition execution, and stores the information in registers.
The output operand register number R1 of the instruction that is being added is stored in AR, and when writing of the operation result begins, the write start flag 6 is turned on (logic "1").
be made into Similarly, in the operation instruction management unit 3, management information during the execution of multiplication is managed, and the output operand register number R1 of the instruction under execution of multiplication is stored in the register MR, and when writing of the operation result starts, a write start flag 7 is set. is turned on (logic "1"). Output operand stored in register AR
Register number R1 is sent to matching circuits 10 and 11, and the output operand stored in register MR.
Register number R1 is sent to matching circuits 12 and 13. The contents of write start flag 6 are inverter 8.
The output of matching circuit 10 is sent to the other input terminal of AND gate 16, and the output of matching circuit 11 is sent to the other input terminal of AND gate 17. . Matching circuits 12 and 13, AND gates 18 and 19, and inverter 9 are similarly connected. The outputs of AND gates 16 to 19 are supplied to each input terminal of OR gate 22, and the output of OR gate 22 is sent to command generation control circuit 5. In the failure detection unit 4, the first operand register number R2 and the second operand register number R3 are stored in the register 24.
5 stores the output operand register number R1 under execution of the operation. The delay register 26 is
The output operand register number R1 stored in the register 25 is stored with a delay of one timing. The output operand register number R1 stored in the delay register 26 is changed to the first operand register number R1 by the matching circuit 14.
2, and is compared by match circuit 15 with second operand register number R3. and,
The outputs of the coincidence circuit 14 as well as the outputs of the timing circuits 27 and 28 are input to the AND gate 20;
The outputs of the coincidence circuit 14 as well as the outputs of the timing circuits 27 and 28 are input to the AND gate 21;
The outputs of AND gates 20 and 21 are sent out through OR gate 23 as a fault detection signal.

Next, the operation will be explained. In the pre-operation instruction management unit 1, when an instruction is started to be executed by the instruction transmission control circuit 5, the output operand register number R1 of the instruction is transmitted to the instruction management units 2 and 3 during operation and the failure detection unit 4.
is sent to the subsequent instruction information register QR.
New subsequent instruction information is stored in . The output operand register number R1 during the operation, the first operand register number R2, and the second operand register number R2 of the subsequent instruction stored in the subsequent instruction information register QR.
Register number R3 means matching circuits 10 to 13.
If no matching signal is sent out from any of the matching circuits 10 to 13, i.e.
If the outputs of any of the matching circuits 10 to 13 are logic "0", an output of logic "0" is sent from the OR gate 22 to the command generation control circuit 5.
However, for example, if the output operand register number R1 of the instruction during execution of addition matches the first operand register number R2 of the subsequent instruction, the output of the matching circuit 10 becomes logic "1". As a result, as shown in FIG. 2, while the write start flag 6 is off (logic "0"), the AND condition of the AND gate 16 is satisfied, and a coincidence output signal of logic "1" is output through the OR gate 22. The command is sent to the command transmission control circuit 5. Then write start flag 6
When the inverter 8 is turned on, the output of the inverter 8 becomes logic "0", and the AND condition of the AND gate 16 no longer holds true. In the command generation control circuit 5, when a coincidence output signal of logic "1" is sent from the OR gate 22, the start of execution of the subsequent instruction is waited, and the coincidence output signal from the OR gate 22 becomes logic "0". When this occurs, execution of the subsequent instruction begins unless there are other waiting conditions.

The output operand register number R1 of the instruction being executed is the first operand register number R2 or the second operand register number R3 of the subsequent instruction.
If the logical "0" signal is sent from the OR gate 22 to the command issuing control circuit 5 even though the numbers match, the execution of the subsequent command is started. At that time, a failure detection signal of logic "1" indicating failure detection is sent from the OR gate 23 of the failure detection section 4. For example, as shown in Figure 3, the addition instruction
When the subsequent instruction of VA is the multiplication instruction VM, when the addition instruction VA is stored in the subsequent instruction information register QR and execution starts at the next timing, the multiplication instruction VM is stored in the subsequent instruction information register QR at the same time. . At this time, in the failure detection section 4, the contents shown in FIG. 3 are set in the registers 24 and 25. The timing circuit 27 outputs a logic "1" for one timing period each time a new instruction starts to be executed, and the timing circuit 28 outputs a logic "1" for a predetermined number of timings after the timing circuit 27 outputs a logic "1". The output becomes logic "1" only for a period (a period until the write start flag is turned on). Therefore, the multiplication instruction is immediately executed at the next timing.
When the VM also starts execution, the first operand register number VMR2 and the second operand register number VMR3 of the multiplication instruction VM whose execution has started are stored in the register 24. Also, the output operand register number VMR1 of the multiplication instruction VM that has started execution is stored in the register 25, but the output operand register number VMR1 of the addition instruction VA one timing before is stored in the delay register 26.
VAR1 is stored and is used as a comparison input for matching circuits 14 and 15. When a coincidence output of logic "1" is obtained in the coincidence circuit 14 or 15, the failure detection signal of logic "1" is output on the condition that the outputs of the timing circuits 27 and 28 are logic "1". - Output from gate 20 or 21 through OR gate 23. As is clear from the time chart shown in Figure 3, even if the multiplication instruction VM starts execution after several timings,
While the output of the timing circuit 28 is logic “1” (before the timing when the write start flag turns on)
If so, you will get similar output results. In this way, the present invention is capable of determining the output operand register number of the preceding instruction and the start of execution on the condition that the preceding instruction has not yet output its output operand (the write start flag is off) when the subsequent instruction starts executing. A failure is detected by comparing the input operand register number of the subsequent instruction.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, if a chain of operands is not processed correctly, a failure can be detected as soon as the instruction starts executing.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing one embodiment of the present invention, and FIGS. 2 and 3 are time charts showing an example of the operation of one embodiment of the present invention. QR...Subsequent instruction information register, 1...Pre-operation instruction management unit, 2 and 3...In-operation instruction management unit, 4...
...Failure detection unit, 5...Command transmission control circuit, 6 and 7
...Write start flag, 8 and 9 are inverters, 1
0 to 15...matching circuit, 16 to 21...
And gate, 22 and 23...or gate,
24, 25, AR and MR... register, 26...
Delay registers, 27 and 28... timing circuit, OP is instruction code, R1... output operand register number, R2... first operand register number, R3... second operand register number.

Claims (1)

[Claims] 1 Compare the output operand register number of the preceding instruction during execution of an arithmetic processing unit equipped with multiple independent arithmetic circuits and the input operand register number of the subsequent instruction before execution of the operation, and if they match, executes the subsequent instruction after the preceding instruction outputs its output operand, and if they do not match, checks for register interference in order to execute the subsequent instruction even before the preceding instruction outputs its output operand. In an instruction control device equipped with a matching circuit, a preceding register stores an output operand register number of the preceding instruction during execution of an operation, a succeeding register stores an input operand register number of the succeeding instruction, and contents of the preceding register. and a failure detection circuit, the failure detection circuit detects a match when the subsequent instruction starts executing an operation, and the preceding instruction outputs the 1. A failure detection method for a matching circuit for inspecting register interference in an instruction control device, characterized in that the matching circuit is configured to send out a failure detection signal on the condition that an operand has not yet been output.