JPS62102340A - Coincidence detection circuit - Google Patents

Abstract

PURPOSE:To debug a program efficiently even in a program loop by outputting a coincidence detection signal when a desired program address to be detected appears by as many times as specified. CONSTITUTION:An external specified value (n) (=m-1) is set in a counter 21 and a detection address on a signal line 12 is set in a register 11 so as to detect a program address which coincides with the desired detected address appearing by (m) times (m>0). A comparator 16 compares the held contents (detected address) of the register 11 with a program address led to an input B. When the number of times of appearance of coincidence reaches (n), the counted value of a subtracting counter 21 becomes 0. A NOR gate 26 makes a signal line 27 true and opens an AND gate and a matching signal MATCH2 coincides with the state of a matching signal MATCH1 outputted by the comparator 16. Namely, the signal MATCH2 becomes true for the first time after the comparator 16 detects the [n+1(=m)]th coincidence.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a match detection circuit such as an address match detection circuit that detects the moment when a microinstruction at a designated address is executed.

[Technical Background of the Invention J51] When dealing with data processing equipment, microprograms,
When debugging hardware or the like that runs in synchronization with hardware, you may want to detect the moment when a microinstruction at a specified address is executed, stop the machine (CPU) at that moment, and examine the contents of registers, etc. A match detection circuit called an address match detection circuit is used to detect this instant.

Now, the conventional address match detection circuit uses a register (
It generally consists of an address match register) and a comparator that compares the contents of the register with the address on the microprogram address bus (program address).

In this type of address match detection circuit, the match detection signal of the comparator is used as the address match signal, and it is possible to stop the machine (or trigger a logic analyzer, etc.) when the program address matches the detected address. Become.

[Problems with the Background Art] However, in conventional address match detection circuits, if the detected address exists in a program loop, for example, an address match signal is output every time the program goes around the loop. . For this reason, it was not possible to perform a match during the nth execution of the loop, making it difficult to perform efficient debugging.

[Purpose of the Invention] This invention was made in view of the above circumstances, and its purpose is to make a match detection signal (match signal) true when a program address that matches a desired detection address appears a specified number of times. It is an object of the present invention to provide a coincidence detection circuit which can improve the efficiency of debugging microprograms and hardware running in synchronization with the microprograms.

[Summary of the Invention] According to the present invention, there is a register that stores data such as an address for matching, and the contents of this register are compared with data on a match detection circuit data line such as a microprogram address bus to find a match. A match detection circuit is provided, comprising: a comparator for detecting. The minus number calculation circuit is further provided with a counter that performs a counting operation in response to coincidence detection by the comparator, and a gate circuit. This gate circuit outputs a data coincidence signal (match signal) in accordance with the match detection result of the comparator when the counter has performed a count operation an externally specified number of times.

[Embodiment of the Invention] FIG. 1 shows the configuration of an address match detection circuit according to an embodiment of the present invention, in which 11 holds a detection address (address for which a match is to be detected) supplied from a signal line 12. register (address match register: AMR
> is. The output of the two-man AND gate 13 is connected to the clock terminal of the register 11. One input of the AND gate 13 is connected to a signal line 14 that guides a clock signal of the circuit to be detected, and the other input is connected to a signal line 15 that controls the AND gate 13. On the other hand, the output of register 11 is connected to the input of comparator 16. The B input of the comparator 16 is connected to a signal line 17 leading to the address on the microprogram address bus of the circuit to be detected. A match result output terminal of the comparator 16 is connected to a signal line 18 from which a match signal MATCHI is derived.

The above configuration (the part surrounded by the broken line in FIG. 1) is a conventional address match detection circuit part, and in this embodiment, the following circuit part is newly added.

Reference numeral 21 denotes a counter, for example, a subtraction counter, to which an externally designated value supplied via a signal line 22 is initially set. The clock terminal of the subtraction counter 21 is connected to the signal line 14, the load enable terminal LE is connected to the signal line 23, the count enable terminal CTE is connected to the signal line 24, and the output (counter output) is connected to the signal line 25.

The input of a NOR gate 26 that detects that the data on the signal line 25 (the count value of the subtraction counter 21) is zero is connected to the signal line 25, and the output of the NOR gate 26 is connected to the signal line 27. An input of an inverter 28 and one input of a two-person gate 29 are connected to the signal line 27 . The other input of the AND gate 29 is connected to the signal line 18, and the output of the AND gate 29 is connected to the signal line 30 from which a match signal MATCH2 indicating address matching is derived. Also, the output of the inverter 28 is 2
The driver is connected to one input of the AND gate 31, and the other input of the AND gate 31 is connected to the signal line 18. The output of the AND gate 31 is connected to the signal line 24.

Next, the operation of the configuration shown in FIG. 1 will be explained.

The program address matching the desired detection address is m
If it is desired to detect that the number of times (m is an integer satisfying m>O) has appeared, an external specified value indicating n <= m-1) is supplied to the subtraction counter 21 via the signal line 22, and
Make true. As a result, the designated value n is set in the anti-itch counter 21. Similarly, the detected address is supplied to the register 11 via the signal line 12, and the signal line 15 is made true. When the signal line 15 becomes true, the AND gate 13 opens and the signal g1
The clock signal on 14 is supplied to the clock terminal of register 11 via AND gate 13. As a result, the detected address on the signal line 12 is set in the register 11.

The comparator 16 inputs the contents held in the register 11 (detected address) supplied to its six inputs and the program address led via the signal line 17 to its B input (in synchronization with the clock signal on the signal line 14). Each time a match is detected, a high-level match signal MATCH1 indicating that the program address matches the detected address is output to the signal line 18.

Now, the count value of the subtraction counter 21 is supplied to the NOR gate 26 via the signal line 25. Noah Gate 26 is
The signal line 27 is made true (high level) only when the count value of the subtraction counter 21 is O (all zeros). Therefore, the signal line 27 becomes false until the count value of the subtraction counter 21 reaches O.

When the signal line 27 is false, the AND gate 29 closes and the state of the match signal MATCH1 output from the comparator 16;
That is, the match signal MATCH2 on the signal 30 becomes false regardless of the match detection result of the comparator 1G.

In this embodiment, instead of the match signal MATCHI, which is the match detection signal of the comparator 16, the match signal MATCH2, which is the output signal of the AND gate 29, is used as the true address signal.
It is used as a match signal, that is, a signal for stopping the CPU and reading out its status, or as a 1 to trigger signal for a logic analyzer, etc.

Therefore, when the signal line 27 is false, that is, when the count value of the subtraction counter 21 is not O, the comparator 16
Even if an address match is detected in , it is not considered an address match.

If signal line 27 is false, the output of inverter 28 will be true. When the output of the inverter 28 becomes true, the AND gate 31 opens and the match signal MA output from the comparator 16
TCH1 is supplied to the count enable terminal CTE of the subtraction counter 21 via the AND gate 31 and the signal line 24. When the signal line 24 is true, that is, when the comparator 16 detects a match while the count value of the subtraction counter 21 is not O, the subtraction counter 21 operates according to the clock signal supplied through the signal line 14. Perform a subtraction operation (-1).

Eventually, the number of occurrences of the program address that matches the detection address set in the register 11 becomes n (-m
-1) times, and therefore, when the number of address-number outputs of the comparator 16 reaches n times, that is, when the subtraction counter 21 performs n subtraction operations, the count value of the subtraction counter 21 becomes 0. When the count value of the subtraction counter 21 becomes 0, the NOR gate 26 makes the signal line 27 true. Signal line 2
7 becomes true, the AND gate 29 opens and the match signal M
ATCH2 is the match signal M output from the comparator 16.
It comes to match the state of ATCH1. Therefore, for the match signal MATCH2, the comparator 1G has n+1 (=m
) It becomes true for the first time when the match signal M AT CH1 is made true after the second match detection is performed.

That is, the match signal MATCH2 can indicate an arbitrary m-th address match. Note that when the signal line 27 becomes true, the AND gate 31 closes and the signal line 24 becomes false. As a result, the subtraction operation of the subtraction counter 21 is prohibited.

As is clear, when the subtraction counter 21 is set to O, the AND gate 29 becomes open from the beginning and the subtraction operation of the subtraction counter 21 is prohibited from the beginning. It becomes true each time.

Although the embodiment described above has been described in the case where the present invention is applied to an address match detection circuit that detects a match between addresses of microprograms, the present invention is not limited to this. That is, the present invention not only uses an address match detection circuit that detects a match between addresses of macro instructions, but also counts the number of occurrences of a specific value consisting of normal data, for example, data on a data line, and detects the moment when a specific value has appeared a specified number of times. It can also be applied to a data match detection circuit that detects.

[Effects of the Invention] As detailed above, according to the present invention, the match detection signal (match signal) can be set to true especially when a program address that matches a desired detection address appears a specified number of times. When the address to be detected exists in a program loop, it is possible to improve the efficiency of debugging a microprogram and hardware running in synchronization with the microprogram.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. 11...Register (A~IF', ), 13.29
．． 31...AND gate, 16...Comparator, 21.
...Reduction counter, 26...Noah Gate. Applicant's representative Patent attorney Takehiko Suzue Figure 1

Claims (1)

[Claims] A register that stores matching data, a comparator that detects a match by comparing the contents of this register with the data on the data line to be matched, and a counter that performs a counting operation in response to the match detected by this comparator. and a gate circuit that outputs a data coincidence signal in accordance with the coincidence detection result of the comparator when the counter has performed a count operation an externally designated number of times.