KR0145893B1 - The apparatus of preventing overflow - Google Patents

Abstract

The present invention relates to an overflow prevention device, comprising: a numerical condition detection circuit for detecting a condition in which an overflow occurs in an accumulator by inputting a negative flag, an overflow flag, a carry flag, and the like, and an output of the condition detection circuit of the number. It is composed of register write function selection circuit that enables or disables the decoder to be written. When accumulating, it detects large or equal condition and small condition by using negative, overflow and carry bit of status register. If the overflow occurs by selecting the register write function according to the detected condition, the overflow prevention device is provided to provide an instruction to store the result in the destination register if the overflow does not occur without updating the register designated by the accumulator. It is about.

Description

Overflow protection device

1 is a flowchart of microcode for performing a conventional general operation,

2 is a graph between the time when a conventional overflow occurred and the accumulator value,

3 is a configuration circuit diagram of an overflow prevention apparatus according to an embodiment of the present invention,

4 is a flowchart of microcode for performing an instruction for preventing overflow according to an embodiment of the present invention.

5 is a graph between time and accumulator value when overflow is prevented according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

10: condition detection circuit of numbers 11: condition detection circuit of signed numbers

12: upper and lower limit detection circuit of the number 13: decoder

14: 4-input NAND gate 20: resistor write function selection circuit

21: decoder 22: enable signal supply circuit

23: decoder

The present invention relates to an overflow prevention device. More specifically, when accumulating, a negative or overflow condition of a status register is detected using a negative, overflow or carry bit. An overflow prevention device that does not update a register designated by an accumulator when an overflow occurs by selecting a write function.

Hereinafter, a conventional overflow prevention method will be described with reference to the accompanying drawings.

FIG. 1 is a flow chart of a microcode performing a conventional general operation, and FIG. 2 is a graph between time and accumulator values when a conventional overflow occurs.

As shown in FIG. 1, a program counter (PC) is first increased, and a value of a destination register is input to an arithmetic logic unit (ALU). In addition, immediate data is input to the arithmetic logic unit. The operation result of the arithmetic logic unit is input to the destination register.

The overflow that occurs during this process is shown in Figure 2.

This failure to prevent overflow results in a sudden change in the accumulator value beyond the register's bit range.

When performing a certain algorithm by designating one register as an accumulator using a conventional microprocessor, the accumulator overflows, and this overflow causes the accumulator to overflow the sign bit. Toggles can sometimes make the value of an accumulator meaningless and cause the algorithm itself to malfunction.

In this case, the general microprocessor has solved the problem by retrieving the input data well so that no overflow occurs, or by checking the overflow before accumulating.

However, in the above-described conventional technique, a method of preventing the occurrence of overflow by searching the input data in advance is difficult to retrieve all the input data in a situation where it may not occur, and also checks the overflow before accumulating. Since the method is the same as repeating the accumulation algorithm twice, there is a problem in that the execution time of the algorithm, the size of the code, and the hardware burden are required.

Accordingly, an object of the present invention is to solve the above-mentioned conventional problem, and to provide an overflow prevention device that does not update a register designated as an accumulator when an overflow occurs when accumulating.

As a means for achieving the above object, the constitution of the present invention is a numerical condition detection circuit which detects a condition in which an overflow occurs in an accumulator by inputting a negative flag, an overflow flag, a carry flag, or the like, and detecting the condition of the number. And a register write function selection circuit for enabling or disabling the decoder on which the write function is to be performed using the output of the circuit and the write mode selected by the microcode.

With the above configuration, the most preferred embodiment which can be easily carried out by those skilled in the art with reference to the present invention will be described in detail with reference to the accompanying drawings.

3 is a configuration circuit diagram of an overflow prevention apparatus according to an embodiment of the present invention. As shown in FIG. 3, the configuration of the overflow prevention apparatus according to the embodiment of the present invention is a numerical condition detection for detecting a condition in which an overflow occurs in the accumulator by inputting a negative flag, an overflow flag, a carry flag, and the like. A register write function selection circuit for enabling or disabling the decoder on which the write function is to be performed using the circuit 10 and the write mode selected by the microcode and the condition detected by the numerical condition detecting circuit 10 ( 20).

Numerical condition detection circuit 10 for detecting a condition in which an overflow occurs in an accumulator by inputting the negative flag, overflow flag, carry flag, and the like is performed. The circuit 12, a decoder 13 having a function of selecting the upper and lower detection circuits 12 of the numbers by two bits allocated to the command register, and supplying the outputs of the upper and lower detection circuits 12 of the numbers as inputs. And a four-input NAND gate 14 that receives the output to the register write function selection circuit 20.

The signed number condition detecting circuit 11 receives a negative flag and an overflow flag as inputs, and detects a condition equal to or greater than the signed number, and also receives a negative flag and an overflow flag as inputs. It consists of an XNOR gate 112 that accepts and detects a small condition of a signed number.

The upper and lower limit detection circuit 12 of the number includes a NAND gate 121 for detecting a low limit condition of a signed number, a NAND gate 122 for detecting a high limit condition of a signed number, and a sign. NAND gate 123 for detecting the lower limit condition of an unsigned number, and NAND gate 124 for detecting the upper limit condition of an unsigned number.

The register write function selection circuit 20 for selecting the register write function using the conditions detected by the numerical condition detection circuit 10 is a decoder 21 for selecting the write mode by the micro code in the overflow prevention instruction. And an input for supplying an enable signal to a decoder for selecting a register by receiving an input from an output of the decoder 21 and an output from a condition different from the condition detected by the large or small condition detecting circuit 10. The enable signal supply circuit 22 and the decoder 23 for receiving the output inverted signal of the enable signal supply circuit 22 as an enable signal and performing a register selection function by a micro code.

The enable signal supply circuit 22 inputs an output of the NAND gate 221, the four-input NAND gate 14, and the decoder 21, which are input from some other state (AnyOtherCondition) and the decoder 21. NAND gate 222 to be received as, and the NOR gate 223 receives the output of the two NAND gates 221, 222 as an input.

The operation of the overflow prevention device according to the embodiment of the present invention by the above configuration is as follows.

The XOR gate 111 detects a condition equal to or greater than the signed number by inputting the negative flag and the overflow flag of the status register, and the XOR gate 12 having the same input as the XOR gate 11 is also a sign. Detects a small condition of a number.

Thus, NAND gate 121 is the lower limit of signed numbers, NAND gate 122 is the upper limit of signed numbers, NAND gate 123 is the lower limit of unsigned numbers, and NAND gate 124 is an unsigned number. The upper limit of is detected, and the selection is made in the decoder 13 by two bits allocated from the instruction register.

Referring to the overflow prevention instruction, four types of overflows are described as the signal for selecting the NAND gates 121, 122, 123, and 124 of FIG. 3 is made by the allocated two bits of the instruction register. It can be seen that a prevention order is being devised.

When adding one signed number, two continue to subtract a signed number, three continue to add an unsigned number, and four continue to subtract an unsigned number.

When the overflow prevention instruction enters the instruction register in the fetch cycle, the code is executed as the corresponding mite. When the internal register and the data are added immediately, the procedure of the microcode of the overflow prevention instruction according to the embodiment of the present invention is performed. It is shown in FIG.

In Fig. 4, it is determined whether or not overflow has occurred according to the condition indicated by the operation result of the arithmetic logic unit. If overflow occurs, the result is not stored in the destination register. Store in the destination register.

A graph between time and accumulator value when overflow is prevented in accordance with an embodiment of the invention is shown in FIG.

For example, if the expression of the overflow prevention instruction is CLIPHS # 10, RD, the condition detection circuit 10 for the condition equal or small with the value of the status register is compared with the value of RD through subtraction with data 10 immediately. By determining whether a condition has occurred, the register write function selection circuit 20 enables or disables the decoder on which the write function is to be performed with the output of the write mode selected by the micro code in the overflow prevention instruction.

That is, when RD is greater than 10 in CLIPHS # 10, RD, a signal generated by the NAND gate 122 of the condition detection circuit 10 that is greater or equal to or smaller than that of the condition detection circuit 10 is decoded by the decoder 23 of the register write function selection circuit 20. Disable disables the write function.

On the contrary, when RD is smaller than 10, the decoder 23 of the register write function selection circuit 20 is enabled and the write function is performed to the corresponding register to accumulate.

As described above, in the embodiment of the present invention, when the purpose of the present invention is shown in FIG. 5, when the overflow is not prevented, the value of the accumulator exceeds the bit range of the register, but there is a sudden change in the value. When used, as shown in FIG. 5, an overflow prevention device having an effect of maintaining the value at a predetermined upper limit or lower limit even when a bit range of a register is exceeded may occur.

This effect of the present invention can be used in the microcomputer field with the function of the 16-bit CPU.

Claims (3)

Negative flag, overflow flag, carry flag Null carry flag is used as input to detect condition where overflow occurs in accumulator, output of the condition detection circuit of number and write mode selected by micro code And a register write function selection circuit for enabling or disabling the decoder on which the write function is to be performed. 2. A signed number condition detecting circuit according to claim 1, wherein said condition detecting circuit of said number is a condition of a signed number which detects a condition by a value of a status register and detects a condition equal to or less than a signed number, and a lower limit of the latter. And a four-input NAND gate for supplying the upper and lower limit detection circuits for detecting the upper and upper limits, the decoder functioning to select the upper and lower limit detection circuits for the number, and supplying a condition selected by the decoder to the register write function selection circuit. An overflow prevention device. The decoder of claim 1, wherein the register write function selection circuit includes a decoder for selecting a write mode from a micro code, an enable signal supply circuit for supplying an enable signal by the decoder, and a decoder for selecting a register by a micro code. Overflow prevention device, characterized in that consisting of.