SU1387000A1 - Device for generating instruction flag - Google Patents

Abstract

The invention relates to the field of computer technology and may find application in debugging computer programs of the 4th and 5th generations. The device allows the computer to automatically generate a command feature during the operation of the command when

Description

SS

(L

with

00

A command is transmitted from the memory to the processor. The device contains a block of 1 constant memory, register 2, multiplexer 3, elements OR 4, 5 and 6, triggers 7, 8 and 9, element NOT 10, elements 11 and 12, element 13 delay, encoder 14, counters 15 and 16. The command code from the device inputs is recorded on register 2 by a signal from the input passing through the element 11. The command received is analyzed using block 1, multiplexer 3, encoder 14. The result of the analysis is the code of the number of memory accesses execute the processor on this command. This code is written to counter 15 sig.

The invention relates to computing and can be used in hardware and hybrid monitors to form an indication of the start of a command.

The aim of the invention is to expand the field of application of the device.

The drawing shows a diagram of an apparatus for generating a command feature.

The device contains a block of 1 constant memory, register 2, multiplexer 3, elements OR 4-6, triggers 7-9, element NOT 10, elements 11 and 12, delay element 13, encoder 14, counters 15 and 16, initial setup input 17, information sign input 18, information input 19, interrupt sign input 20, clock input 21, direct memory access sign input 22, exchange sign input 23 and device command sign output 24.

Block I is designed to convert a command code to a binary code of the number of memory accesses for this command and has (K + 1) an output group, where K is the number of command types differing in the number of operands. The address inputs of block 1 receive the command code from register 2. At the same time, the (K + 1) - output group is assigned to et-from 1-bit (where l log2K) the type number of this command, and the i-th output group ( where, ..., K) is the binary code corresponding to this command of the number of memory accesses performed by this command.

Multiplexer 3 has (K + 2) groups of information inputs, of which the first K groups are connected to the outputs of block 1. On the (K + 1) -and group there is a code of the number of memory accesses that the processor must perform when a fault occurs in the exchange channel. with memory. The (K + 2) -and input group is connected with the code of the number of calls to the memory, which passed from the input of the device through AND 11, OR 6, and delay element 13. With each access to the memory at the input, a signal appears that passes through the AND 12 element to the subtracting input of the counter 15. When the counter 15 is reset, a signal appears at its output, which sets the trigger 9 through the OR 5 element. a command sign is established. Triggers 7, 8, the element OR 4, the element NOT 10 and the counter 16 serve to ensure the response of the device to situations such as interruption, direct memory access and a fault in the communication channel with memory 1 Il.

The processor must execute when an interruption to the computational process occurs.

The device works as follows.

When you turn on the computer system to the input 17 of the device receives a signal of the initial installation. From input 17, this signal goes to the first inputs of the OR 4 and 5 elements. At the output of the OR 4 element, a signal appears that goes to the reset inputs of the flip-flops 7 and B and resets them to zero status.

The signal from the output of the element OR 5 is fed to the input of the trigger setup 9 and sets it to one. A single potential from the output of the flip-flop 9 arrives at the output 24 of the device and is a sign that the first word that is read from the memory after its occurrence is a command. In addition, this potential arrives at the first input of the element 11. Thus, upon the initial activation of the computing system, the device generates an indication of the command at the output 24 and is prepared to receive the first command of the start-up program.

Information read from the memory comes from the computer system to a group of inputs 19 of the device. At the moment of the appearance of information on the group of inputs 19, a signal arrives at the input 18 of the information feature from the computer system. This signal arrives at the second input of the element 11. If there is a single potential at the third input of the last, a signal appears at its output, which arrives at the input of the register entry 2 and records in it information arriving at the information inputs of register 2 from the group of inputs 19 of the device . Since the first word read from the memory after turning on the computing point is 10

20

threads, is a command, register 2 is recorded the first command start program.

In addition, the signal from the output of the element 11 is fed to the first input of the element OR 6, and the signal from the output of the latter to the input of the delay element 13 and the reset input of the trigger 9, resetting it to the zero state. In this case, the signal at the output 24 of the indication of the device command 24 is lost and the And 11 element is blocked.

The command code from the register 2 output goes to the address inputs of block 1. At the i-th group of outputs of block 1, the binary code of the number of memory accesses necessary to execute this command appears, which goes to the i-th group of information inputs of multiplexer 3. The (K + 1) th output group contains the 1-bit type number of this command, which goes to the input group of the encoder 14, and the output output group has the code to the control input group of the multiplexer 3 and allowing it to pass through multiplexer 3 information, rohod at its boiling i-th group of information inputs. Information from the group 25 of the trigger 7. of the multiplexer 3 enters the group of information inputs of the counter 15 and is written into it by a signal coming from the output of the input delay element 13 of the counter 15 entry. Thus, the counter 15 contains the binary code of the number of accesses executed by the processor for this command.

Each time the memory is accessed, a signal arrives at the input 23 of the exchange attribute from the computer system, the duration of which is equal to the duration of the memory access cycle. The signal from input 23 arrives at the first input of element And 12. If there is a single potential at the second input of element 12 at its output, a signal arrives at the subtractive input of counter 15. At the same time, the contents of counter 15 decrease by one.

When the processor performs all the calls required to execute this command, counter 15 is zeroed out and a single signal appears at its output, arriving at the second input of the OR 5 element. The signal from the output of the OR 5 element sets the trigger 9, while at the output 24 is a sign of command.

full reset input counter; 16; i keeps it in the zero state.

If in the exchange channel with luiMfvibH) a malfunction occurs, such as treatment,; to a non-existent address. ::. Hi overflows on his c.i.ivojic :: .. e1h: single signal. This and i :, c.-rvnaer at the setup input trigger.:; :; U Agora input element OR 6. .i;. .i, 1m1da element OR 6 resets rpmicp 9 and starts the element 13 delay. The unit potential from the output of trigger 7 enters the (14-1) th input of the encoder i-i. 1 feed at the last output appears KIM. which allows the passage of the ma. I ul-i- 15 plexor 3 information, comm; .i oi, -uiH (iii on its (K + 1) -th ground info-kiminshnyh inputs (this information is. inetc code intimate code of the number oopaHLennii s, we t b, which the processor must perform when handling a fault communication channel with memory ) After that, the output of the delay element 13 is a signal that writes this information to the counter 15 and, having entered through the element 1, the PI 4 to the reset input of the trigger 7 resets

If a direct memory access cycle is performed in the computer system. then a signal arrives at input 22, which stands there for the duration of the call to

3Q memory from external device. This signal is fed to the input of the element NOT 10, from which the zero signal is fed to the third input of the element 11 and the second input of the element 12, blocking them. Thus, during the direct memory access cycle

35, the operation of the device is blocked, the state of the trigger 9 and the contents of the counter 15 remain unchanged, and the counter 16 is reset. If a computing process is interrupted in the computer system, then a signal arrives at the input 20 of the interrupt attribute, which is sent to the third input of the element OR 6 and the installation input of the trigger 8, setting it to one state. The signal from the output of the element OR 6 triggers the trigger 9 and starts the element 13 delay. The unified potential from the output of trigger 8 is at the (1 + 2) -th input of the cipher-1о); il At the same time, at the output of the last HOHI;., there is a code that permits the passage.

45

output to the multiplexer output 3 In addition, a single signal from the output connected to its (K + 2) -i

a group of information inputs (this information element I 12 arrives at the inverted reset input of counter 16 and allows it to count pulses coming from device 21 to the counting input of counter 16. In the absence of faults in the memory channel, the signal at input 23 disappears earlier, than the counter 16 overflows. At the same time, at the output of AND 12 element, a zero signal appears, which is fed to

The machine is the binary number of calls that the processor must perform when processing an interrupt. After that, a signal appears at the output of the delay element 13, which writes this information to the counter 15 and, after passing through the element OR 4 to the reset input: - flip-flop 8, flushes the flip-flop 8.

full reset input counter; 16; i keeps it in the zero state.

If in the exchange channel with luiMfvibH) a malfunction occurs, such as treatment,; to a non-existent address. ::. Hi overflows on his c.i.ivojic :: .. e1h: single signal. This and i :, c.-rvnaer at the setup input trigger.:; :; U Agora input element OR 6. .i;. .i, 1M1da Ele

trigger 7.

ment OR 6 resets rpmicp 9 and starts delay 13. The unit potential from the output of trigger 7 enters the (14-1) th input of the encoder i-i. 1 feed at the last output appears KIM. which allows the passage of the ma .I ul-iplexer 3 information, comm; .i oi, -uiH (iii on its (K + 1) -th ground info-kiminshnyh inputs (this information is. inetc code intimate code of the number oopaHLennii s, we t b, which the processor must perform when handling a fault communication channel with memory ) After that, the output of the delay element 13 is a signal that writes this information to the counter 15 and, having entered through the element 1, the PI 4 to the reset input of the trigger 7 resets

trigger 7.

If a direct memory access cycle is performed in the computer system. then a signal arrives at input 22, which stands there for the duration of the call to

memory from an external device. This signal is fed to the input of the element NOT 10, from which the zero signal is fed to the third input of the element 11 and the second input of the element 12, blocking them. Thus, during the direct memory access cycle

the operation of the device is blocked, the state of the trigger 9 and the contents of the counter 15 remain unchanged, and the counter 16 is reset. If a computing process is interrupted in the computer system, then a signal arrives at the input 20 of the interrupt attribute, which is sent to the third input of the element OR 6 and the installation input of the trigger 8, setting it to one state. The signal from the output of the element OR 6 triggers the trigger 9 and starts the element 13 delay. The unified potential from the output of trigger 8 is at the (1 + 2) -th input of the cipher-1о); il At the same time, at the output of the last HOHI; .should be a code that allows the passage.

55

The machine is the binary number of calls that the processor must perform when processing an interrupt. After that, a signal appears at the output of the delay element 13, which writes this information to the counter 15 and, after passing through the element OR 4 to the reset input: - flip-flop 8, flushes the flip-flop 8.

Claims (1)

An apparatus for generating an instruction flag comprising a register, a block of permanent memory, the first and second elements AND, the output of the first element AND being connected to the register recording input, characterized in that, in order to expand the field of application, a multiplexer is inserted into the device, three OR elements, three flip-flops, I two counters, an encoder, a delay element and I element are NOT, the input of the sign of the device's first memory access through the element is NOT connected to the first inputs of the first and second elements AND, the input information The device's information, information input and input of the device exchange feature are connected respectively to the second input of the first element I, to the information input of the register, to the second input of the second element I, the output of which is connected to the subtractive input of the first counter and the input of the initial installation of the second counter, the initial input device installation is connected to the first inputs of the first and second elements OR, the output of the lepBoro element OR is connected to the zero inputs of the first and second triggers, the input of the device three-way interrupt is connected to the unit input of the second trigger and the first input of the third element OR, whose output is connected to the zero input of three 0 five the second trigger and through the delay element - with the second input of the first element OR and the recording input of the first counter; the clock input of the device is connected to the counting input of the second counter, the overflow output of which is connected to the second input of the third OR element and to the single input of the first trigger, the output of which is connected to the first input of the encoder, the output of the first element I is connected to the third input of the third element OR, the output of the register is connected to the address input of the memory block, the first and second groups of outputs of the memory block These are connected respectively to the first group of information inputs of the multiplexer and to the group of inputs of the encoder, the output of which is connected to the group of control inputs of the multiplexer, the output of the second trigger is connected to the second input of the encoder, the group of inputs specifying the code number of memory access of the device is connected to the second group of information inputs multiplexer, the output of which is connected to the information input of the first counter, the overflow output of the first counter is connected to the second input of the second OR element, the output of which with one with a single input of the third flip-flop, whose output is connected to a third input of the first AND gate and the output device is a command tag.